Ð þížÅ8•( ½”Ð*chipspark,popmetal-rk3288rockchip,rk3288&7PopMetal-RK3288aliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000…/serial@ff190000�/serial@ff690000•/serial@ff1b0000�/serial@ff1c0000¥/spi@ff110000ª/spi@ff120000¯/spi@ff130000arm-pmuarm,cortex-a12-pmu0´—˜™š¿cpusÒrockchip,rk3066-smpàcpu@500ícpuarm,cortex-a12ùý'œ@5<rV acpu@501ícpuarm,cortex-a12ùý'œ@5<rV acpu@502ícpuarm,cortex-a12ùý'œ@5<rV acpu@503ícpuarm,cortex-a12ùý'œ@5<rV acpu-opp-tableoperating-points-v2iaopp-126000000t‚›€{ » opp-216000000t ßæ{ » opp-312000000t˜¾{ » opp-408000000tQ–{ » opp-600000000t#ÃF{ » opp-696000000t)|{~ðopp-816000000t0£,{B@opp-1008000000t<Ü{�opp-1200000000tG†Œ{Èàopp-1416000000tTfr{O€opp-1512000000tZJ{Ö opp-1608000000t_Ø"{™pbus simple-bus‰dma-controller@ff250000arm,pl330arm,primecellùÿ%@´�›¶5 Íapb_pclkadma-controller@ff600000arm,pl330arm,primecellùÿ`@´�›¶5Á Íapb_pclk Ùdisableddma-controller@ffb20000arm,pl330arm,primecellùÿ²@´�›¶5Á Íapb_pclka]reserved-memory‰dma-unusable@fe000000ùþoscillator fixed-clockàn6ðxin24ma timerarm,armv7-timer0´   àn64timer@ff810000rockchip,rk3288-timerùÿ�  ´H 5a  Ípclktimerdisplay-subsystemrockchip,display-subsystemK mmc@ff0c0000rockchip,rk3288-dw-mshcQðÑ€ 5ÈDrvÍbiuciuciu-driveciu-sample_ ´ ùÿ @ý€jresetÙokayv€’£ÈµÀdefaultÎ Øåòÿ mmc@ff0d0000rockchip,rk3288-dw-mshcQðÑ€ 5ÉEswÍbiuciuciu-driveciu-sample_ ´!ùÿ @ý�jreset Ùdisabledmmc@ff0e0000rockchip,rk3288-dw-mshcQðÑ€ 5ÊFtxÍbiuciuciu-driveciu-sample_ ´"ùÿ@ý‚jreset Ùdisabledmmc@ff0f0000rockchip,rk3288-dw-mshcQðÑ€ 5ËGuyÍbiuciuciu-driveciu-sample_ ´#ùÿ@ýƒjresetÙokayv€&3BÀdefaultÎ saradc@ff100000rockchip,saradcùÿ ´$P5I[Ísaradcapb_pclkýW jsaradc-apb Ùdisabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARÍspiclkapb_pclkb  gtxrx ´,ÀdefaultÎùÿ Ùdisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSÍspiclkapb_pclkb gtxrx ´-ÀdefaultÎ !ùÿ Ùdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTÍspiclkapb_pclkbgtxrx ´.ÀdefaultÎ"#$%ùÿ Ùdisabledi2c@ff140000rockchip,rk3288-i2cùÿ ´>Íi2c5MÀdefaultÎ&Ùokayà€ak8963@dasahi-kasei,ak8975ù &'´ÀdefaultÎ(q|l3g4200d@69st,l3g4200d-gyro‡ùiq—mma8452@1d fsl,mma8452ù&'´ÀdefaultÎ)i2c@ff150000rockchip,rk3288-i2cùÿ ´?Íi2c5OÀdefaultÎ*Ùokayi2c@ff160000rockchip,rk3288-i2cùÿ ´@Íi2c5PÀdefaultÎ+Ùokayi2c@ff170000rockchip,rk3288-i2cùÿ ´AÍi2c5QÀdefaultÎ,Ùokayasserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uartùÿ ´7¤®5MUÍbaudclkapb_pclkbgtxrxÀdefaultÎ-Ùokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uartùÿ ´8¤®5NVÍbaudclkapb_pclkbgtxrxÀdefaultÎ.Ùokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uartùÿi ´9¤®5OWÍbaudclkapb_pclkÀdefaultÎ/Ùokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uartùÿ ´:¤®5PXÍbaudclkapb_pclkbgtxrxÀdefaultÎ0Ùokayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uartùÿ ´;¤®5QYÍbaudclkapb_pclkb  gtxrxÀdefaultÎ1Ùokaythermal-zonesreserve_thermal»èшß2cpu_thermal»dшß2tripscpu_alert0ïpûÐôpassivea3cpu_alert1ï$øûÐôpassivea4cpu_critï_�ûÐ ôcriticalcooling-mapsmap030 ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap140 ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿgpu_thermal»dшß2tripsgpu_alert0ïpûÐôpassivea5gpu_critï_�ûÐ ôcriticalcooling-mapsmap05  6ÿÿÿÿÿÿÿÿtsadc@ff280000rockchip,rk3288-tsadcùÿ( ´%5HZÍtsadcapb_pclkýŸ jtsadc-apbÀinitdefaultsleepÎ78$7.D9QsÙokayha2ethernet@ff290000rockchip,rk3288-gmacùÿ)´šmacirqeth_wake_irqD985—fgc˜Ä]MÍstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macýB jstmmacethÙokayª:µrgmii¾input Ë;Û ñ'B@—<ÀdefaultÎ=-06usb@ff500000 generic-ehciùÿP ´5Â?>Dusb Ùdisabledusb@ff520000 generic-ohciùÿR ´)5Â?>Dusb Ùdisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2ùÿT ´5ÃÍotgNhost?? Dusb2-phyV Ùdisabledusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2ùÿX ´5ÁÍotgNotgmŽ€€@@ ?@ Dusb2-phyÙokayusb@ff5c0000 generic-ehciùÿ\ ´5Ä Ùdisabledi2c@ff650000rockchip,rk3288-i2cùÿe ´<Íi2c5LÀdefaultÎAÙokayà€pmic@1brockchip,rk808ù&B´ÀdefaultÎCD�¾ðxin32krk808-clkout2ÌEØEäEðEüEEF ,9EF—regulatorsDCDC_REG1Sgy q°‘™p©vdd_arma regulator-state-mem¸DCDC_REG2Sgy øP‘Щvdd_gpuregulator-state-memÑéB@DCDC_REG3Sg©vcc_ddrregulator-state-memÑDCDC_REG4Sgy2Z ‘2Z ©vcc_ioaregulator-state-memÑé2Z LDO_REG1Sgy2Z ‘2Z ©vcc_lana:regulator-state-memÑé2Z LDO_REG2Sgyw@‘2Z  ©vccio_sdaregulator-state-mem¸LDO_REG3SgyB@‘B@©vdd_10regulator-state-memÑéB@LDO_REG4Sgyw@‘w@ ©vcc18_lcdregulator-state-memÑéw@LDO_REG5Syw@‘2Z ©ldo5LDO_REG6SgyB@‘B@ ©vdd10_lcdregulator-state-memÑéB@LDO_REG7Sgyw@‘w@©vcc_18aFregulator-state-memÑéw@LDO_REG8Sgy2Z ‘2Z ©vcca_33aZregulator-state-memÑé2Z SWITCH_REG1Sg ©vccio_wla\regulator-state-memÑSWITCH_REG2Sg©vcc_lcdregulator-state-memÑi2c@ff660000rockchip,rk3288-i2cùÿf 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#address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-ddr-1_8vmmc-hs200-1_8vnon-removable#io-channel-cellsdmasdma-namesvdd-supplyvid-supplyst,drdy-int-pinvddio-supplyreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usassigned-clocksassigned-clock-parentstx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplybb-supplydvp-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthautorepeatgpioslinux,codelabellinux,input-typedebounce-intervalvin-supplystartup-delay-usenable-active-high