Ð þí\µ8V¼(ùV„,mecer,xms6rockchip,rk32297Mecer Xtreme Mini S6aliases=/serial@11010000E/serial@11020000M/serial@11030000U/spi@11090000cpuscpu@f00Zcpu,arm,cortex-a7fjq…”œ@¢©psci·Âcpu@f01Zcpu,arm,cortex-a7fjq…©psci·Âcpu@f02Zcpu,arm,cortex-a7fjq…©psci·Âcpu@f03Zcpu,arm,cortex-a7fjq…©psci·Âopp_table0,operating-points-v2ÊÂopp-408000000ÕQ–Ü~ðêœ@ûopp-600000000Õ#ÃFÜà˜opp-816000000Õ0£,ÜB@opp-1008000000Õ<ÜÜíØopp-1200000000ÕG†ŒÜtxopp-1296000000ÕM?dÜ7Èopp-1392000000ÕRø<Üûopp-1464000000ÕWBÞÜ\Àbus ,simple-buspdma@110f0000,arm,pl330arm,primecellf@$¢Â ;apb_pclk arm-pmu,arm,cortex-a7-pmu0LMNOGpsci,arm,psci-1.0arm,psci-0.2°smctimer,arm,armv7-timerZ0   ~n6oscillator ,fixed-clock~n6Žxin24m¡Â"display-subsystem,rockchip,display-subsystem® i2s1@100b0000(,rockchip,rk3228-i2srockchip,rk3066-i2sf @ ;i2s_clki2s_hclk¢Q»´  ¹txrxÃdefaultÑ  Ûdisabledi2s0@100c0000(,rockchip,rk3228-i2srockchip,rk3066-i2sf @ ;i2s_clki2s_hclk¢Pº´ ¹txrx Ûdisabledspdif@100d0000,rockchip,rk3228-spdiff  ¢S½ ;mclkhclk´ ¹txÃdefaultÑ  Ûdisabledi2s2@100e0000(,rockchip,rk3228-i2srockchip,rk3066-i2sf@ ;i2s_clki2s_hclk¢R¼´ ¹txrx Ûdisabledsyscon@11000000&,rockchip,rk3228-grfsysconsimple-mfdfÂ#io-domains",rockchip,rk3228-io-voltage-domainÛokayâ ðþ usb2-phy@760,rockchip,rk3228-usb2phyf` ¢Ž;phyclk Žusb480m_phy0¡ÛokayÂ<otg-port$;<= otg-bvalidotg-idlinestateÛokay'Â;host-port >  linestateÛokay'Â=usb2-phy@800,rockchip,rk3228-usb2phyf ¢�;phyclk Žusb480m_phy1¡ÛokayÂ>otg-port D  linestateÛokay'Â?host-port E  linestateÛokay'Â@serial@11010000,snps,dw-apb-uartf 7~n6¢MU;baudclkapb_pclkÃdefault Ñ2< Ûdisabledserial@11020000,snps,dw-apb-uartf 8~n6¢NV;baudclkapb_pclkÃdefaultÑ2< Ûdisabledserial@11030000,snps,dw-apb-uartf 9~n6¢OW;baudclkapb_pclkÃdefaultÑ2<Ûokayefuse@11040000,rockchip,rk3228-efusef ¢G ;pclk_efuseid@7fcpu_leakage@17fi2c@11050000,rockchip,rk3228-i2cf $;i2c¢LÃdefaultÑ Ûdisabledi2c@11060000,rockchip,rk3228-i2cf %;i2c¢MÃdefaultÑ Ûdisabledi2c@11070000,rockchip,rk3228-i2cf &;i2c¢NÃdefaultÑ Ûdisabledi2c@11080000,rockchip,rk3228-i2cf ';i2c¢OÃdefaultÑ Ûdisabledspi@11090000,rockchip,rk3228-spif  1¢AR;spiclkapb_pclkÃdefaultÑ Ûdisabledwatchdog@110a0000 ,snps,dw-wdtf  (¢b Ûdisabledpwm@110b0000,rockchip,rk3288-pwmf I¢^;pwmÃdefaultÑ Ûdisabledpwm@110b0010,rockchip,rk3288-pwmf I¢^;pwmÃdefaultÑÛokayÂLpwm@110b0020,rockchip,rk3288-pwmf I¢^;pwmÃdefaultÑ ÛokayÂMpwm@110b0030,rockchip,rk3288-pwmf 0I¢^;pwmÃdefaultÑ! Ûdisabledtimer@110c0000,,rockchip,rk3228-timerrockchip,rk3288-timerf  + ¢"a ;timerpclkclock-controller@110e0000,rockchip,rk3228-crufT#¡aHnÒÞkÃÌb$~#g¸€0£,ÍeðÑ€ðÑ€xhÀðÑ€ðÑ€xhÀÂthermal-zonescpu-thermal“d©ˆ·$tripscpu_alert0ÇpÓÐapassiveÂ%cpu_alert1Ç$øÓÐapassiveÂ&cpu_critÇ_�ÓÐ acriticalcooling-mapsmap0Þ%0ãÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1Þ&0ãÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿtsadc@11150000,rockchip,rk3228-tsadcf :¢HX;tsadcapb_pclknH~€jW òtsadc-apbÃinitdefaultsleepÑ'þ('(sÛokay?Â$hdmi-phy@12030000,rockchip,rk3228-hdmi-phyf¢m"¿;sysclkrefoclkrefpclk¡ Žhdmiphy_phyÛokayÂ,gpu@20000000",rockchip,rk3228-maliarm,mali-400f H gpgpmmupp0ppmmu0pp1ppmmu1¢ÕÕ ;buscorej~ÛokayV)iommu@20020800,rockchip,iommuf   ¢ÊÐ ;aclkifaceb Ûdisablediommu@20030480,rockchip,iommuf €@ À@ ¢ËÑ ;aclkifaceb Ûdisabledvop@20050000,rockchip,rk3228-vopf ü  ¢Ó¾Ä;aclk_vopdclk_vophclk_vopjdef òaxiahbdclko*Ûokayport endpoint@0fv+Â0iommu@20053f00,rockchip,iommuf ?  ¢ÓÄ ;aclkifacebÛokayÂ*rga@20060000(,rockchip,rk3228-rgarockchip,rk3288-rgaf  !¢ÍÓ‡;aclkhclksclkjkmn òcoreaxiahbiommu@20070800,rockchip,iommuf  ¢ÌÔ ;aclkifacebÛokayhdmi@200a0000,rockchip,rk3228-dw-hdmif < #n�†,¢l{‰;iahbisfrcecÃdefault Ñ-./j`òhdmi�,¢hdmiT#Ûokayportsportendpoint@0fv0Â+mmc@300000000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@   ¢ÈDrv;biuciuciu-driveciu-sample¬Ãdefault Ñ123Ûokay·Émmc@300100000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@   ¢ÉEsw;biuciuciu-driveciu-sample¬Ãdefault Ñ456ÛokayÔÞïü7mmc@300200000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@ ~<4`"<4` ¢ËGuy;biuciuciu-driveciu-sampleÔ0ž¬Ãdefault Ñ89:jSòresetÛokay·usb@300400002,rockchip,rk3228-usbrockchip,rk3066-usbsnps,dwc2f0 ¢Ú;otgNotgVhw€€@ �; ¢usb2-phyÛokayusb@30080000 ,generic-ehcif0  ¢×<�=¢usbÛokayusb@300a0000 ,generic-ohcif0   ¢×<�=¢usbÛokayusb@300c0000 ,generic-ehcif0   ¢Ø>�?¢usbÛokayusb@300e0000 ,generic-ohcif0  ¢Ø>�?¢usbÛokayusb@30100000 ,generic-ehcif0 B ¢Ù>�@¢usbÛokayusb@30120000 ,generic-ohcif0 C ¢Ù>�@¢usbÛokayethernet@30200000,rockchip,rk3228-gmacf0   macirq8¢~�‚€ÔoM;stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macj8 òstmmacethT#Ûokayn|~úð€†output“Ažrmii'Bmdio,snps,dwmac-mdioethernet-phy@04,ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22f¢ƒ§j?ÂAinterrupt-controller@32010000 ,arm,gic-400¹Î f22 2@ 2`   Âpinctrl,rockchip,rk3228-pinctrlT#gpio0@11110000,rockchip,gpio-bankf 3¢@ßï¹Îgpio1@11120000,rockchip,gpio-bankf 4¢Aßï¹Îgpio2@11130000,rockchip,gpio-bankf 5¢Bßï¹ÎÂHgpio3@11140000,rockchip,gpio-bankf 6¢Cßï¹ÎÂGpcfg-pull-upûÂFpcfg-pull-downÂEpcfg-pull-noneÂDpcfg-pull-none-drv-12ma$ ÂCsdmmcsdmmc-clk3CÂ1sdmmc-cmd3CÂ2sdmmc-bus4@3CCCCÂ3sdiosdio-clk3CÂ4sdio-cmd3CÂ5sdio-bus4@3CCCCÂ6emmcemmc-clk3DÂ8emmc-cmd3DÂ9emmc-bus8€3DDDDDDDDÂ:gmacrgmii-pinsð3D DDCCCC C CDDDD DDrmii-pins 3D DDCC CDDDDphy-pins 3DDhdmihdmi-hpd3EÂ.hdmii2c-xfer 3DDÂ-hdmi-cec3DÂ/i2c0i2c0-xfer 3DDÂi2c1i2c1-xfer 3DDÂi2c2i2c2-xfer 3DDÂi2c3i2c3-xfer 3DDÂspi0spi0-clk3 FÂspi0-cs03FÂspi0-tx3 FÂspi0-rx3 FÂspi0-cs13 FÂspi1spi1-clk3Fspi1-cs03Fspi1-rx3Fspi1-tx3Fspi1-cs13Fi2s1i2s1-bus�3D D D D DDDDD pwm0pwm0-pin3DÂpwm1pwm1-pin3DÂpwm2pwm2-pin3 D pwm3pwm3-pin3 DÂ!spdifspdif-tx3D tsadcotp-pin3DÂ'otp-out3DÂ(uart0uart0-xfer 3DDÂuart0-cts3DÂuart0-rts3DÂuart1uart1-xfer 3 D DÂuart1-cts3Duart1-rts3 Duart2uart2-xfer 3FDuart21-xfer 3 F DÂuart2-cts3Duart2-rts3Dusbhost-vbus-drv3DÂImemory@60000000Zmemoryf`@dc-12v-regulator,regulator-fixedAdc_12vPdv·Ž·ÂKext_gmac ,fixed-clock~sY@ Žext_gmac¡power-led ,gpio-ledsled-0 ¦G¬onsdio-pwrseq,mmc-pwrseq-simpleºHHÂ7vcc-host-regulator,regulator-fixedÆ ÙGÃdefaultÑI Avcc_hostPdÞJÂvcc-phy-regulator,regulator-fixedÆAvcc_phyvw@Žw@PdÞÂBvcc-sys-regulator,regulator-fixedAvcc_sysPdvLK@ŽLK@ÞKÂJvccio-1v8-regulator,regulator-fixed Avccio_1v8vw@Žw@PÞJÂvccio-3v3-regulator,regulator-fixed Avccio_3v3v2Z Ž2Z PÞJ vdd-arm-regulator,pwm-regulatoréLa¨îJAvdd_armv~ðŽ\ÀPdÂvdd-log-regulator,pwm-regulatoréMa¨îJAvdd_logvB@ŽÖ PdÂ) #address-cells#size-cellsinterrupt-parentcompatiblemodelserial0serial1serial2spi0device_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksenable-methodcpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterrupts#dma-cellsarm,pl330-periph-burstclock-namesinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsportsdmasdma-namespinctrl-namespinctrl-0statusvccio1-supplyvccio2-supplyvccio4-supplyinterrupt-names#phy-cellsphy-supplyreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-modemali-supply#iommu-cellsiommusremote-endpointassigned-clock-parentsphysphy-namesfifo-depthcap-mmc-highspeeddisable-wpbus-widthcap-sd-highspeedcap-sdio-irqmmc-pwrseqnon-removablevqmmc-supplymax-frequencyrockchip,default-sample-phasedr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeclock_in_outphy-handlephy-modephy-is-integratedinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltgpiosdefault-statereset-gpiosenable-active-highgpiovin-supplypwmspwm-supply