Ð þí\E8VL(ùV$,rockchip,rk3229-evbrockchip,rk3229!7Rockchip RK3229 Evaluation boardaliases=/serial@11010000E/serial@11020000M/serial@11030000U/spi@11090000cpuscpu@f00Zcpu,arm,cortex-a7fjq…”œ@¢©psci·Âcpu@f01Zcpu,arm,cortex-a7fjq…©psci·Âcpu@f02Zcpu,arm,cortex-a7fjq…©psci·Âcpu@f03Zcpu,arm,cortex-a7fjq…©psci·Âopp_table0,operating-points-v2ÊÂopp-408000000ÕQ–Ü~ðêœ@ûopp-600000000Õ#ÃFÜà˜opp-816000000Õ0£,ÜB@opp-1008000000Õ<ÜÜíØopp-1200000000ÕG†ŒÜtxopp-1296000000ÕM?dÜ7Èopp-1392000000ÕRø<Üûopp-1464000000ÕWBÞÜ\Àbus ,simple-buspdma@110f0000,arm,pl330arm,primecellf@$¢Â ;apb_pclk arm-pmu,arm,cortex-a7-pmu0LMNOGpsci,arm,psci-1.0arm,psci-0.2°smctimer,arm,armv7-timerZ0   ~n6oscillator ,fixed-clock~n6Žxin24m¡Â"display-subsystem,rockchip,display-subsystem® i2s1@100b0000(,rockchip,rk3228-i2srockchip,rk3066-i2sf @ ;i2s_clki2s_hclk¢Q»´  ¹txrxÃdefaultÑ  Ûdisabledi2s0@100c0000(,rockchip,rk3228-i2srockchip,rk3066-i2sf @ ;i2s_clki2s_hclk¢Pº´ ¹txrx Ûdisabledspdif@100d0000,rockchip,rk3228-spdiff  ¢S½ ;mclkhclk´ ¹txÃdefaultÑ  Ûdisabledi2s2@100e0000(,rockchip,rk3228-i2srockchip,rk3066-i2sf@ ;i2s_clki2s_hclk¢R¼´ ¹txrx Ûdisabledsyscon@11000000&,rockchip,rk3228-grfsysconsimple-mfdfÂ#io-domains",rockchip,rk3228-io-voltage-domainÛokayâ ðþ usb2-phy@760,rockchip,rk3228-usb2phyf` ¢Ž;phyclk Žusb480m_phy0¡ÛokayÂ:otg-port$;<= otg-bvalidotg-idlinestateÛokayÂ9host-port >  linestateÛokay'Â;usb2-phy@800,rockchip,rk3228-usb2phyf ¢�;phyclk Žusb480m_phy1¡ÛokayÂ<otg-port D  linestateÛokay'Â=host-port E  linestateÛokay'Â>serial@11010000,snps,dw-apb-uartf 7~n6¢MU;baudclkapb_pclkÃdefault Ñ2< Ûdisabledserial@11020000,snps,dw-apb-uartf 8~n6¢NV;baudclkapb_pclkÃdefaultÑ2< Ûdisabledserial@11030000,snps,dw-apb-uartf 9~n6¢OW;baudclkapb_pclkÃdefaultÑ2<Ûokayefuse@11040000,rockchip,rk3228-efusef ¢G ;pclk_efuseid@7fcpu_leakage@17fi2c@11050000,rockchip,rk3228-i2cf $;i2c¢LÃdefaultÑ Ûdisabledi2c@11060000,rockchip,rk3228-i2cf %;i2c¢MÃdefaultÑ Ûdisabledi2c@11070000,rockchip,rk3228-i2cf &;i2c¢NÃdefaultÑ Ûdisabledi2c@11080000,rockchip,rk3228-i2cf ';i2c¢OÃdefaultÑ Ûdisabledspi@11090000,rockchip,rk3228-spif  1¢AR;spiclkapb_pclkÃdefaultÑ Ûdisabledwatchdog@110a0000 ,snps,dw-wdtf  (¢b Ûdisabledpwm@110b0000,rockchip,rk3288-pwmf I¢^;pwmÃdefaultÑ Ûdisabledpwm@110b0010,rockchip,rk3288-pwmf I¢^;pwmÃdefaultÑÛokayÂKpwm@110b0020,rockchip,rk3288-pwmf I¢^;pwmÃdefaultÑ ÛokayÂLpwm@110b0030,rockchip,rk3288-pwmf 0I¢^;pwmÃdefaultÑ! Ûdisabledtimer@110c0000,,rockchip,rk3228-timerrockchip,rk3288-timerf  + ¢"a ;timerpclkclock-controller@110e0000,rockchip,rk3228-crufT#¡aHnÒÞkÃÌb$~#g¸€0£,ÍeðÑ€ðÑ€xhÀðÑ€ðÑ€xhÀÂthermal-zonescpu-thermal“d©ˆ·$tripscpu_alert0ÇpÓÐapassiveÂ%cpu_alert1Ç$øÓÐapassiveÂ&cpu_critÇ_�ÓÐ acriticalcooling-mapsmap0Þ%0ãÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1Þ&0ãÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿtsadc@11150000,rockchip,rk3228-tsadcf :¢HX;tsadcapb_pclknH~€jW òtsadc-apbÃinitdefaultsleepÑ'þ('(sÛokay?Â$hdmi-phy@12030000,rockchip,rk3228-hdmi-phyf¢m"¿;sysclkrefoclkrefpclk¡ Žhdmiphy_phy ÛdisabledÂ+gpu@20000000",rockchip,rk3228-maliarm,mali-400f H gpgpmmupp0ppmmu0pp1ppmmu1¢ÕÕ ;buscorej~ Ûdisablediommu@20020800,rockchip,iommuf   ¢ÊÐ ;aclkifaceV Ûdisablediommu@20030480,rockchip,iommuf €@ À@ ¢ËÑ ;aclkifaceV Ûdisabledvop@20050000,rockchip,rk3228-vopf ü  ¢Ó¾Ä;aclk_vopdclk_vophclk_vopjdef òaxiahbdclkc) Ûdisabledport endpoint@0fj*Â/iommu@20053f00,rockchip,iommuf ?  ¢ÓÄ ;aclkifaceV ÛdisabledÂ)rga@20060000(,rockchip,rk3228-rgarockchip,rk3288-rgaf  !¢ÍÓ‡;aclkhclksclkjkmn òcoreaxiahbiommu@20070800,rockchip,iommuf  ¢ÌÔ ;aclkifaceV Ûdisabledhdmi@200a0000,rockchip,rk3228-dw-hdmif < #n�z+¢l{‰;iahbisfrcecÃdefault Ñ,-.j`òhdmi‘+–hdmiT# Ûdisabledportsportendpoint@0fj/Â*mmc@300000000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@   ¢ÈDrv;biuciuciu-driveciu-sample Ãdefault Ñ012 Ûdisabledmmc@300100000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@   ¢ÉEsw;biuciuciu-driveciu-sample Ãdefault Ñ345 Ûdisabledmmc@300200000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@ ~<4`«<4` ¢ËGuy;biuciuciu-driveciu-sample¹Þ Ãdefault Ñ678jSòresetÛokayáóusb@300400002,rockchip,rk3228-usbrockchip,rk3066-usbsnps,dwc2f0 ¢Ú;otgotg *€€@ ‘9 –usb2-phyÛokayusb@30080000 ,generic-ehcif0  ¢×:‘;–usbÛokayusb@300a0000 ,generic-ohcif0   ¢×:‘;–usbÛokayusb@300c0000 ,generic-ehcif0   ¢Ø<‘=–usbÛokayusb@300e0000 ,generic-ohcif0  ¢Ø<‘=–usbÛokayusb@30100000 ,generic-ehcif0 B ¢Ù<‘>–usbÛokayusb@30120000 ,generic-ohcif0 C ¢Ù<‘>–usbÛokayethernet@30200000,rockchip,rk3228-gmacf0   macirq8¢~�‚€ÔoM;stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macj8 òstmmacethT#Ûokayn}~ z?}9input'@FrgmiiÃdefaultÑA OB_ u'B@Š0“interrupt-controller@32010000 ,arm,gic-400œ± f22 2@ 2`   Âpinctrl,rockchip,rk3228-pinctrlT#gpio0@11110000,rockchip,gpio-bankf 3¢@ÂÒœ±gpio1@11120000,rockchip,gpio-bankf 4¢AÂÒœ±gpio2@11130000,rockchip,gpio-bankf 5¢BÂÒœ±ÂBgpio3@11140000,rockchip,gpio-bankf 6¢CÂÒœ±ÂGpcfg-pull-upÞÂFpcfg-pull-downëÂEpcfg-pull-noneúÂDpcfg-pull-none-drv-12ma ÂCsdmmcsdmmc-clkCÂ0sdmmc-cmdCÂ1sdmmc-bus4@CCCCÂ2sdiosdio-clkCÂ3sdio-cmdCÂ4sdio-bus4@CCCCÂ5emmcemmc-clkDÂ6emmc-cmdDÂ7emmc-bus8€DDDDDDDDÂ8gmacrgmii-pinsðD DDCCCC C CDDDD DDÂArmii-pins D DDCC CDDDDphy-pins DDhdmihdmi-hpdEÂ-hdmii2c-xfer DDÂ,hdmi-cecDÂ.i2c0i2c0-xfer DDÂi2c1i2c1-xfer DDÂi2c2i2c2-xfer DDÂi2c3i2c3-xfer DDÂspi0spi0-clk FÂspi0-cs0FÂspi0-tx FÂspi0-rx FÂspi0-cs1 FÂspi1spi1-clkFspi1-cs0Fspi1-rxFspi1-txFspi1-cs1Fi2s1i2s1-bus�D D D D DDDDD pwm0pwm0-pinDÂpwm1pwm1-pinDÂpwm2pwm2-pin D pwm3pwm3-pin DÂ!spdifspdif-txD tsadcotp-pinDÂ'otp-outDÂ(uart0uart0-xfer DDÂuart0-ctsDÂuart0-rtsDÂuart1uart1-xfer  D DÂuart1-ctsDuart1-rts Duart2uart2-xfer FDÂuart21-xfer  F Duart2-ctsDuart2-rtsDkeyspwr-keyFÂMusbhost-vbus-drvDÂHmemory@60000000Zmemoryf`@dc-12v-regulator,regulator-fixed$dc_12v3GY·q·ÂJext_gmac ,fixed-clock~sY@ Žext_gmac¡Â?vcc-host-regulator,regulator-fixed‰ ZGÃdefaultÑH $vcc_host3GœIÂvcc-phy-regulator,regulator-fixed‰$vcc_phyYw@qw@3GœÂ@vcc-sys-regulator,regulator-fixed$vcc_sys3GYLK@qLK@œJÂIvccio-1v8-regulator,regulator-fixed $vccio_1v8Yw@qw@3œIÂvccio-3v3-regulator,regulator-fixed $vccio_3v3Y2Z q2Z 3œI vdd-arm-regulator,pwm-regulator§Ka¨¬I$vdd_armY~ðq\À3GÂvdd-log-regulator,pwm-regulator§La¨¬I$vdd_logYB@qÖ 3Ggpio_keys ,gpio-keys·ÃdefaultÑMpower-keyÂGPIO Key Power ÈGÎtÙdë #address-cells#size-cellsinterrupt-parentcompatiblemodelserial0serial1serial2spi0device_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksenable-methodcpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterrupts#dma-cellsarm,pl330-periph-burstclock-namesinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsportsdmasdma-namespinctrl-namespinctrl-0statusvccio1-supplyvccio2-supplyvccio4-supplyinterrupt-names#phy-cellsphy-supplyreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-mode#iommu-cellsiommusremote-endpointassigned-clock-parentsphysphy-namesfifo-depthmax-frequencybus-widthrockchip,default-sample-phasecap-mmc-highspeednon-removabledr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeclock_in_outphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltenable-active-highvin-supplypwmspwm-supplyautorepeatlabelgpioslinux,codedebounce-intervalwakeup-source