Ð þíTR8Nè(jN°!,Rockchip RK3228 Evaluation board$2rockchip,rk3228-evbrockchip,rk3228aliases=/serial@11010000E/serial@11020000M/serial@11030000U/spi@11090000cpuscpu@f00Zcpu2arm,cortex-a7fjq…”œ@¢©psci·cpu@f01Zcpu2arm,cortex-a7fjq…©psci·cpu@f02Zcpu2arm,cortex-a7fjq…©psci·cpu@f03Zcpu2arm,cortex-a7fjq…©psci·opp_table02operating-points-v2¿·opp-408000000ÊQ–Ñ~ðßœ@ðopp-600000000Ê#ÃFÑà˜opp-816000000Ê0£,ÑB@opp-1008000000Ê<ÜÑíØopp-1200000000ÊG†ŒÑtxbus 2simple-busüpdma@110f00002arm,pl330arm,primecellf@¢Â 0apb_pclk· arm-pmu2arm,cortex-a7-pmu0LMNO<psci2arm,psci-1.0arm,psci-0.2°smctimer2arm,armv7-timerO0   sn6oscillator 2fixed-clocksn6ƒxin24m–·display-subsystem2rockchip,display-subsystem£i2s1@100b0000(2rockchip,rk3228-i2srockchip,rk3066-i2sf @ 0i2s_clki2s_hclk¢Q»©  ®txrx¸defaultÆ  Ðdisabledi2s0@100c0000(2rockchip,rk3228-i2srockchip,rk3066-i2sf @ 0i2s_clki2s_hclk¢Pº© ®txrx Ðdisabledspdif@100d00002rockchip,rk3228-spdiff  ¢S½ 0mclkhclk© ®tx¸defaultÆ  Ðdisabledi2s2@100e0000(2rockchip,rk3228-i2srockchip,rk3066-i2sf@ 0i2s_clki2s_hclk¢R¼© ®txrx Ðdisabledsyscon@11000000&2rockchip,rk3228-grfsysconsimple-mfdf·io-domains"2rockchip,rk3228-io-voltage-domain Ðdisabledusb2-phy@7602rockchip,rk3228-usb2phyf` ¢Ž0phyclk ƒusb480m_phy0– Ðdisabled·6otg-port$;<=×otg-bvalidotg-idlinestateç Ðdisabled·5host-port > ×linestateç Ðdisabled·7usb2-phy@8002rockchip,rk3228-usb2phyf ¢�0phyclk ƒusb480m_phy1– Ðdisabled·8otg-port D ×linestateç Ðdisabled·9host-port E ×linestateç Ðdisabled·:serial@110100002snps,dw-apb-uartf 7sn6¢MU0baudclkapb_pclk¸default Æ òü Ðdisabledserial@110200002snps,dw-apb-uartf 8sn6¢NV0baudclkapb_pclk¸defaultÆòü Ðdisabledserial@110300002snps,dw-apb-uartf 9sn6¢OW0baudclkapb_pclk¸defaultÆòüÐokayefuse@110400002rockchip,rk3228-efusef ¢G 0pclk_efuseid@7fcpu_leakage@17fi2c@110500002rockchip,rk3228-i2cf $0i2c¢L¸defaultÆ Ðdisabledi2c@110600002rockchip,rk3228-i2cf %0i2c¢M¸defaultÆ Ðdisabledi2c@110700002rockchip,rk3228-i2cf &0i2c¢N¸defaultÆ Ðdisabledi2c@110800002rockchip,rk3228-i2cf '0i2c¢O¸defaultÆ Ðdisabledspi@110900002rockchip,rk3228-spif  1¢AR0spiclkapb_pclk¸defaultÆ Ðdisabledwatchdog@110a0000 2snps,dw-wdtf  (¢b Ðdisabledpwm@110b00002rockchip,rk3288-pwmf  ¢^0pwm¸defaultÆ Ðdisabledpwm@110b00102rockchip,rk3288-pwmf  ¢^0pwm¸defaultÆ Ðdisabledpwm@110b00202rockchip,rk3288-pwmf  ¢^0pwm¸defaultÆ Ðdisabledpwm@110b00302rockchip,rk3288-pwmf 0 ¢^0pwm¸defaultÆ Ðdisabledtimer@110c0000,2rockchip,rk3228-timerrockchip,rk3288-timerf  + ¢a 0timerpclkclock-controller@110e00002rockchip,rk3228-cruf–!H.ÒÞkÃÌb$>#g¸€0£,ÍeðÑ€ðÑ€xhÀðÑ€ðÑ€xhÀ·thermal-zonescpu-thermalSdiˆw tripscpu_alert0‡p“Ðapassive·!cpu_alert1‡$ø“Ðapassive·"cpu_crit‡_�“Ð acriticalcooling-mapsmap0ž!0£ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1ž"0£ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿtsadc@111500002rockchip,rk3228-tsadcf :¢HX0tsadcapb_pclk.H>€jW ²tsadc-apb¸initdefaultsleepÆ#¾$È#ÒèsÐokayÿ· hdmi-phy@120300002rockchip,rk3228-hdmi-phyf¢m¿0sysclkrefoclkrefpclk– ƒhdmiphy_phyç Ðdisabled·'gpu@20000000"2rockchip,rk3228-maliarm,mali-400f H×gpgpmmupp0ppmmu0pp1ppmmu1¢ÕÕ 0buscorej~ Ðdisablediommu@200208002rockchip,iommuf   ¢ÊÐ 0aclkiface1 Ðdisablediommu@200304802rockchip,iommuf €@ À@ ¢ËÑ 0aclkiface1 Ðdisabledvop@200500002rockchip,rk3228-vopf ü  ¢Ó¾Ä0aclk_vopdclk_vophclk_vopjdef ²axiahbdclk>% Ðdisabledport·endpoint@0fE&·+iommu@20053f002rockchip,iommuf ?  ¢ÓÄ 0aclkiface1 Ðdisabled·%rga@20060000(2rockchip,rk3228-rgarockchip,rk3288-rgaf  !¢ÍÓ‡0aclkhclksclkjkmn ²coreaxiahbiommu@200708002rockchip,iommuf  ¢ÌÔ 0aclkiface1 Ðdisabledhdmi@200a00002rockchip,rk3228-dw-hdmif ü #.�U'¢l{‰0iahbisfrcec¸default Æ()*j`²hdmil'qhdmi Ðdisabledportsportendpoint@0fE+·&mmc@3000000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@   ¢ÈDrv0biuciuciu-driveciu-sample{¸default Æ,-. Ðdisabledmmc@3001000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@   ¢ÉEsw0biuciuciu-driveciu-sample{¸default Æ/01 Ðdisabledmmc@3002000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@ s<4`†<4` ¢ËGuy0biuciuciu-driveciu-sample”žž{¸default Æ234jS²resetÐokay¼ÎÛæusb@3004000022rockchip,rk3228-usbrockchip,rk3066-usbsnps,dwc2f0 ¢Ú0otgôotgü€€@ l5 qusb2-phy Ðdisabledusb@30080000 2generic-ehcif0  ¢×6l7qusb Ðdisabledusb@300a0000 2generic-ohcif0   ¢×6l7qusb Ðdisabledusb@300c0000 2generic-ehcif0   ¢Ø8l9qusb Ðdisabledusb@300e0000 2generic-ohcif0  ¢Ø8l9qusb Ðdisabledusb@30100000 2generic-ehcif0 B ¢Ù8l:qusb Ðdisabledusb@30120000 2generic-ohcif0 C ¢Ù8l:qusb Ðdisabledethernet@302000002rockchip,rk3228-gmacf0  ×macirq8¢~�‚€ÔoM0stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macj8 ²stmmacethÐokay.|>úð€,output9;DrmiiM<mdio2snps,dwmac-mdioethernet-phy@042ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22f¢ƒj?X·<interrupt-controller@32010000 2arm,gic-400j f22 2@ 2`   ·pinctrl2rockchip,rk3228-pinctrlügpio0@111100002rockchip,gpio-bankf 3¢@� jgpio1@111200002rockchip,gpio-bankf 4¢A� jgpio2@111300002rockchip,gpio-bankf 5¢B� jgpio3@111400002rockchip,gpio-bankf 6¢C� jpcfg-pull-up¬·@pcfg-pull-down¹·?pcfg-pull-noneÈ·>pcfg-pull-none-drv-12maÕ ·=sdmmcsdmmc-clkä=·,sdmmc-cmdä=·-sdmmc-bus4@ä====·.sdiosdio-clkä=·/sdio-cmdä=·0sdio-bus4@ä====·1emmcemmc-clkä>·2emmc-cmdä>·3emmc-bus8€ä>>>>>>>>·4gmacrgmii-pinsðä> >>==== = =>>>> >>rmii-pins ä> >>== =>>>>phy-pins ä>>hdmihdmi-hpdä?·)hdmii2c-xfer ä>>·(hdmi-cecä>·*i2c0i2c0-xfer ä>>·i2c1i2c1-xfer ä>>·i2c2i2c2-xfer ä>>·i2c3i2c3-xfer ä>>·spi0spi0-clkä @·spi0-cs0ä@·spi0-txä @·spi0-rxä @·spi0-cs1ä @·spi1spi1-clkä@spi1-cs0ä@spi1-rxä@spi1-txä@spi1-cs1ä@i2s1i2s1-bus�ä> > > > >>>>>· pwm0pwm0-pinä>·pwm1pwm1-pinä>·pwm2pwm2-pinä >·pwm3pwm3-pinä >·spdifspdif-txä>· tsadcotp-pinä>·#otp-outä>·$uart0uart0-xfer ä>>· uart0-ctsä>· uart0-rtsä>·uart1uart1-xfer ä > >·uart1-ctsä>uart1-rtsä >uart2uart2-xfer ä@>·uart21-xfer ä @ >uart2-ctsä>uart2-rtsä>memory@60000000Zmemoryf`@vcc-phy-regulator2regulator-fixedòvcc_phyw@,w@DX·; #address-cells#size-cellsinterrupt-parentmodelcompatibleserial0serial1serial2spi0device_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksenable-methodphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterrupts#dma-cellsarm,pl330-periph-burstclock-namesinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsportsdmasdma-namespinctrl-namespinctrl-0statusinterrupt-names#phy-cellsreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarity#iommu-cellsiommusremote-endpointassigned-clock-parentsphysphy-namesfifo-depthmax-frequencybus-widthrockchip,default-sample-phasecap-mmc-highspeedmmc-ddr-1_8vdisable-wpnon-removabledr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeclock_in_outphy-supplyphy-modephy-handlephy-is-integratedinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsenable-active-highregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-on