Ð þí_j8Y4(6Xü,radxa,rockrockchip,rk3188 7Radxa Rockaliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/mmc@1021c000f/mmc@10214000l/mmc@10218000r/serial@10124000z/serial@10126000‚/serial@20064000Š/serial@20068000’/spi@20070000—/spi@20074000bus ,simple-busœdma-controller@20018000,arm,pl330arm,primecell£ €@§²½ØïÀ öapb_pclk:dma-controller@2001c000,arm,pl330arm,primecell£ À@§²½ØïÀ öapb_pclk  disableddma-controller@20078000,arm,pl330arm,primecell£ €@§²½ØïÁ öapb_pclkoscillator ,fixed-clockn6!.xin24mgpu@10090000",rockchip,rk3188-maliarm,mali-400£ ïÅÅ öbuscoreAÅQõáfx okayx§ 5mgpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3}cache-controller@10138000,arm,pl310-cache£€‹™4scu@1013c000,arm,cortex-a9-scu£Àglobal-timer@1013c200,arm,cortex-a9-global-timer£  § ï  disabledlocal-timer@1013c600,arm,cortex-a9-twd-timer£Æ  § ïinterrupt-controller@1013d000,arm,cortex-a9-gic¥º£ÐÁserial@10124000&,rockchip,rk3188-uartsnps,dw-apb-uart£@ §"ËÕöbaudclkapb_pclkï@L okayâdefaultðserial@10126000&,rockchip,rk3188-uartsnps,dw-apb-uart£` §#ËÕöbaudclkapb_pclkïAM okayâdefaultðqos@1012d000,syscon£Ð qos@1012e000,syscon£à qos@1012f000,syscon£ð qos@1012f080,syscon£ð€ qos@1012f100,syscon£ñ qos@1012f180,syscon£ñ€ qos@1012f200,syscon£ò qos@1012f280,syscon£ò€ usb@10180000,rockchip,rk3066-usbsnps,dwc2£ §ïÃöotgúotg#€€@@ 2 7usb2-phy okayusb@101c0000 ,snps,dwc2£ §ïÉöotgúhost2 7usb2-phy okayethernet@10204000,rockchip,rk3188-emac£ @< §AïÄD öhclkmacrefNdXrmii okayâdefault ð a e ethernet-phy@0£§ mmc@10214000,rockchip,rk2928-dw-mshc£!@ §ïÀHöbiuciupurx-txfQŠreset okayâdefault𖢬¾Ïmmc@10218000,rockchip,rk2928-dw-mshc£!€ §ïÁIöbiuciupurx-txfRŠreset  disabledmmc@1021c000,rockchip,rk2928-dw-mshc£!À §ïÂJöbiuciupurx-txfSŠreset  disabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd£ @<reboot-mode,syscon-reboot-modeÚ@áRBÃíRBÃûRBà  RBÃpower-controller!,rockchip,rk3188-power-controllerpower-domain@7£hïÃľ¿ÍÎOÊÐÈÑÉÒ+power-domain@6£ ïÎÍØ×+power-domain@8£ïÅ+grf@20008000,syscon£ €i2c@2002d000,rockchip,rk3188-i2c£ Ð §(Aöi2cïP  disabledâdefaultði2c@2002f000,rockchip,rk3188-i2c£ ð §)AïQöi2c okayâdefaultð€rtc@51,haoyu,hym8563£Q§ âdefaultð!.xin32kact8846@5a,active-semi,act8846£Z okay2âdefaultð J!U!`!k!v"‚!Ž!regulatorsREG1šVCC_DDR©O€ÁO€ÙREG2šVDD_LOG©B@ÁB@ÙREG3šVDD_ARM© YøÁ™pÙ6REG4šVCC_IO©2Z Á2Z Ù"REG5šVDD_10©B@ÁB@ÙREG6 šVDD_HDMI©&% Á&% ÙREG7šVCC_18©w@Áw@ÙREG8šVCCA_33©2Z Á2Z ÙREG9 šVCC_RMII©2Z Á2Z  REG10 šVCCIO_WL©2Z Á2Z ÙREG11 šVCC18_IO©w@Áw@ÙREG12šVCC_28©*¹€Á*¹€Ùpwm@20030000,rockchip,rk2928-pwm£ íïF  disabledâdefaultð#pwm@20030010,rockchip,rk2928-pwm£ íïF okayâdefaultð$watchdog@2004c000 ,rockchip,rk3188-wdtsnps,dw-wdt£ ÀïK §3 okaypwm@20050020,rockchip,rk2928-pwm£  íïG okayâdefaultð%pwm@20050030,rockchip,rk2928-pwm£ 0íïG okayâdefaultð&i2c@20056000,rockchip,rk3188-i2c£ ` §*AïRöi2c  disabledâdefaultð'i2c@2005a000,rockchip,rk3188-i2c£   §+AïSöi2c  disabledâdefaultð(i2c@2005e000,rockchip,rk3188-i2c£ à §4AïTöi2c  disabledâdefaultð)serial@20064000&,rockchip,rk3188-uartsnps,dw-apb-uart£ @ §$ËÕöbaudclkapb_pclkïBN okayâdefaultð*serial@20068000&,rockchip,rk3188-uartsnps,dw-apb-uart£ € §%ËÕöbaudclkapb_pclkïCO okayâdefaultð+saradc@2006c000,rockchip,saradc£ À §øïGJösaradcapb_pclkfW Šsaradc-apb  disabledspi@20070000(,rockchip,rk3188-spirockchip,rk3066-spiïEHöspiclkapb_pclk §&£ p  utxrx  disabledâdefaultð,-./spi@20074000(,rockchip,rk3188-spirockchip,rk3066-spiïFIöspiclkapb_pclk §'£ @p  utxrx  disabledâdefaultð0123cpus rockchip,rk3066-smpcpu@0cpu,arm,cortex-a9$4£5œ@ïC5fW6cpu@1cpu,arm,cortex-a9$4£C5fW6cpu@2cpu,arm,cortex-a9$4£C5fW6cpu@3cpu,arm,cortex-a9$4£C5fW6opp_table0,operating-points-v2b5opp-312000000m˜¾t Yø‚œ@opp-504000000m ntHopp-600000000m#ÃFt~ð“opp-816000000m0£,tà˜opp-1008000000m<Ütg8opp-1200000000mG†ŒtŒ0opp-1416000000mTfrtÐopp-1608000000m_Ø"t™pdisplay-subsystem,rockchip,display-subsystemŸ78sram@10080000 ,mmio-sram£€ œ€smp-sram@0,rockchip,rk3066-smp-sram£Pvop@1010c000,rockchip,rk3188-vop£À § ïþÍöaclk_vopdclk_vophclk_vop}fdef Šaxiahbdclk  disabledport7vop@1010e000,rockchip,rk3188-vop£à §ïÄ¿Îöaclk_vopdclk_vophclk_vop}fghi Šaxiahbdclk  disabledport8timer@2000e000,,rockchip,rk3188-timerrockchip,rk3288-timer£ à  §.ïEW öpclktimertimer@200380a0,,rockchip,rk3188-timerrockchip,rk3288-timer£ €   §@ïBZ öpclktimeri2s@1011a000(,rockchip,rk3188-i2srockchip,rk3066-i2s£   § âdefaultð9ïKÆöi2s_clki2s_hclkp::utxrx¥ÀÚ  disabledsound@1011e000,,rockchip,rk3188-spdifrockchip,rk3066-spdif£à ÚïNÅ ömclkhclkp:utx § âdefaultð; okay@clock-controller@20000000,rockchip,rk3188-cru£ A!ëefuse@20010000,rockchip,rk3188-efuse£ @ï[ öpclk_efusecpu_leakage@17£phy0,rockchip,rk3188-usb-phyrockchip,rk3288-usb-phyA okayusb-phy@10cø£ ïQöphyclk!usb-phy@11cø£ïRöphyclk!pinctrl,rockchip,rk3188-pinctrlA<œgpio0@2000a000,rockchip,rk3188-gpio-bank0£   §6ïU ¥ºgpio1@2003c000,rockchip,gpio-bank£ À §7ïV ¥ºgpio2@2003e000,rockchip,gpio-bank£ à §8ïW ¥ºCgpio3@20080000,rockchip,gpio-bank£  §9ïX ¥ºpcfg_pull_up,>pcfg_pull_down9pcfg_pull_noneH=emmcemmc-clkU=emmc-cmdU>emmc-rstU=emacemac-xfer€U======== emac-mdio U== i2c0i2c0-xfer U==i2c1i2c1-xfer U==i2c2i2c2-xfer U=='i2c3i2c3-xfer U==(i2c4i2c4-xfer U==)lcdc1lcdc1-dclkU=lcdc1-denU=lcdc1-hsyncU=lcdc1-vsyncU=lcdc1-rgb24€U========= = = = = ===========pwm0pwm0-outU=#pwm1pwm1-outU=$pwm2pwm2-outU=%pwm3pwm3-outU=&spi0spi0-clkU>,spi0-cs0U>/spi0-txU>-spi0-rxU>.spi0-cs1U>spi1spi1-clkU>0spi1-cs0U>3spi1-rxU>2spi1-txU>1spi1-cs1U>uart0uart0-xfer U>=uart0-ctsU=uart0-rtsU=uart1uart1-xfer U>=uart1-ctsU=uart1-rtsU=uart2uart2-xfer U> =*uart3uart3-xfer U > =+uart3-ctsU =uart3-rtsU =sd0sd0-clkU=sd0-cmdU=sd0-cdU=sd0-wpU =sd0-pwrU=sd0-bus-width1U=sd0-bus-width4@U====sdmmc-pwrU=Esd1sd1-clkU=sd1-cmdU=sd1-cdU=sd1-wpU=sd1-bus-width1U=sd1-bus-width4@U====i2s0i2s0-bus`U======9spdifspdif-txU=;pcfg-output-lowc?act8846act8846-dvs0-ctlU? hym8563rtc-intU>lan8720aphy-intU> ir-receiverir-recv-pinU =Busbhost-vbus-drvU=Fotg-vbus-drvU=Dmemory@60000000memory£`€gpio-keys ,gpio-keysnpower ytŠGPIO Key Power�¡¯dgpio-leds ,gpio-ledsled-0Šrock:green:user1 y Áoffled-1Šrock:blue:user2 yÁoffled-2Šrock:red:power yÁoffsound,simple-audio-cardÏSPDIFsimple-audio-card,dai-link@1cpuæ@codecæAspdif-out,linux,spdif-ditÚAir-receiver,gpio-ir-receiver y âdefaultðBusb-otg-regulator,regulator-fixedð CâdefaultðD šotg-vbus©LK@ÁLK@Ùsdmmc-regulator,regulator-fixed šsdmmc-supply©2Z Á2Z  âdefaultðE† +"usb-host-regulator,regulator-fixedð âdefaultðF šhost-pwr©LK@ÁLK@Ùvsys-regulator,regulator-fixedšvsys©LK@ÁLK@! #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1rangesreginterrupts#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclocksclock-namesphandlestatusclock-frequency#clock-cellsclock-output-namesassigned-clocksassigned-clock-ratesresetsinterrupt-namespower-domainscache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthpinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modephyphy-supplydmasdma-namesfifo-depthreset-namesvmmc-supplybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qossystem-power-controllervp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-on#pwm-cells#io-channel-cellsenable-methoddevice_typenext-level-cacheclock-latencyoperating-points-v2cpu-supplyopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cells#phy-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disablerockchip,pinsoutput-lowautorepeatgpioslinux,codelabellinux,input-typewakeup-sourcedebounce-intervaldefault-statesimple-audio-card,namesound-daienable-active-highgpioregulator-boot-onstartup-delay-usvin-supply