Ð þíik8cx(óc@(,chipspark,rayeager-px2rockchip,rk3066a 7Rayeager PX2aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/mmc@1021c000f/mmc@10214000l/mmc@10218000r/serial@10124000z/serial@10126000‚/serial@20064000Š/serial@20068000’/spi@20070000—/spi@20074000bus ,simple-busœdma-controller@20018000,arm,pl330arm,primecell£ €@§²½ØïÀ öapb_pclkdma-controller@2001c000,arm,pl330arm,primecell£ À@§²½ØïÀ öapb_pclk  disableddma-controller@20078000,arm,pl330arm,primecell£ €@§²½ØïÁ öapb_pclkoscillator ,fixed-clockn6!.xin24mgpu@10090000",rockchip,rk3066-maliarm,mali-400£ ïÅÅ öbuscoreAÅQõáfx  disabledx§5mgpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3}cache-controller@10138000,arm,pl310-cache£€‹™Hscu@1013c000,arm,cortex-a9-scu£Àglobal-timer@1013c200,arm,cortex-a9-global-timer£  § ï  disabledlocal-timer@1013c600,arm,cortex-a9-twd-timer£Æ  § ïinterrupt-controller@1013d000,arm,cortex-a9-gic¥º£ÐÁserial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uart£@ §"ËÕöbaudclkapb_pclkï@L okayâçtxrxñdefault ÿserial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uart£` §#ËÕöbaudclkapb_pclkïAM  disabledâçtxrxñdefaultÿqos@1012d000,syscon£Ð )qos@1012e000,syscon£à (qos@1012f000,syscon£ð "qos@1012f080,syscon£ð€ $qos@1012f100,syscon£ñ &qos@1012f180,syscon£ñ€ #qos@1012f200,syscon£ò %qos@1012f280,syscon£ò€ 'usb@10180000,rockchip,rk3066-usbsnps,dwc2£ §ïÃöotg otg#2€€@@ A  Fusb2-phy okayusb@101c0000 ,snps,dwc2£ §ïÉöotg hostA  Fusb2-phy okayñdefaultÿ ethernet@10204000,rockchip,rk3066-emac£ @< §P ïÄD öhclkmacref]dgrmii okayñdefault ÿptethernet-phy@0£ mmc@10214000,rockchip,rk2928-dw-mshc£!@ §ïÀHöbiuciuâçrx-tx‹fQ–reset okayúð€¢úð€ñdefaultÿ°ºÅÑãmmc@10218000,rockchip,rk2928-dw-mshc£!€ §ïÁIöbiuciuâçrx-tx‹fR–reset okayñdefault ÿ°ôÅmmc@1021c000,rockchip,rk2928-dw-mshc£!À §ïÂJöbiuciuâçrx-tx‹fS–reset okay°Ñôñdefault ÿ Å!!pmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd£ @reboot-mode,syscon-reboot-mode@RBÃ"RBÃ0RBà @RBÃpower-controller!,rockchip,rk3066-power-controllerLpower-domain@7£ˆïÃľ¿ÍÎPÇÖOÊÐÙÈÑÉÒ`"#$%&'power-domain@6£ ïÎÍØ×`(power-domain@8£ïÅ`)grf@20008000,syscon£ € i2c@2002d000,rockchip,rk3066-i2c£ Ð §(P öi2cïP okayñdefaultÿ*€ak8963@d,asahi-kasei,ak8975£ +§ñdefaultÿ,mma8452@1d ,fsl,mma8452£+§ñdefaultÿ-i2c@2002f000,rockchip,rk3066-i2c£ ð §)P ïQöi2c okayñdefaultÿ.€tps@2d£-/§ñdefaultÿ01g2s22‹2—3£3¯2»2 ,ti,tps65910regulatorsregulator@0Èvcc_rtc×£ëvrtcregulator@1Èvcc_io2Z 2Z ×£ëvio3regulator@2Èvdd_arm 'Àã`×0£ëvdd1Iregulator@3Èvcc_ddr 'Àã`×0£ëvdd2regulator@5Èvcc18w@w@×£ëvdig1regulator@6Èvdd_11ÈàÈà×£ëvdig2regulator@7Èvcc_25&% &% ×£ëvpll?regulator@8 Èvccio_wlw@w@£ëvdacregulator@9 Èvcc25_hdmi&% &% £ ëvaux1regulator@10Èvcca_332Z 2Z £ ëvaux2regulator@11 Èvcc_rmii2Z 2Z £ ëvaux33regulator@12 Èvcc28_cif*¹€*¹€£ ëvmmcregulator@4£ëvdd3regulator@13£ ëvbbpwm@20030000,rockchip,rk2928-pwm£ BïF  disabledñdefaultÿ4pwm@20030010,rockchip,rk2928-pwm£ BïF okayñdefaultÿ5watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt£ ÀïK §3 okaypwm@20050020,rockchip,rk2928-pwm£  BïG okayñdefaultÿ6pwm@20050030,rockchip,rk2928-pwm£ 0BïG okayñdefaultÿ7Zi2c@20056000,rockchip,rk3066-i2c£ ` §*P ïRöi2c okayñdefaultÿ8i2c@2005a000,rockchip,rk3066-i2c£   §+P ïSöi2c okayñdefaultÿ9i2c@2005e000,rockchip,rk3066-i2c£ à §4P ïTöi2c okayñdefaultÿ:serial@20064000&,rockchip,rk3066-uartsnps,dw-apb-uart£ @ §$ËÕöbaudclkapb_pclkïBN okayâçtxrxñdefaultÿ;serial@20068000&,rockchip,rk3066-uartsnps,dw-apb-uart£ € §%ËÕöbaudclkapb_pclkïCO okayâ çtxrxñdefault ÿ<=>saradc@2006c000,rockchip,saradc£ À §MïGJösaradcapb_pclkfW –saradc-apb okay_?spi@20070000,rockchip,rk3066-spiïEHöspiclkapb_pclk §&£ â  çtxrx okayñdefaultÿ@ABCspi@20074000,rockchip,rk3066-spiïFIöspiclkapb_pclk §'£ @â  çtxrx  disabledñdefaultÿDEFGcpuskrockchip,rk3066-smpcpu@0ycpu,arm,cortex-a9…H£8–›@Ö O€íØa€*ˆ s€*ˆ 'ÀÈà°ÀÈàÂÀg8§œ@ïµIcpu@1ycpu,arm,cortex-a9…H£µIdisplay-subsystem,rockchip,display-subsystemÀJKsram@10080000 ,mmio-sram£ œsmp-sram@0,rockchip,rk3066-smp-sram£Pvop@1010c000,rockchip,rk3066-vop£Àœ § ïþÍöaclk_vopdclk_vophclk_vop}fdef –axiahbdclk  disabledportJendpoint@0£ÆLPvop@1010e000,rockchip,rk3066-vop£àœ §ïÄ¿Îöaclk_vopdclk_vophclk_vop}fghi –axiahbdclk  disabledportKendpoint@0£ÆMQhdmi@10116000,rockchip,rk3066-hdmi£`  §@ïÙöhclkñdefaultÿNO}P Ö  disabledportsport@0£endpoint@0£ÆPLendpoint@1£ÆQMport@1£i2s@10118000,rockchip,rk3066-i2s£€  §ñdefaultÿRïKÆöi2s_clki2s_hclkâçtxrxçÖ  disabledi2s@1011a000,rockchip,rk3066-i2s£   § ñdefaultÿSïLÇöi2s_clki2s_hclkâçtxrxçÖ  disabledi2s@1011c000,rockchip,rk3066-i2s£À  §ñdefaultÿTïMÈöi2s_clki2s_hclkâ  çtxrxçÖ  disabledclock-controller@20000000,rockchip,rk3066a-cru£ P !@AËÔ^ÌÕ_ Qׄ#g¸€á£ðÑ€xhÀá£ðÑ€xhÀtimer@2000e000,snps,dw-apb-timer-osc£ à §.ïVD ötimerpclkefuse@20010000,rockchip,rk3066a-efuse£ @ï[ öpclk_efusecpu_leakage@17£timer@20038000,snps,dw-apb-timer-osc£ € §,ïTB ötimerpclktimer@2003a000,snps,dw-apb-timer-osc£   §-ïUC ötimerpclktsadc@20060000,rockchip,rk3066-tsadc£ ï]]ösaradcapb_pclk §Mf\ –saradc-apb  disabledphy1,rockchip,rk3066a-usb-phyrockchip,rk3288-usb-phyP  okayusb-phy@17c)£|ïQöphyclk! usb-phy@188)£ˆïRöphyclk! pinctrl,rockchip,rk3066a-pinctrlP œgpio0@20034000,rockchip,gpio-bank£ @ §6ïU4D¥º_gpio1@2003c000,rockchip,gpio-bank£ À §7ïV4D¥ºgpio2@2003e000,rockchip,gpio-bank£ à §8ïW4D¥ºgpio3@20080000,rockchip,gpio-bank£  §9ïX4D¥º]gpio4@20084000,rockchip,gpio-bank£ @ §:ïY4D¥º+gpio6@2000a000,rockchip,gpio-bank£   §<ïZ4D¥º/pcfg_pull_defaultPWpcfg_pull_nonefUemacemac-xfer€sUUUUUUUUemac-mdio sUUrmii-rstsVemmcemmc-clksWemmc-cmds Wemmc-rsts W hdmihdmi-hpdsWOhdmii2c-xfer sUUNi2c0i2c0-xfer sUU*i2c1i2c1-xfer sUU.i2c2i2c2-xfer sUU8i2c3i2c3-xfer sUU9i2c4i2c4-xfer sUU:pwm0pwm0-outsU4pwm1pwm1-outsU5pwm2pwm2-outsU6pwm3pwm3-outsU7spi0spi0-clksW@spi0-cs0sWCspi0-txsWAspi0-rxsWBspi0-cs1sWspi1spi1-clksWDspi1-cs0sWGspi1-rxsWFspi1-txsWEspi1-cs1sWuart0uart0-xfer sWWuart0-ctssWuart0-rtssWuart1uart1-xfer sWWuart1-ctssWuart1-rtssWuart2uart2-xfer sW W;uart3uart3-xfer sWW<uart3-ctssW=uart3-rtssW>sd0sd0-clksWsd0-cmds Wsd0-cdsWsd0-wpsWsd0-bus-width1s Wsd0-bus-width4@s W W W Wsd1sd1-clksWsd1-cmdsWsd1-cdsWsd1-wpsWsd1-bus-width1sWsd1-bus-width4@sWWWWi2s0i2s0-bus�sWW W W W W WWWRi2s1i2s1-bus`sWWWWWWSi2s2i2s2-bus`sWWWWWWTpcfg-output-high�Vak8963comp-intsW,irir-intsWXkeyspwr-keysWYmma8452gsensor-intsW-mmcsdmmc-pwrsW^usb_hosthost-drvsW`hub-rstsV sata-pwrsW[sata-resets V usb_otgotg-drvsWatpspmic-intsW0pwr-holdsV1memory@60000000ymemory£`@ir-receiver,gpio-ir-receiver …/ñdefaultÿXgpio-keys ,gpio-keyspower� …/ ›GPIO Power¡tñdefaultÿYvdd-log,pwm-regulator ¬ZèÈvdd_logO€O€×±B@dO€* okayvsys-regulator,regulator-fixedÈvsysLK@LK@×025v-stdby-regulator,regulator-fixed È5v_stdbyLK@LK@×0\emmc-regulator,regulator-fixed Èemmc_vccq-ÆÀ-ÆÀ¿2!sata-regulator,regulator-fixedÊ Ý+ñdefaultÿ[Èusb_5vLK@LK@׿\sdmmc-regulator,regulator-fixed Ý]ñdefaultÿ^Èvcc_sd2Z 2Z â† ¿3usb-host-regulator,regulator-fixedÊ Ý_ñdefaultÿ` Èhost-pwrLK@LK@׿\usb-otg-regulator,regulator-fixedÊ Ý_ñdefaultÿaÈvcc_otgLK@LK@׿\ #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1rangesreginterrupts#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclocksclock-namesphandlestatusclock-frequency#clock-cellsclock-output-namesassigned-clocksassigned-clock-ratesresetsinterrupt-namespower-domainscache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modephyphy-supplyreset-gpiosfifo-depthreset-namesmax-frequencybus-widthdisable-wpvmmc-supplycap-mmc-highspeedcap-sd-highspeednon-removablevqmmc-supplyoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qosvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsvref-supplyenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu-supplyportsremote-endpoint#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#reset-cells#phy-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsoutput-highwakeup-sourcelabellinux,codepwmsvoltage-tablevin-supplyenable-active-highgpiostartup-delay-us