Ð þí\K8VÀ(‹Vˆ',mundoreader,bq-curie2rockchip,rk3066a 7bq Curie 2aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/mmc@1021c000f/mmc@10214000l/mmc@10218000r/serial@10124000z/serial@10126000‚/serial@20064000Š/serial@20068000’/spi@20070000—/spi@20074000bus ,simple-busœdma-controller@20018000,arm,pl330arm,primecell£ €@§²½ØïÀ öapb_pclkdma-controller@2001c000,arm,pl330arm,primecell£ À@§²½ØïÀ öapb_pclk  disableddma-controller@20078000,arm,pl330arm,primecell£ €@§²½ØïÁ öapb_pclk oscillator ,fixed-clockn6!.xin24mgpu@10090000",rockchip,rk3066-maliarm,mali-400£ ïÅÅ öbuscoreAÅQõáfx  disabledx§5mgpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3}cache-controller@10138000,arm,pl310-cache£€‹™0scu@1013c000,arm,cortex-a9-scu£Àglobal-timer@1013c200,arm,cortex-a9-global-timer£  § ï  disabledlocal-timer@1013c600,arm,cortex-a9-twd-timer£Æ  § ïinterrupt-controller@1013d000,arm,cortex-a9-gic¥º£ÐÁserial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uart£@ §"ËÕöbaudclkapb_pclkï@L okayâçtxrxñdefaultÿserial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uart£` §#ËÕöbaudclkapb_pclkïAM okayâçtxrxñdefaultÿqos@1012d000,syscon£Ð qos@1012e000,syscon£à qos@1012f000,syscon£ð qos@1012f080,syscon£ð€ qos@1012f100,syscon£ñ qos@1012f180,syscon£ñ€ qos@1012f200,syscon£ò qos@1012f280,syscon£ò€ usb@10180000,rockchip,rk3066-usbsnps,dwc2£ §ïÃöotg otg#2€€@@ A Fusb2-phy  disabledusb@101c0000 ,snps,dwc2£ §ïÉöotg hostA Fusb2-phy  disabledethernet@10204000,rockchip,rk3066-emac£ @< §P ïÄD öhclkmacref]dgrmii  disabledmmc@10214000,rockchip,rk2928-dw-mshc£!@ §ïÀHöbiuciuâ çrx-txpfQ{reset okayúð€‡úð€ñdefaultÿ •¡«½Îmmc@10218000,rockchip,rk2928-dw-mshc£!€ §ïÁIöbiuciuâ çrx-txpfR{reset okayñdefault ÿÙ¡mmc@1021c000,rockchip,rk2928-dw-mshc£!À §ïÂJöbiuciuâ çrx-txpfS{reset  disabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd£ @reboot-mode,syscon-reboot-modeç@îRBÃúRBÃRBà RBÃpower-controller!,rockchip,rk3066-power-controller$power-domain@7£ˆïÃľ¿ÍÎPÇÖOÊÐÙÈÑÉÒ8power-domain@6£ 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disabledñdefaultÿ$i2c@2005e000,rockchip,rk3066-i2c£ à §4P ïTöi2c  disabledñdefaultÿ%serial@20064000&,rockchip,rk3066-uartsnps,dw-apb-uart£ @ §$ËÕöbaudclkapb_pclkïBN okayâ  çtxrxñdefaultÿ&serial@20068000&,rockchip,rk3066-uartsnps,dw-apb-uart£ € §%ËÕöbaudclkapb_pclkïCO okayâ  çtxrxñdefaultÿ'saradc@2006c000,rockchip,saradc£ À §ÜïGJösaradcapb_pclkfW {saradc-apb  disabledspi@20070000,rockchip,rk3066-spiïEHöspiclkapb_pclk §&£ â çtxrx  disabledñdefaultÿ()*+spi@20074000,rockchip,rk3066-spiïFIöspiclkapb_pclk §'£ @â çtxrx  disabledñdefaultÿ,-./cpusîrockchip,rk3066-smpcpu@0ücpu,arm,cortex-a90£8›@Ö O€íØa€*ˆ s€*ˆ 'ÀÈà°ÀÈàÂÀg8*œ@ï81cpu@1ücpu,arm,cortex-a90£81display-subsystem,rockchip,display-subsystemC23sram@10080000 ,mmio-sram£ œsmp-sram@0,rockchip,rk3066-smp-sram£Pvop@1010c000,rockchip,rk3066-vop£Àœ § ïþÍöaclk_vopdclk_vophclk_vop}fdef {axiahbdclk  disabledport2endpoint@0£I48vop@1010e000,rockchip,rk3066-vop£àœ §ïÄ¿Îöaclk_vopdclk_vophclk_vop}fghi {axiahbdclk  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§6ïU·Ç¥ºgpio1@2003c000,rockchip,gpio-bank£ À §7ïV·Ç¥ºgpio2@2003e000,rockchip,gpio-bank£ à §8ïW·Ç¥ºgpio3@20080000,rockchip,gpio-bank£  §9ïX·Ç¥º@gpio4@20084000,rockchip,gpio-bank£ @ §:ïY·Ç¥ºAgpio6@2000a000,rockchip,gpio-bank£   §<ïZ·Ç¥ºpcfg_pull_defaultÓ>pcfg_pull_noneé=emacemac-xfer€ö========emac-mdio ö==emmcemmc-clkö>emmc-cmdö >emmc-rstö >hdmihdmi-hpdö>7hdmii2c-xfer ö==6i2c0i2c0-xfer ö==i2c1i2c1-xfer ö==i2c2i2c2-xfer ö==#i2c3i2c3-xfer ö==$i2c4i2c4-xfer ö==%pwm0pwm0-outö=pwm1pwm1-outö= pwm2pwm2-outö=!pwm3pwm3-outö="spi0spi0-clkö>(spi0-cs0ö>+spi0-txö>)spi0-rxö>*spi0-cs1ö>spi1spi1-clkö>,spi1-cs0ö>/spi1-rxö>.spi1-txö>-spi1-cs1ö>uart0uart0-xfer ö>>uart0-ctsö>uart0-rtsö>uart1uart1-xfer ö>>uart1-ctsö>uart1-rtsö>uart2uart2-xfer ö> >&uart3uart3-xfer ö>>'uart3-ctsö>uart3-rtsö>sd0sd0-clkö> sd0-cmdö > sd0-cdö> sd0-wpö>sd0-bus-width1ö >sd0-bus-width4@ö > > > >sd1sd1-clkö>sd1-cmdö>sd1-cdö>sd1-wpö>sd1-bus-width1ö>sd1-bus-width4@ö>>>>i2s0i2s0-bus�ö>> > > > > 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#address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1rangesreginterrupts#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclocksclock-namesphandlestatusclock-frequency#clock-cellsclock-output-namesassigned-clocksassigned-clock-ratesresetsinterrupt-namespower-domainscache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modefifo-depthreset-namesmax-frequencyvmmc-supplybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpnon-removableoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qosvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu-supplyportsremote-endpoint#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#reset-cells#phy-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinspwmsvoltage-tablegpiostartup-delay-usvin-supplyautorepeatgpioslinux,codelabellinux,input-typewakeup-sourcedebounce-interval