Ð þí6¯82ˆ('2P$rockchip,rk3036-evbrockchip,rk3036&!7Rockchip RK3036 Evaluation boardaliases=/i2c@20072000B/i2c@20056000G/i2c@2005a000L/mmc@1021c000R/mmc@10214000X/mmc@10218000^/serial@20060000f/serial@20064000n/serial@20068000v/spi@20074000cpuszrockchip,rk3036-smpcpu@f00ˆcpuarm,cortex-a7”˜Ÿ s€B@°œ@¾Åcpu@f01ˆcpuarm,cortex-a7”˜Åbus simple-busÍpdma@20078000arm,pl330arm,primecell” €@Ôßê¾Â apb_pclkÅ arm-pmuarm,cortex-a7-pmuÔLM(display-subsystemrockchip,display-subsystem;timerarm,armv7-timerA0Ô   en6oscillator fixed-clocken6uxin24mˆÅsram@10080000 mmio-sram”  Í smp-sram@0rockchip,rk3066-smp-sram”gpu@10090000"rockchip,rk3036-maliarm,mali-400” 0Ô•gpgpmmupp0ppmmu0¥@µõá¾@@ buscore˜x Êdisabledvop@10118000rockchip,rk3036-vop”€œ Ô+¾ÅdÑaclk_vopdclk_vophclk_vop˜uvw ÑaxiahbdclkÝ ÊdisabledportÅendpoint@0”äÅiommu@10118300rockchip,iommu”ƒ Ô+•vop_mmu¾ÅÑ aclkifaceô ÊdisabledÅinterrupt-controller@10139000 arm,gic-400 ”�  À à  Ô Åusb@101800002rockchip,rk3036-usbrockchip,rk3066-usbsnps,dwc2” Ô ¾Áotg'otg/AP€€@@  Êdisabledusb@101c00002rockchip,rk3036-usbrockchip,rk3066-usbsnps,dwc2” Ô ¾Âotg'host Êdisabledethernet@10200000#rockchip,rk3036-emacsnps,arc-emac” @ Ô_¾Ì˜—hclkmacrefmacclk¥™lƒd�rmiiÊokay–default¤ ®  ²  ethernet-phy@0”Å mmc@102140000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc”!@@e<4`Õ<4`¾ÈDbiuciuã Ô˜QÑreset Êdisabledmmc@102180000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc”!€@Õ<4` ¾ÉEswbiuciuciu-driveciu-sampleã Ô˜RÑreset Êdisabledmmc@1021c0000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc”!À@ Ôîøe<4`Õ<4` ¾ËGuybiuciuciu-driveciu-sample ž(3 8rx-txãBO–default ¤˜SÑreset Êdisabledi2s@10220000(rockchip,rk3036-i2srockchip,rk3066-i2s”"@ Ô3i2s_clki2s_hclk¾RÎ3 8txrx–default¤] Êdisabledclock-controller@20000000rockchip,rk3036-cru” _ˆn¥µ#g¸€Åsyscon@20008000&rockchip,rk3036-grfsysconsimple-mfd” €Åreboot-modesyscon-reboot-mode{Ø‚RBÃŽRBÜRBà ¬RBÃacodec-ana@20030000 rk3036-codec” @_ acodec_pclk¾q Êdisabledhdmi@20034000rockchip,rk3036-inno-hdmi” @@ Ô-¾hpclk_–default¤ Êdisabledportsport@0”endpointäÅport@1”timer@20044000,rockchip,rk3036-timerrockchip,rk3288-timer” @  Ô ¾a timerpclkpwm@20050000(rockchip,rk3036-pwmrockchip,rk2928-pwm” ¸¾^pwm–default¤ Êdisabledpwm@20050010(rockchip,rk3036-pwmrockchip,rk2928-pwm” ¸¾^pwm–default¤ Êdisabledpwm@20050020(rockchip,rk3036-pwmrockchip,rk2928-pwm”  ¸¾^pwm–default¤ Êdisabledpwm@20050030(rockchip,rk3036-pwmrockchip,rk2928-pwm” 0¸¾^pwm–default¤ Êdisabledi2c@20056000(rockchip,rk3036-i2crockchip,rk3288-i2c” ` Ôi2c¾M–default¤Êokayrtc@51haoyu,hym8563”Qˆe€uxin32ki2c@2005a000(rockchip,rk3036-i2crockchip,rk3288-i2c”   Ôi2c¾N–default¤ Êdisabledserial@20060000&rockchip,rk3036-uartsnps,dw-apb-uart”  ÔÃÍen6¾MUbaudclkapb_pclk–default ¤ Êdisabledserial@20064000&rockchip,rk3036-uartsnps,dw-apb-uart” @ ÔÃÍen6¾NVbaudclkapb_pclk–default¤ Êdisabledserial@20068000&rockchip,rk3036-uartsnps,dw-apb-uart” € ÔÃÍen6¾OWbaudclkapb_pclk–default¤Êokayi2c@20072000(rockchip,rk3036-i2crockchip,rk3288-i2c”   Ôi2c¾L–default¤  Êdisabledspi@20074000rockchip,rockchip-spi” @ Ô¾RAapb-pclkspi_pclk3  8txrx–default¤!"#$ Êdisabledpinctrlrockchip,rk3036-pinctrl_Ígpio0@2007c000rockchip,gpio-bank” À Ô$¾@Úêgpio1@20080000rockchip,gpio-bank”  Ô%¾AÚêgpio2@20084000rockchip,gpio-bank” @ Ô&¾BÚêÅ pcfg_pull_defaultöÅ&pcfg-pull-none Å%pwm0pwm0-pin%Åpwm1pwm1-pin%Åpwm2pwm2-pin%Åpwm3pwm3-pin%Åsdmmcsdmmc-clk%sdmmc-cmd&sdmmc-cd&sdmmc-bus1&sdmmc-bus4@&&&&sdiosdio-bus1 &sdio-bus4@ & & &&sdio-cmd&sdio-clk %emmcemmc-clk%Åemmc-cmd&Åemmc-bus8€&&&&&&&&Åemacemac-xfer€ & &&&&&&&Å emac-mdio  &&Å i2c0i2c0-xfer %%Å i2c1i2c1-xfer %%Åi2c2i2c2-xfer %%Åi2si2s-bus`&&&&&&Åhdmihdmi-ctl@% % % %Åuart0uart0-xfer &%Åuart0-cts&Åuart0-rts%Åuart1uart1-xfer &%Åuart2uart2-xfer &%Åspi-pinsspi-txd&Å!spi-rxd&Å"spi-clk&Å#spi-cs0&Å$spi-cs1&memory@60000000ˆmemory”`@ #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2mshc0mshc1mshc2serial0serial1serial2spienable-methoddevice_typeregresetsoperating-pointsclock-latencyclocksphandlerangesinterrupts#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclock-namesinterrupt-affinityportsarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsinterrupt-namesassigned-clocksassigned-clock-ratesstatusreset-namesiommusremote-endpoint#iommu-cellsinterrupt-controller#interrupt-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,grfassigned-clock-parentsmax-speedphy-modepinctrl-namespinctrl-0phyphy-reset-gpiosphy-reset-durationmax-frequencyfifo-depthbus-widthcap-mmc-highspeedrockchip,default-sample-phasedisable-wpdmasdma-namesmmc-ddr-1_8vnon-removable#sound-dai-cells#reset-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#pwm-cellsreg-shiftreg-io-widthgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pins