Ð þí÷ 8ïl( ï41lg,omap3-sniperti,omap3630ti,omap36xxti,omap3 +7LG Optimus Blackchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000s/ocp@68000000/serial@49042000cpus+cpu@0arm,cortex-a8{cpu‡‹’cpuž“à¬ÀËÚæpmu@54000000arm,cortex-a8-pmu‡T€îùdebugsssocti,omap-inframpu ti,omap3-mpuùmpuiva ti,iva2.2ùivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus‡hî +ùl3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus‡ +  pinmux@30 ti,omap3-padconfpinctrl-single‡08+ *?]ÿzdefaultæçpinmux_uart3_pinsˆnpæèpinmux_dp3t_sel_pinsˆfhæépinmux_i2c1_pinsˆŠŒæêpinmux_i2c2_pinsˆŽ�æñpinmux_i2c3_pinsˆ’”æòpinmux_lp8720_en_pinˆPæópinmux_mmc1_pins0ˆæöpinmux_mmc2_pinsPˆ(*,.02468:æúpinmux_usb_otg_hs_pins`ˆrtvxz|~€‚„†ˆæpinmux_twl4030_pinsˆ°Aæëscm_conf@270sysconsimple-bus‡p0+ p0æpbias_regulator@2b0ti,pbias-omap3ti,pbias-omap‡°œpbias_mmc_omap2430£pbias_mmc_omap2430²w@Ê-ÆÀæõclocks+mcbsp5_mux_fck@68âti,composite-mux-clock‹ï‡hæ mcbsp5_fckâti,composite-clock‹ æmcbsp1_mux_fck@4âti,composite-mux-clock‹ï‡æ mcbsp1_fckâti,composite-clock‹ æümcbsp2_mux_fck@4âti,composite-mux-clock‹ ï‡æmcbsp2_fckâti,composite-clock‹æþmcbsp3_mux_fck@68âti,composite-mux-clock‹ ‡hæmcbsp3_fckâti,composite-clock‹æÿmcbsp4_mux_fck@68âti,composite-mux-clock‹ ï‡hæmcbsp4_fckâti,composite-clock‹æclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single‡ \+ *?]ÿzdefaultpinmux_mmc1_cd_pinˆæ÷pinmux_twl4030_vpins ˆæìtarget-module@480a6000ti,sysc-omap2ti,sysc‡H `DH `HH `Lürevsyscsyss !‹’ick+ H ` aes1@0 ti,omap3-aes‡Pî.  3txrxtarget-module@480c5000ti,sysc-omap2ti,sysc‡H PDH PHH PLürevsyscsyss !‹’ick+ H P aes2@0 ti,omap3-aes‡Pî.AB3txrxprm@48306000 ti,omap3-prm‡H0`@î clocks+virt_16_8m_ckâ fixed-clock=Yæosc_sys_ck@d40â ti,mux-clock‹‡ @æsys_ck@1270âti,divider-clock‹ïM‡pXæ"sys_clkout1@d70âti,gate-clock‹‡ pïdpll3_x2_ckâfixed-factor-clock‹ozdpll3_m2x2_ckâfixed-factor-clock‹ozæ!dpll4_x2_ckâfixed-factor-clock‹ ozcorex2_fckâfixed-factor-clock‹!ozæ#wkup_l4_ickâfixed-factor-clock‹"ozæRcorex2_d3_fckâfixed-factor-clock‹#ozæ‰corex2_d5_fckâfixed-factor-clock‹#ozæŠclockdomainscm@48004000 ti,omap3-cm‡H@@clocks+dummy_apb_pclkâ fixed-clock=omap_32k_fckâ fixed-clock=€æDvirt_12m_ckâ fixed-clock=·ævirt_13m_ckâ fixed-clock=Æ]@ævirt_19200000_ckâ fixed-clock=$øævirt_26000000_ckâ fixed-clock=Œº€ævirt_38_4m_ckâ fixed-clock=Iðædpll4_ck@d00âti,omap3-dpll-per-j-type-clock‹""‡ D 0æ dpll4_m2_ck@d48âti,divider-clock‹ M?‡ HXæ$dpll4_m2x2_mul_ckâfixed-factor-clock‹$ozæ%dpll4_m2x2_ck@d00âti,hsdiv-gate-clock‹%ï‡ „æ&omap_96m_alwon_fckâfixed-factor-clock‹&ozæ-dpll3_ck@d00âti,omap3-dpll-core-clock‹""‡ @ 0ædpll3_m3_ck@1140âti,divider-clock‹ïM‡@Xæ'dpll3_m3x2_mul_ckâfixed-factor-clock‹'ozæ(dpll3_m3x2_ck@d00âti,hsdiv-gate-clock‹(ï ‡ „æ)emu_core_alwon_ckâfixed-factor-clock‹)ozæfsys_altclkâ fixed-clock=æ2mcbsp_clksâ fixed-clock=ædpll3_m2_ck@d40âti,divider-clock‹ïM‡ @Xæcore_ckâfixed-factor-clock‹ozæ*dpll1_fck@940âti,divider-clock‹*ïM‡ @Xæ+dpll1_ck@904âti,omap3-dpll-clock‹"+‡  $ @ 4ædpll1_x2_ckâfixed-factor-clock‹ozæ,dpll1_x2m2_ck@944âti,divider-clock‹,M‡ DXæ@cm_96m_fckâfixed-factor-clock‹-ozæ.omap_96m_fck@d40â ti,mux-clock‹."ï‡ @æIdpll4_m3_ck@e40âti,divider-clock‹ ïM ‡@Xæ/dpll4_m3x2_mul_ckâfixed-factor-clock‹/ozæ0dpll4_m3x2_ck@d00âti,hsdiv-gate-clock‹0ï‡ „æ1omap_54m_fck@d40â ti,mux-clock‹12ï‡ @æ<cm_96m_d2_fckâfixed-factor-clock‹.ozæ3omap_48m_fck@d40â ti,mux-clock‹32ï‡ @æ4omap_12m_fckâfixed-factor-clock‹4ozæKdpll4_m4_ck@e40âti,divider-clock‹ M‡@Xæ5dpll4_m4x2_mul_ckâti,fixed-factor-clock‹5š¨µæ6dpll4_m4x2_ck@d00âti,gate-clock‹6ï‡ „µæ�dpll4_m5_ck@f40âti,divider-clock‹ M?‡@Xæ7dpll4_m5x2_mul_ckâti,fixed-factor-clock‹7š¨µæ8dpll4_m5x2_ck@d00âti,hsdiv-gate-clock‹8ï‡ „µændpll4_m6_ck@1140âti,divider-clock‹ ïM?‡@Xæ9dpll4_m6x2_mul_ckâfixed-factor-clock‹9ozæ:dpll4_m6x2_ck@d00âti,hsdiv-gate-clock‹:ï‡ „æ;emu_per_alwon_ckâfixed-factor-clock‹;ozægclkout2_src_gate_ck@d70â ti,composite-no-wait-gate-clock‹*ï‡ pæ=clkout2_src_mux_ck@d70âti,composite-mux-clock‹*".<‡ pæ>clkout2_src_ckâti,composite-clock‹=>æ?sys_clkout2@d70âti,divider-clock‹?ïM@‡ pÈmpu_ckâfixed-factor-clock‹@ozæAarm_fck@924âti,divider-clock‹A‡ $Memu_mpu_alwon_ckâfixed-factor-clock‹Aozæhl3_ick@a40âti,divider-clock‹*M‡ @XæBl4_ick@a40âti,divider-clock‹BïM‡ @XæCrm_ick@c40âti,divider-clock‹CïM‡ @Xgpt10_gate_fck@a00âti,composite-gate-clock‹"ï ‡ æEgpt10_mux_fck@a40âti,composite-mux-clock‹D"ï‡ @æFgpt10_fckâti,composite-clock‹EFgpt11_gate_fck@a00âti,composite-gate-clock‹"ï ‡ æGgpt11_mux_fck@a40âti,composite-mux-clock‹D"ï‡ @æHgpt11_fckâti,composite-clock‹GHcore_96m_fckâfixed-factor-clock‹Iozæmmchs2_fck@a00âti,wait-gate-clock‹‡ ïæ¹mmchs1_fck@a00âti,wait-gate-clock‹‡ ïæºi2c3_fck@a00âti,wait-gate-clock‹‡ ïæ»i2c2_fck@a00âti,wait-gate-clock‹‡ ïæ¼i2c1_fck@a00âti,wait-gate-clock‹‡ ïæ½mcbsp5_gate_fck@a00âti,composite-gate-clock‹ï ‡ æ mcbsp1_gate_fck@a00âti,composite-gate-clock‹ï ‡ æ core_48m_fckâfixed-factor-clock‹4ozæJmcspi4_fck@a00âti,wait-gate-clock‹J‡ ïæ¾mcspi3_fck@a00âti,wait-gate-clock‹J‡ ïæ¿mcspi2_fck@a00âti,wait-gate-clock‹J‡ ïæÀmcspi1_fck@a00âti,wait-gate-clock‹J‡ ïæÁuart2_fck@a00âti,wait-gate-clock‹J‡ ïæÂuart1_fck@a00âti,wait-gate-clock‹J‡ ï æÃcore_12m_fckâfixed-factor-clock‹KozæLhdq_fck@a00âti,wait-gate-clock‹L‡ ïæÄcore_l3_ickâfixed-factor-clock‹BozæMsdrc_ick@a10âti,wait-gate-clock‹M‡ ïæŽgpmc_fckâfixed-factor-clock‹Mozcore_l4_ickâfixed-factor-clock‹CozæNmmchs2_ick@a10âti,omap3-interface-clock‹N‡ ïæÅmmchs1_ick@a10âti,omap3-interface-clock‹N‡ ïæÆhdq_ick@a10âti,omap3-interface-clock‹N‡ ïæÇmcspi4_ick@a10âti,omap3-interface-clock‹N‡ ïæÈmcspi3_ick@a10âti,omap3-interface-clock‹N‡ ïæÉmcspi2_ick@a10âti,omap3-interface-clock‹N‡ ïæÊmcspi1_ick@a10âti,omap3-interface-clock‹N‡ ïæËi2c3_ick@a10âti,omap3-interface-clock‹N‡ ïæÌi2c2_ick@a10âti,omap3-interface-clock‹N‡ ïæÍi2c1_ick@a10âti,omap3-interface-clock‹N‡ ïæÎuart2_ick@a10âti,omap3-interface-clock‹N‡ ïæÏuart1_ick@a10âti,omap3-interface-clock‹N‡ ï æÐgpt11_ick@a10âti,omap3-interface-clock‹N‡ ï æÑgpt10_ick@a10âti,omap3-interface-clock‹N‡ ï æÒmcbsp5_ick@a10âti,omap3-interface-clock‹N‡ ï æÓmcbsp1_ick@a10âti,omap3-interface-clock‹N‡ ï æÔomapctrl_ick@a10âti,omap3-interface-clock‹N‡ ïæÕdss_tv_fck@e00âti,gate-clock‹<‡ïæ´dss_96m_fck@e00âti,gate-clock‹I‡ïæµdss2_alwon_fck@e00âti,gate-clock‹"‡ïæ¶dummy_ckâ fixed-clock=gpt1_gate_fck@c00âti,composite-gate-clock‹"ï‡ æOgpt1_mux_fck@c40âti,composite-mux-clock‹D"‡ @æPgpt1_fckâti,composite-clock‹OPæaes2_ick@a10âti,omap3-interface-clock‹Nï‡ æwkup_32k_fckâfixed-factor-clock‹DozæQgpio1_dbck@c00âti,gate-clock‹Q‡ ïæ«sha12_ick@a10âti,omap3-interface-clock‹N‡ ïæÖwdt2_fck@c00âti,wait-gate-clock‹Q‡ ïæ¬wdt2_ick@c10âti,omap3-interface-clock‹R‡ ïæ­wdt1_ick@c10âti,omap3-interface-clock‹R‡ ïæ®gpio1_ick@c10âti,omap3-interface-clock‹R‡ ïæ¯omap_32ksync_ick@c10âti,omap3-interface-clock‹R‡ ïæ°gpt12_ick@c10âti,omap3-interface-clock‹R‡ ïæ±gpt1_ick@c10âti,omap3-interface-clock‹R‡ ïæ²per_96m_fckâfixed-factor-clock‹-ozæ per_48m_fckâfixed-factor-clock‹4ozæSuart3_fck@1000âti,wait-gate-clock‹S‡ï æ�gpt2_gate_fck@1000âti,composite-gate-clock‹"ï‡æTgpt2_mux_fck@1040âti,composite-mux-clock‹D"‡@æUgpt2_fckâti,composite-clock‹TUægpt3_gate_fck@1000âti,composite-gate-clock‹"ï‡æVgpt3_mux_fck@1040âti,composite-mux-clock‹D"ï‡@æWgpt3_fckâti,composite-clock‹VWgpt4_gate_fck@1000âti,composite-gate-clock‹"ï‡æXgpt4_mux_fck@1040âti,composite-mux-clock‹D"ï‡@æYgpt4_fckâti,composite-clock‹XYgpt5_gate_fck@1000âti,composite-gate-clock‹"ï‡æZgpt5_mux_fck@1040âti,composite-mux-clock‹D"ï‡@æ[gpt5_fckâti,composite-clock‹Z[gpt6_gate_fck@1000âti,composite-gate-clock‹"ï‡æ\gpt6_mux_fck@1040âti,composite-mux-clock‹D"ï‡@æ]gpt6_fckâti,composite-clock‹\]gpt7_gate_fck@1000âti,composite-gate-clock‹"ï‡æ^gpt7_mux_fck@1040âti,composite-mux-clock‹D"ï‡@æ_gpt7_fckâti,composite-clock‹^_gpt8_gate_fck@1000âti,composite-gate-clock‹"ï ‡æ`gpt8_mux_fck@1040âti,composite-mux-clock‹D"ï‡@æagpt8_fckâti,composite-clock‹`agpt9_gate_fck@1000âti,composite-gate-clock‹"ï ‡æbgpt9_mux_fck@1040âti,composite-mux-clock‹D"ï‡@æcgpt9_fckâti,composite-clock‹bcper_32k_alwon_fckâfixed-factor-clock‹Dozædgpio6_dbck@1000âti,gate-clock‹d‡ïæ‘gpio5_dbck@1000âti,gate-clock‹d‡ïæ’gpio4_dbck@1000âti,gate-clock‹d‡ïæ“gpio3_dbck@1000âti,gate-clock‹d‡ïæ”gpio2_dbck@1000âti,gate-clock‹d‡ï æ•wdt3_fck@1000âti,wait-gate-clock‹d‡ï æ–per_l4_ickâfixed-factor-clock‹Cozæegpio6_ick@1010âti,omap3-interface-clock‹e‡ïæ—gpio5_ick@1010âti,omap3-interface-clock‹e‡ïæ˜gpio4_ick@1010âti,omap3-interface-clock‹e‡ïæ™gpio3_ick@1010âti,omap3-interface-clock‹e‡ïæšgpio2_ick@1010âti,omap3-interface-clock‹e‡ï æ›wdt3_ick@1010âti,omap3-interface-clock‹e‡ï æœuart3_ick@1010âti,omap3-interface-clock‹e‡ï æ�uart4_ick@1010âti,omap3-interface-clock‹e‡ïæžgpt9_ick@1010âti,omap3-interface-clock‹e‡ï æŸgpt8_ick@1010âti,omap3-interface-clock‹e‡ï æ gpt7_ick@1010âti,omap3-interface-clock‹e‡ïæ¡gpt6_ick@1010âti,omap3-interface-clock‹e‡ïæ¢gpt5_ick@1010âti,omap3-interface-clock‹e‡ïæ£gpt4_ick@1010âti,omap3-interface-clock‹e‡ïæ¤gpt3_ick@1010âti,omap3-interface-clock‹e‡ïæ¥gpt2_ick@1010âti,omap3-interface-clock‹e‡ïæ¦mcbsp2_ick@1010âti,omap3-interface-clock‹e‡ïæ§mcbsp3_ick@1010âti,omap3-interface-clock‹e‡ïæ¨mcbsp4_ick@1010âti,omap3-interface-clock‹e‡ïæ©mcbsp2_gate_fck@1000âti,composite-gate-clock‹ï‡æmcbsp3_gate_fck@1000âti,composite-gate-clock‹ï‡æmcbsp4_gate_fck@1000âti,composite-gate-clock‹ï‡æemu_src_mux_ck@1140â ti,mux-clock‹"fgh‡@æiemu_src_ckâti,clkdm-gate-clock‹iæjpclk_fck@1140âti,divider-clock‹jïM‡@Xpclkx2_fck@1140âti,divider-clock‹jïM‡@Xatclk_fck@1140âti,divider-clock‹jïM‡@Xtraceclk_src_fck@1140â ti,mux-clock‹"fghï‡@æktraceclk_fck@1140âti,divider-clock‹kï M‡@Xsecure_32k_fckâ fixed-clock=€ælgpt12_fckâfixed-factor-clock‹lozæwdt1_fckâfixed-factor-clock‹lozsecurity_l4_ick2âfixed-factor-clock‹Cozæmaes1_ick@a14âti,omap3-interface-clock‹mï‡ ærng_ick@a14âti,omap3-interface-clock‹m‡ ïæýsha11_ick@a14âti,omap3-interface-clock‹m‡ ïdes1_ick@a14âti,omap3-interface-clock‹m‡ ïcam_mclk@f00âti,gate-clock‹ncam_ick@f10â!ti,omap3-no-wait-interface-clock‹C‡ïæÝcsi2_96m_fck@f00âti,gate-clock‹‡ïæÞsecurity_l3_ickâfixed-factor-clock‹Bozæopka_ick@a14âti,omap3-interface-clock‹o‡ ïicr_ick@a10âti,omap3-interface-clock‹N‡ ïdes2_ick@a10âti,omap3-interface-clock‹N‡ ïmspro_ick@a10âti,omap3-interface-clock‹N‡ ïmailboxes_ick@a10âti,omap3-interface-clock‹N‡ ïssi_l4_ickâfixed-factor-clock‹Cozævsr1_fck@c00âti,wait-gate-clock‹"‡ ïæ sr2_fck@c00âti,wait-gate-clock‹"‡ ïæ sr_l4_ickâfixed-factor-clock‹Cozdpll2_fck@40âti,divider-clock‹*ïM‡@Xæpdpll2_ck@4âti,omap3-dpll-clock‹"p‡$@4Þðøæqdpll2_m2_ck@44âti,divider-clock‹qM‡DXæriva2_ck@0âti,wait-gate-clock‹r‡ïæßmodem_fck@a00âti,omap3-interface-clock‹"‡ ïæàsad2d_ick@a10âti,omap3-interface-clock‹B‡ ïæámad2d_ick@a18âti,omap3-interface-clock‹B‡ ïæâmspro_fck@a00âti,wait-gate-clock‹‡ ïssi_ssr_gate_fck_3430es2@a00â ti,composite-no-wait-gate-clock‹#ï‡ æsssi_ssr_div_fck_3430es2@a40âti,composite-divider-clock‹#ï‡ @$ ætssi_ssr_fck_3430es2âti,composite-clock‹stæussi_sst_fck_3430es2âfixed-factor-clock‹uozæhsotgusb_ick_3430es2@a10â"ti,omap3-hsotgusb-interface-clock‹M‡ ïæ�ssi_ick_3430es2@a10âti,omap3-ssi-interface-clock‹v‡ ïæusim_gate_fck@c00âti,composite-gate-clock‹Iï ‡ æ�sys_d2_ckâfixed-factor-clock‹"ozæxomap_96m_d2_fckâfixed-factor-clock‹Iozæyomap_96m_d4_fckâfixed-factor-clock‹Iozæzomap_96m_d8_fckâfixed-factor-clock‹Iozæ{omap_96m_d10_fckâfixed-factor-clock‹Ioz æ|dpll5_m2_d4_ckâfixed-factor-clock‹wozæ}dpll5_m2_d8_ckâfixed-factor-clock‹wozæ~dpll5_m2_d16_ckâfixed-factor-clock‹wozædpll5_m2_d20_ckâfixed-factor-clock‹wozæ€usim_mux_fck@c40âti,composite-mux-clock(‹"xyz{|}~€ï‡ @Xæ‚usim_fckâti,composite-clock‹�‚usim_ick@c10âti,omap3-interface-clock‹R‡ ï æ³dpll5_ck@d04âti,omap3-dpll-clock‹""‡  $ L 4Þðæƒdpll5_m2_ck@d50âti,divider-clock‹ƒM‡ PXæwsgx_gate_fck@b00âti,composite-gate-clock‹*ï‡ æ‹core_d3_ckâfixed-factor-clock‹*ozæ„core_d4_ckâfixed-factor-clock‹*ozæ…core_d6_ckâfixed-factor-clock‹*ozæ†omap_192m_alwon_fckâfixed-factor-clock‹&ozæ‡core_d2_ckâfixed-factor-clock‹*ozæˆsgx_mux_fck@b40âti,composite-mux-clock ‹„…†.‡ˆ‰Š‡ @æŒsgx_fckâti,composite-clock‹‹Œæ sgx_ick@b10âti,wait-gate-clock‹B‡ ïæãcpefuse_fck@a08âti,gate-clock‹"‡ ïæ×ts_fck@a08âti,gate-clock‹D‡ ïæØusbtll_fck@a08âti,wait-gate-clock‹w‡ ïæÙusbtll_ick@a18âti,omap3-interface-clock‹N‡ ïæÚmmchs3_ick@a10âti,omap3-interface-clock‹N‡ ïæÛmmchs3_fck@a00âti,wait-gate-clock‹‡ ïæÜdss1_alwon_fck_3430es2@e00âti,dss-gate-clock‹�æ·dss_ick_3430es2@e10âti,omap3-dss-interface-clock‹C‡ïæ¸usbhost_120m_fck@1400âti,gate-clock‹w‡ïæäusbhost_48m_fck@1400âti,dss-gate-clock‹4‡ïæåusbhost_ick@1410âti,omap3-dss-interface-clock‹C‡ïææuart4_fck@1000âti,wait-gate-clock‹S‡ïæªclockdomainscore_l3_clkdmti,clockdomain‹Ž�dpll3_clkdmti,clockdomain‹dpll1_clkdmti,clockdomain‹per_clkdmti,clockdomainl‹�‘’“”•–—˜™š›œ�žŸ ¡¢£¤¥¦§¨©ªemu_clkdmti,clockdomain‹jdpll4_clkdmti,clockdomain‹ wkup_clkdmti,clockdomain$‹«¬­®¯°±²³dss_clkdmti,clockdomain‹´µ¶·¸core_l4_clkdmti,clockdomain”‹¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖרÙÚÛÜcam_clkdmti,clockdomain‹ÝÞiva2_clkdmti,clockdomain‹ßdpll2_clkdmti,clockdomain‹qd2d_clkdmti,clockdomain ‹àáâdpll5_clkdmti,clockdomain‹ƒsgx_clkdmti,clockdomain‹ãusbhost_clkdmti,clockdomain ‹äåætarget-module@48320000ti,sysc-omap2ti,sysc‡H2H2 ürevsysc‹Q°’fckick+ H2counter@0ti,omap-counter32k‡ interrupt-controller@48200000ti,omap3-intc*‡H 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-points-v2vbb-supply#cooling-cellscpu0-supplyphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsti,no-reset-on-initinterrupts-extendedpinctrl-0ti,use_poweroffbci3v1-supplyio-channelsio-channel-namesregulator-always-onusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cellsenable-gpios#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplycd-gpiosbus-widthti,non-removablestatus#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinsmultipointnum-epsram-bitsinterface-typeusb-phyphysphy-namespowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modeti,absolute-max-voltage-uvpolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-device