Ð þíè'8Þ\( ËÞ$Dcompulab,omap3-sbc-t3517compulab,omap3-cm-t3517ti,am3517ti,omap3 +!7CompuLab SBC-T3517 with CM-T3517chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000s/ocp@68000000/serial@4809e000{/ocp@68000000/can@5c050000/dvi-connectorˆ/svideo-connectorcpus+cpu@0arm,cortex-a8‘cpu�¡¨cpu´“àÂpmu@54000000arm,cortex-a8-pmu�T€Öádebugsssocti,omap-inframpu ti,omap3-mpuámpuiva ti,iva2.2áiva ëdisableddsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus�hÖ +òál3_mainl4@48000000ti,omap3-l4-coresimple-bus+ òHscm@2000ti,omap3-scmsimple-bus� + ò pinmux@30 ti,omap3-padconfpinctrl-single�08+ù.Lÿidefaultwpinmux_uart3_pins�np•Ðpinmux_mmc1_pins0�•Øpinmux_green_led_pins�²•öpinmux_dss_dpi_pins_common°�¤¦¨ª¸º¼¾ÀÂÄÆÈÊÌÎÐÒÔÖØÚ•ïpinmux_dss_dpi_pins_cm_t35x0�¬®°²´¶•ðpinmux_ads7846_pins�Š•Ôpinmux_mcspi1_pins �˜šœž•Ópinmux_i2c1_pins�ŠŒ•Ñpinmux_mcbsp2_pins � •ápinmux_hsusb1_phy_reset_pins�H•ùpinmux_hsusb2_phy_reset_pins�J•ûpinmux_otg_drv_vbus�à•ópinmux_mmc2_pins0�(*,.02•Üpinmux_wl12xx_core_pins�ˆF•þpinmux_usb_hub_pins�T•pinmux_smsc2_pins�†¢•ëpinmux_tfp410_pins�„•pinmux_i2c3_pins�’”•Òpinmux_sb_t35_audio_amp�˜•pinmux_mmc1_aux_pins��D•Ùpinmux_sb_t35_usb_hub_pins�¼•scm_conf@270sysconsimple-bus�p0+ òp0•pbias_regulator@2b0ti,pbias-omap3ti,pbias-omap�°�pbias_mmc_omap2430¤pbias_mmc_omap2430³w@Ë-ÆÀ•×clocks+mcbsp5_mux_fck@68ãti,composite-mux-clock¡ð�h• mcbsp5_fckãti,composite-clock¡ •ämcbsp1_mux_fck@4ãti,composite-mux-clock¡ð�• mcbsp1_fckãti,composite-clock¡ •ßmcbsp2_mux_fck@4ãti,composite-mux-clock¡ ð�•mcbsp2_fckãti,composite-clock¡•àmcbsp3_mux_fck@68ãti,composite-mux-clock¡ �h•mcbsp3_fckãti,composite-clock¡•âmcbsp4_mux_fck@68ãti,composite-mux-clock¡ ð�h•mcbsp4_fckãti,composite-clock¡•ãemac_ick@32cãti,am35xx-gate-clock¡�,ð•zemac_fck@32cãti,gate-clock¡�,ð •ôvpfe_ick@32cãti,am35xx-gate-clock¡�,ð•{vpfe_fck@32cãti,gate-clock¡�,ð hsotgusb_ick_am35xx@32cãti,am35xx-gate-clock¡�,ð•|hsotgusb_fck_am35xx@32cãti,gate-clock¡�,ð•}hecc_ck@32cãti,am35xx-gate-clock¡�,ð•~clockdomainspinmux@a00 ti,omap3-padconfpinctrl-single� \+ù.Lÿpinmux_wl12xx_wkup_pins�•ýprm@48306000 ti,omap3-prm�H0`@Ö clocks+virt_16_8m_ckã fixed-clockýY•osc_sys_ck@d40ã ti,mux-clock¡� @•sys_ck@1270ãti,divider-clock¡ð �p•sys_clkout1@d70ãti,gate-clock¡� pðdpll3_x2_ckãfixed-factor-clock¡/:dpll3_m2x2_ckãfixed-factor-clock¡ /:•"dpll4_x2_ckãfixed-factor-clock¡!/:corex2_fckãfixed-factor-clock¡"/:•#wkup_l4_ickãfixed-factor-clock¡/:•Rcorex2_d3_fckãfixed-factor-clock¡#/:•scorex2_d5_fckãfixed-factor-clock¡#/:•tclockdomainscm@48004000 ti,omap3-cm�H@@clocks+dummy_apb_pclkã fixed-clockýomap_32k_fckã fixed-clocký€•Dvirt_12m_ckã fixed-clocký·•virt_13m_ckã fixed-clockýÆ]@•virt_19200000_ckã fixed-clocký$ø•virt_26000000_ckã fixed-clockýŒº€•virt_38_4m_ckã fixed-clockýIð•dpll4_ck@d00ãti,omap3-dpll-per-clock¡� D 0•!dpll4_m2_ck@d48ãti,divider-clock¡! ?� H•$dpll4_m2x2_mul_ckãfixed-factor-clock¡$/:•%dpll4_m2x2_ck@d00ãti,gate-clock¡%ð� D•&omap_96m_alwon_fckãfixed-factor-clock¡&/:•-dpll3_ck@d00ãti,omap3-dpll-core-clock¡� @ 0•dpll3_m3_ck@1140ãti,divider-clock¡ð �@•'dpll3_m3x2_mul_ckãfixed-factor-clock¡'/:•(dpll3_m3x2_ck@d00ãti,gate-clock¡(ð � D•)emu_core_alwon_ckãfixed-factor-clock¡)/:•fsys_altclkã fixed-clocký•2mcbsp_clksã fixed-clocký•dpll3_m2_ck@d40ãti,divider-clock¡ð � @• core_ckãfixed-factor-clock¡ /:•*dpll1_fck@940ãti,divider-clock¡*ð � @•+dpll1_ck@904ãti,omap3-dpll-clock¡+�  $ @ 4•dpll1_x2_ckãfixed-factor-clock¡/:•,dpll1_x2m2_ck@944ãti,divider-clock¡, � D•@cm_96m_fckãfixed-factor-clock¡-/:•.omap_96m_fck@d40ã ti,mux-clock¡.ð� @•Idpll4_m3_ck@e40ãti,divider-clock¡!ð �@•/dpll4_m3x2_mul_ckãfixed-factor-clock¡//:•0dpll4_m3x2_ck@d00ãti,gate-clock¡0ð� D•1omap_54m_fck@d40ã ti,mux-clock¡12ð� @•<cm_96m_d2_fckãfixed-factor-clock¡./:•3omap_48m_fck@d40ã ti,mux-clock¡32ð� @•4omap_12m_fckãfixed-factor-clock¡4/:•Kdpll4_m4_ck@e40ãti,divider-clock¡! �@•5dpll4_m4x2_mul_ckãti,fixed-factor-clock¡5Zhu•6dpll4_m4x2_ck@d00ãti,gate-clock¡6ð� Du•xdpll4_m5_ck@f40ãti,divider-clock¡! ?�@•7dpll4_m5x2_mul_ckãti,fixed-factor-clock¡7Zhu•8dpll4_m5x2_ck@d00ãti,gate-clock¡8ð� Dudpll4_m6_ck@1140ãti,divider-clock¡!ð ?�@•9dpll4_m6x2_mul_ckãfixed-factor-clock¡9/:•:dpll4_m6x2_ck@d00ãti,gate-clock¡:ð� D•;emu_per_alwon_ckãfixed-factor-clock¡;/:•gclkout2_src_gate_ck@d70ã ti,composite-no-wait-gate-clock¡*ð� p•=clkout2_src_mux_ck@d70ãti,composite-mux-clock¡*.<� p•>clkout2_src_ckãti,composite-clock¡=>•?sys_clkout2@d70ãti,divider-clock¡?ð @� pˆmpu_ckãfixed-factor-clock¡@/:•Aarm_fck@924ãti,divider-clock¡A� $ emu_mpu_alwon_ckãfixed-factor-clock¡A/:•hl3_ick@a40ãti,divider-clock¡* � @•Bl4_ick@a40ãti,divider-clock¡Bð � @•Crm_ick@c40ãti,divider-clock¡Cð � @gpt10_gate_fck@a00ãti,composite-gate-clock¡ð � •Egpt10_mux_fck@a40ãti,composite-mux-clock¡Dð� @•Fgpt10_fckãti,composite-clock¡EFgpt11_gate_fck@a00ãti,composite-gate-clock¡ð � •Ggpt11_mux_fck@a40ãti,composite-mux-clock¡Dð� @•Hgpt11_fckãti,composite-clock¡GHcore_96m_fckãfixed-factor-clock¡I/:•mmchs2_fck@a00ãti,wait-gate-clock¡� ð•¦mmchs1_fck@a00ãti,wait-gate-clock¡� ð•§i2c3_fck@a00ãti,wait-gate-clock¡� ð•¨i2c2_fck@a00ãti,wait-gate-clock¡� ð•©i2c1_fck@a00ãti,wait-gate-clock¡� ð•ªmcbsp5_gate_fck@a00ãti,composite-gate-clock¡ð � • mcbsp1_gate_fck@a00ãti,composite-gate-clock¡ð � • core_48m_fckãfixed-factor-clock¡4/:•Jmcspi4_fck@a00ãti,wait-gate-clock¡J� ð•«mcspi3_fck@a00ãti,wait-gate-clock¡J� ð•¬mcspi2_fck@a00ãti,wait-gate-clock¡J� ð•­mcspi1_fck@a00ãti,wait-gate-clock¡J� ð•®uart2_fck@a00ãti,wait-gate-clock¡J� ð•¯uart1_fck@a00ãti,wait-gate-clock¡J� ð •°core_12m_fckãfixed-factor-clock¡K/:•Lhdq_fck@a00ãti,wait-gate-clock¡L� ð•±core_l3_ickãfixed-factor-clock¡B/:•Msdrc_ick@a10ãti,wait-gate-clock¡M� ð•ygpmc_fckãfixed-factor-clock¡M/:core_l4_ickãfixed-factor-clock¡C/:•Nmmchs2_ick@a10ãti,omap3-interface-clock¡N� ð•²mmchs1_ick@a10ãti,omap3-interface-clock¡N� ð•³hdq_ick@a10ãti,omap3-interface-clock¡N� ð•´mcspi4_ick@a10ãti,omap3-interface-clock¡N� ð•µmcspi3_ick@a10ãti,omap3-interface-clock¡N� ð•¶mcspi2_ick@a10ãti,omap3-interface-clock¡N� ð•·mcspi1_ick@a10ãti,omap3-interface-clock¡N� ð•¸i2c3_ick@a10ãti,omap3-interface-clock¡N� ð•¹i2c2_ick@a10ãti,omap3-interface-clock¡N� ð•ºi2c1_ick@a10ãti,omap3-interface-clock¡N� ð•»uart2_ick@a10ãti,omap3-interface-clock¡N� ð•¼uart1_ick@a10ãti,omap3-interface-clock¡N� ð •½gpt11_ick@a10ãti,omap3-interface-clock¡N� ð •¾gpt10_ick@a10ãti,omap3-interface-clock¡N� ð •¿mcbsp5_ick@a10ãti,omap3-interface-clock¡N� ð •Àmcbsp1_ick@a10ãti,omap3-interface-clock¡N� ð •Áomapctrl_ick@a10ãti,omap3-interface-clock¡N� ð•Âdss_tv_fck@e00ãti,gate-clock¡<�ð•¡dss_96m_fck@e00ãti,gate-clock¡I�ð•¢dss2_alwon_fck@e00ãti,gate-clock¡�ð•£dummy_ckã fixed-clockýgpt1_gate_fck@c00ãti,composite-gate-clock¡ð� •Ogpt1_mux_fck@c40ãti,composite-mux-clock¡D� @•Pgpt1_fckãti,composite-clock¡OP•åaes2_ick@a10ãti,omap3-interface-clock¡Nð� •Ãwkup_32k_fckãfixed-factor-clock¡D/:•Qgpio1_dbck@c00ãti,gate-clock¡Q� ð•™sha12_ick@a10ãti,omap3-interface-clock¡N� ð•Äwdt2_fck@c00ãti,wait-gate-clock¡Q� ð•šwdt2_ick@c10ãti,omap3-interface-clock¡R� ð•›wdt1_ick@c10ãti,omap3-interface-clock¡R� ð•œgpio1_ick@c10ãti,omap3-interface-clock¡R� ð•�omap_32ksync_ick@c10ãti,omap3-interface-clock¡R� ð•žgpt12_ick@c10ãti,omap3-interface-clock¡R� ð•Ÿgpt1_ick@c10ãti,omap3-interface-clock¡R� ð• per_96m_fckãfixed-factor-clock¡-/:• per_48m_fckãfixed-factor-clock¡4/:•Suart3_fck@1000ãti,wait-gate-clock¡S�ð •gpt2_gate_fck@1000ãti,composite-gate-clock¡ð�•Tgpt2_mux_fck@1040ãti,composite-mux-clock¡D�@•Ugpt2_fckãti,composite-clock¡TU•ægpt3_gate_fck@1000ãti,composite-gate-clock¡ð�•Vgpt3_mux_fck@1040ãti,composite-mux-clock¡Dð�@•Wgpt3_fckãti,composite-clock¡VWgpt4_gate_fck@1000ãti,composite-gate-clock¡ð�•Xgpt4_mux_fck@1040ãti,composite-mux-clock¡Dð�@•Ygpt4_fckãti,composite-clock¡XYgpt5_gate_fck@1000ãti,composite-gate-clock¡ð�•Zgpt5_mux_fck@1040ãti,composite-mux-clock¡Dð�@•[gpt5_fckãti,composite-clock¡Z[gpt6_gate_fck@1000ãti,composite-gate-clock¡ð�•\gpt6_mux_fck@1040ãti,composite-mux-clock¡Dð�@•]gpt6_fckãti,composite-clock¡\]gpt7_gate_fck@1000ãti,composite-gate-clock¡ð�•^gpt7_mux_fck@1040ãti,composite-mux-clock¡Dð�@•_gpt7_fckãti,composite-clock¡^_gpt8_gate_fck@1000ãti,composite-gate-clock¡ð �•`gpt8_mux_fck@1040ãti,composite-mux-clock¡Dð�@•agpt8_fckãti,composite-clock¡`agpt9_gate_fck@1000ãti,composite-gate-clock¡ð �•bgpt9_mux_fck@1040ãti,composite-mux-clock¡Dð�@•cgpt9_fckãti,composite-clock¡bcper_32k_alwon_fckãfixed-factor-clock¡D/:•dgpio6_dbck@1000ãti,gate-clock¡d�ð•€gpio5_dbck@1000ãti,gate-clock¡d�ð•�gpio4_dbck@1000ãti,gate-clock¡d�ð•‚gpio3_dbck@1000ãti,gate-clock¡d�ð•ƒgpio2_dbck@1000ãti,gate-clock¡d�ð •„wdt3_fck@1000ãti,wait-gate-clock¡d�ð •…per_l4_ickãfixed-factor-clock¡C/:•egpio6_ick@1010ãti,omap3-interface-clock¡e�ð•†gpio5_ick@1010ãti,omap3-interface-clock¡e�ð•‡gpio4_ick@1010ãti,omap3-interface-clock¡e�ð•ˆgpio3_ick@1010ãti,omap3-interface-clock¡e�ð•‰gpio2_ick@1010ãti,omap3-interface-clock¡e�ð •Šwdt3_ick@1010ãti,omap3-interface-clock¡e�ð •‹uart3_ick@1010ãti,omap3-interface-clock¡e�ð •Œuart4_ick@1010ãti,omap3-interface-clock¡e�ð•�gpt9_ick@1010ãti,omap3-interface-clock¡e�ð •Žgpt8_ick@1010ãti,omap3-interface-clock¡e�ð •�gpt7_ick@1010ãti,omap3-interface-clock¡e�ð•�gpt6_ick@1010ãti,omap3-interface-clock¡e�ð•‘gpt5_ick@1010ãti,omap3-interface-clock¡e�ð•’gpt4_ick@1010ãti,omap3-interface-clock¡e�ð•“gpt3_ick@1010ãti,omap3-interface-clock¡e�ð•”gpt2_ick@1010ãti,omap3-interface-clock¡e�ð••mcbsp2_ick@1010ãti,omap3-interface-clock¡e�ð•–mcbsp3_ick@1010ãti,omap3-interface-clock¡e�ð•—mcbsp4_ick@1010ãti,omap3-interface-clock¡e�ð•˜mcbsp2_gate_fck@1000ãti,composite-gate-clock¡ð�•mcbsp3_gate_fck@1000ãti,composite-gate-clock¡ð�•mcbsp4_gate_fck@1000ãti,composite-gate-clock¡ð�•emu_src_mux_ck@1140ã ti,mux-clock¡fgh�@•iemu_src_ckãti,clkdm-gate-clock¡i•jpclk_fck@1140ãti,divider-clock¡jð �@pclkx2_fck@1140ãti,divider-clock¡jð �@atclk_fck@1140ãti,divider-clock¡jð �@traceclk_src_fck@1140ã ti,mux-clock¡fghð�@•ktraceclk_fck@1140ãti,divider-clock¡kð  �@secure_32k_fckã fixed-clocký€•lgpt12_fckãfixed-factor-clock¡l/:•çwdt1_fckãfixed-factor-clock¡l/:ipss_ick@a10ãti,am35xx-interface-clock¡M� ð•rmii_ckã fixed-clockýúð€•pclk_ckã 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¤ads7846-reg³2Z Ë2Z •Õsvideo-connectorsvideo-connectorytvportendpointaü•ñregulator-vmmcregulator-fixed¤vmmc³2Z Ë2Z •Úwl12xx_vmmc2regulator-fixed¤vw1271idefaultwýþ³w@Ëw@ ðÿ lN  ”•Ýwl12xx_vaux2regulator-fixed¤vwl1271_vaux2³w@Ëw@•Þencoder ti,tfp410 §Öidefaultwports+port@0�endpointa•òport@1�endpointa•dvi-connectordvi-connectorydviportendpointa•audio_ampregulator-fixed ¤audio_ampidefaultw ðÖ ·regulator-vddvario-sb-t35regulator-fixed ¤vddvario ·•íregulator-vdd33a-sb-t35regulator-fixed¤vdd33a ·•î compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2serial3candisplay0display1device_typeregclocksclock-namesclock-latencyoperating-points-v2interruptsti,hwmodsstatusranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockreg-namesti,sysc-sidleti,sysc-maskti,sysc-midleti,syss-mask#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendeddmasdma-namespagesize#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-repwakeup-sourceti,dual-voltpbias-supplybus-widthvmmc-supplywp-gpioscd-gpiosvqmmc-supplynon-removablecap-power-off-cardref-clock-frequency#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport1-modeport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,page-burst-access-nsgpmc,access-nsgpmc,cycle2cycle-delay-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,bus-turnaround-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsremote-endpointti,channelsdata-linesti,davinci-ctrl-reg-offsetti,davinci-ctrl-mod-reg-offsetti,davinci-ctrl-ram-offsetti,davinci-ctrl-ram-sizeti,davinci-rmii-enlocal-mac-addressbus_freqopp-hzopp-microvoltopp-supported-hwopp-suspendlinux,default-triggerstartup-delay-us#phy-cellsreset-gpiosenable-active-highpowerdown-gpiosregulator-always-on