Ð þí U8ý¼( ™ý„Qgumstix,omap3-overo-tobiduogumstix,omap3-overoti,omap3630ti,omap36xxti,omap3 +07OMAP36xx/AM37xx/DM37xx Gumstix Overo on TobiDuochosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000s/ocp@68000000/serial@49042000cpus+cpu@0arm,cortex-a8{cpu‡‹’cpuž“à¬ÀËÚpmu@54000000arm,cortex-a8-pmu‡T€âídebugsssocti,omap-inframpu ti,omap3-mpuímpuiva ti,iva2.2íivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus‡hâ +÷íl3_mainl4@48000000ti,omap3-l4-coresimple-bus+ ÷Hscm@2000ti,omap3-scmsimple-bus‡ + ÷ pinmux@30 ti,omap3-padconfpinctrl-single‡08+þ 3Qÿndefault|Úèpinmux_uart2_pins †<>@BÚçpinmux_i2c1_pins†ŠŒÚêpinmux_mmc1_pins0†Úõpinmux_mmc2_pins0†(*,.02Ú÷pinmux_w3cbw003c_pins†„lÚpinmux_hsusb2_pins@†¤ ¦ ¨ ª ¬ ® Ž�Úpinmux_twl4030_pins†°AÚëpinmux_i2c3_pins†’”Úñpinmux_uart3_pins†npÚéscm_conf@270sysconsimple-bus‡p0+ ÷p0Úpbias_regulator@2b0ti,pbias-omap3ti,pbias-omap‡°špbias_mmc_omap2430¡pbias_mmc_omap2430°w@È-ÆÀÚôclocks+mcbsp5_mux_fck@68àti,composite-mux-clock‹í‡hÚ mcbsp5_fckàti,composite-clock‹ Úÿmcbsp1_mux_fck@4àti,composite-mux-clock‹í‡Ú mcbsp1_fckàti,composite-clock‹ Úúmcbsp2_mux_fck@4àti,composite-mux-clock‹ í‡Úmcbsp2_fckàti,composite-clock‹Úümcbsp3_mux_fck@68àti,composite-mux-clock‹ ‡hÚmcbsp3_fckàti,composite-clock‹Úýmcbsp4_mux_fck@68àti,composite-mux-clock‹ í‡hÚmcbsp4_fckàti,composite-clock‹Úþclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single‡ \+þ 3Qÿpinmux_twl4030_vpins †Úìtarget-module@480a6000ti,sysc-omap2ti,sysc‡H `DH `HH `Lúrevsyscsyss ‹’ick+ ÷H ` aes1@0 ti,omap3-aes‡Pâ,  1txrxtarget-module@480c5000ti,sysc-omap2ti,sysc‡H PDH PHH PLúrevsyscsyss ‹’ick+ ÷H P aes2@0 ti,omap3-aes‡Pâ,AB1txrxprm@48306000 ti,omap3-prm‡H0`@â clocks+virt_16_8m_ckà fixed-clock;YÚosc_sys_ck@d40à ti,mux-clock‹‡ @Úsys_ck@1270àti,divider-clock‹íK‡pVÚ"sys_clkout1@d70àti,gate-clock‹‡ pídpll3_x2_ckàfixed-factor-clock‹mxdpll3_m2x2_ckàfixed-factor-clock‹mxÚ!dpll4_x2_ckàfixed-factor-clock‹ mxcorex2_fckàfixed-factor-clock‹!mxÚ#wkup_l4_ickàfixed-factor-clock‹"mxÚRcorex2_d3_fckàfixed-factor-clock‹#mxÚ‰corex2_d5_fckàfixed-factor-clock‹#mxÚŠclockdomainscm@48004000 ti,omap3-cm‡H@@clocks+dummy_apb_pclkà fixed-clock;omap_32k_fckà fixed-clock;€ÚDvirt_12m_ckà fixed-clock;·Úvirt_13m_ckà fixed-clock;Æ]@Úvirt_19200000_ckà fixed-clock;$øÚvirt_26000000_ckà fixed-clock;Œº€Úvirt_38_4m_ckà fixed-clock;IðÚdpll4_ck@d00àti,omap3-dpll-per-j-type-clock‹""‡ D 0Ú dpll4_m2_ck@d48àti,divider-clock‹ K?‡ HVÚ$dpll4_m2x2_mul_ckàfixed-factor-clock‹$mxÚ%dpll4_m2x2_ck@d00àti,hsdiv-gate-clock‹%í‡ ‚Ú&omap_96m_alwon_fckàfixed-factor-clock‹&mxÚ-dpll3_ck@d00àti,omap3-dpll-core-clock‹""‡ @ 0Údpll3_m3_ck@1140àti,divider-clock‹íK‡@VÚ'dpll3_m3x2_mul_ckàfixed-factor-clock‹'mxÚ(dpll3_m3x2_ck@d00àti,hsdiv-gate-clock‹(í ‡ ‚Ú)emu_core_alwon_ckàfixed-factor-clock‹)mxÚfsys_altclkà fixed-clock;Ú2mcbsp_clksà fixed-clock;Údpll3_m2_ck@d40àti,divider-clock‹íK‡ @VÚcore_ckàfixed-factor-clock‹mxÚ*dpll1_fck@940àti,divider-clock‹*íK‡ @VÚ+dpll1_ck@904àti,omap3-dpll-clock‹"+‡  $ @ 4Údpll1_x2_ckàfixed-factor-clock‹mxÚ,dpll1_x2m2_ck@944àti,divider-clock‹,K‡ DVÚ@cm_96m_fckàfixed-factor-clock‹-mxÚ.omap_96m_fck@d40à ti,mux-clock‹."í‡ @ÚIdpll4_m3_ck@e40àti,divider-clock‹ íK ‡@VÚ/dpll4_m3x2_mul_ckàfixed-factor-clock‹/mxÚ0dpll4_m3x2_ck@d00àti,hsdiv-gate-clock‹0í‡ ‚Ú1omap_54m_fck@d40à ti,mux-clock‹12í‡ @Ú<cm_96m_d2_fckàfixed-factor-clock‹.mxÚ3omap_48m_fck@d40à ti,mux-clock‹32í‡ @Ú4omap_12m_fckàfixed-factor-clock‹4mxÚKdpll4_m4_ck@e40àti,divider-clock‹ K‡@VÚ5dpll4_m4x2_mul_ckàti,fixed-factor-clock‹5˜¦³Ú6dpll4_m4x2_ck@d00àti,gate-clock‹6í‡ ‚³Ú�dpll4_m5_ck@f40àti,divider-clock‹ K?‡@VÚ7dpll4_m5x2_mul_ckàti,fixed-factor-clock‹7˜¦³Ú8dpll4_m5x2_ck@d00àti,hsdiv-gate-clock‹8í‡ ‚³Úndpll4_m6_ck@1140àti,divider-clock‹ íK?‡@VÚ9dpll4_m6x2_mul_ckàfixed-factor-clock‹9mxÚ:dpll4_m6x2_ck@d00àti,hsdiv-gate-clock‹:í‡ ‚Ú;emu_per_alwon_ckàfixed-factor-clock‹;mxÚgclkout2_src_gate_ck@d70à ti,composite-no-wait-gate-clock‹*í‡ pÚ=clkout2_src_mux_ck@d70àti,composite-mux-clock‹*".<‡ pÚ>clkout2_src_ckàti,composite-clock‹=>Ú?sys_clkout2@d70àti,divider-clock‹?íK@‡ pÆmpu_ckàfixed-factor-clock‹@mxÚAarm_fck@924àti,divider-clock‹A‡ $Kemu_mpu_alwon_ckàfixed-factor-clock‹AmxÚhl3_ick@a40àti,divider-clock‹*K‡ @VÚBl4_ick@a40àti,divider-clock‹BíK‡ @VÚCrm_ick@c40àti,divider-clock‹CíK‡ @Vgpt10_gate_fck@a00àti,composite-gate-clock‹"í ‡ ÚEgpt10_mux_fck@a40àti,composite-mux-clock‹D"í‡ @ÚFgpt10_fckàti,composite-clock‹EFgpt11_gate_fck@a00àti,composite-gate-clock‹"í ‡ ÚGgpt11_mux_fck@a40àti,composite-mux-clock‹D"í‡ @ÚHgpt11_fckàti,composite-clock‹GHcore_96m_fckàfixed-factor-clock‹ImxÚmmchs2_fck@a00àti,wait-gate-clock‹‡ íÚ¹mmchs1_fck@a00àti,wait-gate-clock‹‡ íÚºi2c3_fck@a00àti,wait-gate-clock‹‡ íÚ»i2c2_fck@a00àti,wait-gate-clock‹‡ íÚ¼i2c1_fck@a00àti,wait-gate-clock‹‡ íÚ½mcbsp5_gate_fck@a00àti,composite-gate-clock‹í ‡ Ú mcbsp1_gate_fck@a00àti,composite-gate-clock‹í ‡ Ú core_48m_fckàfixed-factor-clock‹4mxÚJmcspi4_fck@a00àti,wait-gate-clock‹J‡ íÚ¾mcspi3_fck@a00àti,wait-gate-clock‹J‡ íÚ¿mcspi2_fck@a00àti,wait-gate-clock‹J‡ íÚÀmcspi1_fck@a00àti,wait-gate-clock‹J‡ íÚÁuart2_fck@a00àti,wait-gate-clock‹J‡ íÚÂuart1_fck@a00àti,wait-gate-clock‹J‡ í ÚÃcore_12m_fckàfixed-factor-clock‹KmxÚLhdq_fck@a00àti,wait-gate-clock‹L‡ íÚÄcore_l3_ickàfixed-factor-clock‹BmxÚMsdrc_ick@a10àti,wait-gate-clock‹M‡ íÚŽgpmc_fckàfixed-factor-clock‹Mmxcore_l4_ickàfixed-factor-clock‹CmxÚNmmchs2_ick@a10àti,omap3-interface-clock‹N‡ íÚÅmmchs1_ick@a10àti,omap3-interface-clock‹N‡ íÚÆhdq_ick@a10àti,omap3-interface-clock‹N‡ íÚÇmcspi4_ick@a10àti,omap3-interface-clock‹N‡ íÚÈmcspi3_ick@a10àti,omap3-interface-clock‹N‡ íÚÉmcspi2_ick@a10àti,omap3-interface-clock‹N‡ íÚÊmcspi1_ick@a10àti,omap3-interface-clock‹N‡ íÚËi2c3_ick@a10àti,omap3-interface-clock‹N‡ íÚÌi2c2_ick@a10àti,omap3-interface-clock‹N‡ íÚÍi2c1_ick@a10àti,omap3-interface-clock‹N‡ íÚÎuart2_ick@a10àti,omap3-interface-clock‹N‡ íÚÏuart1_ick@a10àti,omap3-interface-clock‹N‡ í ÚÐgpt11_ick@a10àti,omap3-interface-clock‹N‡ í ÚÑgpt10_ick@a10àti,omap3-interface-clock‹N‡ í ÚÒmcbsp5_ick@a10àti,omap3-interface-clock‹N‡ í ÚÓmcbsp1_ick@a10àti,omap3-interface-clock‹N‡ í ÚÔomapctrl_ick@a10àti,omap3-interface-clock‹N‡ íÚÕdss_tv_fck@e00àti,gate-clock‹<‡íÚ´dss_96m_fck@e00àti,gate-clock‹I‡íÚµdss2_alwon_fck@e00àti,gate-clock‹"‡íÚ¶dummy_ckà fixed-clock;gpt1_gate_fck@c00àti,composite-gate-clock‹"í‡ ÚOgpt1_mux_fck@c40àti,composite-mux-clock‹D"‡ @ÚPgpt1_fckàti,composite-clock‹OPÚaes2_ick@a10àti,omap3-interface-clock‹Ní‡ Úwkup_32k_fckàfixed-factor-clock‹DmxÚQgpio1_dbck@c00àti,gate-clock‹Q‡ íÚ«sha12_ick@a10àti,omap3-interface-clock‹N‡ íÚÖwdt2_fck@c00àti,wait-gate-clock‹Q‡ íÚ¬wdt2_ick@c10àti,omap3-interface-clock‹R‡ íÚ­wdt1_ick@c10àti,omap3-interface-clock‹R‡ íÚ®gpio1_ick@c10àti,omap3-interface-clock‹R‡ íÚ¯omap_32ksync_ick@c10àti,omap3-interface-clock‹R‡ íÚ°gpt12_ick@c10àti,omap3-interface-clock‹R‡ íÚ±gpt1_ick@c10àti,omap3-interface-clock‹R‡ íÚ²per_96m_fckàfixed-factor-clock‹-mxÚ per_48m_fckàfixed-factor-clock‹4mxÚSuart3_fck@1000àti,wait-gate-clock‹S‡í Ú�gpt2_gate_fck@1000àti,composite-gate-clock‹"í‡ÚTgpt2_mux_fck@1040àti,composite-mux-clock‹D"‡@ÚUgpt2_fckàti,composite-clock‹TUÚgpt3_gate_fck@1000àti,composite-gate-clock‹"í‡ÚVgpt3_mux_fck@1040àti,composite-mux-clock‹D"í‡@ÚWgpt3_fckàti,composite-clock‹VWgpt4_gate_fck@1000àti,composite-gate-clock‹"í‡ÚXgpt4_mux_fck@1040àti,composite-mux-clock‹D"í‡@ÚYgpt4_fckàti,composite-clock‹XYgpt5_gate_fck@1000àti,composite-gate-clock‹"í‡ÚZgpt5_mux_fck@1040àti,composite-mux-clock‹D"í‡@Ú[gpt5_fckàti,composite-clock‹Z[gpt6_gate_fck@1000àti,composite-gate-clock‹"í‡Ú\gpt6_mux_fck@1040àti,composite-mux-clock‹D"í‡@Ú]gpt6_fckàti,composite-clock‹\]gpt7_gate_fck@1000àti,composite-gate-clock‹"í‡Ú^gpt7_mux_fck@1040àti,composite-mux-clock‹D"í‡@Ú_gpt7_fckàti,composite-clock‹^_gpt8_gate_fck@1000àti,composite-gate-clock‹"í ‡Ú`gpt8_mux_fck@1040àti,composite-mux-clock‹D"í‡@Úagpt8_fckàti,composite-clock‹`agpt9_gate_fck@1000àti,composite-gate-clock‹"í ‡Úbgpt9_mux_fck@1040àti,composite-mux-clock‹D"í‡@Úcgpt9_fckàti,composite-clock‹bcper_32k_alwon_fckàfixed-factor-clock‹DmxÚdgpio6_dbck@1000àti,gate-clock‹d‡íÚ‘gpio5_dbck@1000àti,gate-clock‹d‡íÚ’gpio4_dbck@1000àti,gate-clock‹d‡íÚ“gpio3_dbck@1000àti,gate-clock‹d‡íÚ”gpio2_dbck@1000àti,gate-clock‹d‡í Ú•wdt3_fck@1000àti,wait-gate-clock‹d‡í Ú–per_l4_ickàfixed-factor-clock‹CmxÚegpio6_ick@1010àti,omap3-interface-clock‹e‡íÚ—gpio5_ick@1010àti,omap3-interface-clock‹e‡íÚ˜gpio4_ick@1010àti,omap3-interface-clock‹e‡íÚ™gpio3_ick@1010àti,omap3-interface-clock‹e‡íÚšgpio2_ick@1010àti,omap3-interface-clock‹e‡í Ú›wdt3_ick@1010àti,omap3-interface-clock‹e‡í Úœuart3_ick@1010àti,omap3-interface-clock‹e‡í Ú�uart4_ick@1010àti,omap3-interface-clock‹e‡íÚžgpt9_ick@1010àti,omap3-interface-clock‹e‡í ÚŸgpt8_ick@1010àti,omap3-interface-clock‹e‡í Ú gpt7_ick@1010àti,omap3-interface-clock‹e‡íÚ¡gpt6_ick@1010àti,omap3-interface-clock‹e‡íÚ¢gpt5_ick@1010àti,omap3-interface-clock‹e‡íÚ£gpt4_ick@1010àti,omap3-interface-clock‹e‡íÚ¤gpt3_ick@1010àti,omap3-interface-clock‹e‡íÚ¥gpt2_ick@1010àti,omap3-interface-clock‹e‡íÚ¦mcbsp2_ick@1010àti,omap3-interface-clock‹e‡íÚ§mcbsp3_ick@1010àti,omap3-interface-clock‹e‡íÚ¨mcbsp4_ick@1010àti,omap3-interface-clock‹e‡íÚ©mcbsp2_gate_fck@1000àti,composite-gate-clock‹í‡Úmcbsp3_gate_fck@1000àti,composite-gate-clock‹í‡Úmcbsp4_gate_fck@1000àti,composite-gate-clock‹í‡Úemu_src_mux_ck@1140à ti,mux-clock‹"fgh‡@Úiemu_src_ckàti,clkdm-gate-clock‹iÚjpclk_fck@1140àti,divider-clock‹jíK‡@Vpclkx2_fck@1140àti,divider-clock‹jíK‡@Vatclk_fck@1140àti,divider-clock‹jíK‡@Vtraceclk_src_fck@1140à ti,mux-clock‹"fghí‡@Úktraceclk_fck@1140àti,divider-clock‹kí K‡@Vsecure_32k_fckà fixed-clock;€Úlgpt12_fckàfixed-factor-clock‹lmxÚwdt1_fckàfixed-factor-clock‹lmxsecurity_l4_ick2àfixed-factor-clock‹CmxÚmaes1_ick@a14àti,omap3-interface-clock‹mí‡ Úrng_ick@a14àti,omap3-interface-clock‹m‡ íÚûsha11_ick@a14àti,omap3-interface-clock‹m‡ ídes1_ick@a14àti,omap3-interface-clock‹m‡ ícam_mclk@f00àti,gate-clock‹n퇳cam_ick@f10à!ti,omap3-no-wait-interface-clock‹C‡íÚÝcsi2_96m_fck@f00àti,gate-clock‹‡íÚÞsecurity_l3_ickàfixed-factor-clock‹BmxÚopka_ick@a14àti,omap3-interface-clock‹o‡ íicr_ick@a10àti,omap3-interface-clock‹N‡ ídes2_ick@a10àti,omap3-interface-clock‹N‡ ímspro_ick@a10àti,omap3-interface-clock‹N‡ ímailboxes_ick@a10àti,omap3-interface-clock‹N‡ íssi_l4_ickàfixed-factor-clock‹CmxÚvsr1_fck@c00àti,wait-gate-clock‹"‡ íÚsr2_fck@c00àti,wait-gate-clock‹"‡ íÚsr_l4_ickàfixed-factor-clock‹Cmxdpll2_fck@40àti,divider-clock‹*íK‡@VÚpdpll2_ck@4àti,omap3-dpll-clock‹"p‡$@4ÜîöÚqdpll2_m2_ck@44àti,divider-clock‹qK‡DVÚriva2_ck@0àti,wait-gate-clock‹r‡íÚßmodem_fck@a00àti,omap3-interface-clock‹"‡ íÚàsad2d_ick@a10àti,omap3-interface-clock‹B‡ íÚámad2d_ick@a18àti,omap3-interface-clock‹B‡ íÚâmspro_fck@a00àti,wait-gate-clock‹‡ íssi_ssr_gate_fck_3430es2@a00à ti,composite-no-wait-gate-clock‹#í‡ Ússsi_ssr_div_fck_3430es2@a40àti,composite-divider-clock‹#í‡ @$ Útssi_ssr_fck_3430es2àti,composite-clock‹stÚussi_sst_fck_3430es2àfixed-factor-clock‹umxÚ hsotgusb_ick_3430es2@a10à"ti,omap3-hsotgusb-interface-clock‹M‡ íÚ�ssi_ick_3430es2@a10àti,omap3-ssi-interface-clock‹v‡ íÚ usim_gate_fck@c00àti,composite-gate-clock‹Ií ‡ Ú�sys_d2_ckàfixed-factor-clock‹"mxÚxomap_96m_d2_fckàfixed-factor-clock‹ImxÚyomap_96m_d4_fckàfixed-factor-clock‹ImxÚzomap_96m_d8_fckàfixed-factor-clock‹ImxÚ{omap_96m_d10_fckàfixed-factor-clock‹Imx Ú|dpll5_m2_d4_ckàfixed-factor-clock‹wmxÚ}dpll5_m2_d8_ckàfixed-factor-clock‹wmxÚ~dpll5_m2_d16_ckàfixed-factor-clock‹wmxÚdpll5_m2_d20_ckàfixed-factor-clock‹wmxÚ€usim_mux_fck@c40àti,composite-mux-clock(‹"xyz{|}~€í‡ @VÚ‚usim_fckàti,composite-clock‹�‚usim_ick@c10àti,omap3-interface-clock‹R‡ í Ú³dpll5_ck@d04àti,omap3-dpll-clock‹""‡  $ L 4ÜîÚƒdpll5_m2_ck@d50àti,divider-clock‹ƒK‡ PVÚwsgx_gate_fck@b00àti,composite-gate-clock‹*í‡ Ú‹core_d3_ckàfixed-factor-clock‹*mxÚ„core_d4_ckàfixed-factor-clock‹*mxÚ…core_d6_ckàfixed-factor-clock‹*mxÚ†omap_192m_alwon_fckàfixed-factor-clock‹&mxÚ‡core_d2_ckàfixed-factor-clock‹*mxÚˆsgx_mux_fck@b40àti,composite-mux-clock ‹„…†.‡ˆ‰Š‡ @ÚŒsgx_fckàti,composite-clock‹‹ŒÚsgx_ick@b10àti,wait-gate-clock‹B‡ íÚãcpefuse_fck@a08àti,gate-clock‹"‡ íÚ×ts_fck@a08àti,gate-clock‹D‡ íÚØusbtll_fck@a08àti,wait-gate-clock‹w‡ íÚÙusbtll_ick@a18àti,omap3-interface-clock‹N‡ íÚÚmmchs3_ick@a10àti,omap3-interface-clock‹N‡ íÚÛmmchs3_fck@a00àti,wait-gate-clock‹‡ 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-points-v2vbb-supply#cooling-cellsphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsstatuspagesizeVdd-supplyVdd_IO-supplyst,click-single-xst,click-single-yst,click-single-zst,click-thresh-xst,click-thresh-yst,click-thresh-zst,irq1-clickst,irq2-clickst,wakeup-x-lost,wakeup-x-hist,wakeup-y-lost,wakeup-y-hist,wakeup-z-lost,wakeup-z-hist,min-limit-xst,min-limit-yst,min-limit-zst,max-limit-xst,max-limit-yst,max-limit-z#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplybus-widthvqmmc-supplycap-sdio-irqnon-removable#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modeti,absolute-max-voltage-uvpolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicepwmsmax-brightnesslinux,default-triggerti,modelti,mcbspgpiostartup-delay-usenable-active-highreset-gpiosvcc-supplyregulator-always-on