Ð þíØ8ý( ØüÈPgumstix,omap3-overo-summitgumstix,omap3-overoti,omap3630ti,omap36xxti,omap3 +/7OMAP36xx/AM37xx/DM37xx Gumstix Overo on Summitchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000s/ocp@68000000/serial@49042000 {/connectorcpus+cpu@0arm,cortex-a8„cpu�”›cpu§“àµÉÔãpmu@54000000arm,cortex-a8-pmu�T€ëödebugsssocti,omap-inframpu ti,omap3-mpuömpuiva ti,iva2.2öivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus�hë +öl3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus� +  pinmux@30 ti,omap3-padconfpinctrl-single�08+'<Zÿwdefault…ãèpinmux_uart2_pins �<>@Bãçpinmux_i2c1_pins�ŠŒãêpinmux_mmc1_pins0�ãõpinmux_mmc2_pins0�(*,.02ã÷pinmux_w3cbw003c_pins�„lãpinmux_hsusb2_pins@�¤ ¦ ¨ ª ¬ ® Ž�ãpinmux_twl4030_pins�°Aãëpinmux_i2c3_pins�’”ãñpinmux_uart3_pins�npãépinmux_dss_dpi_pinsà�¤¦¨ª¬®°²´¶¸º¼¾ÀÂÄÆÈÊÌÎÐÒÔÖØÚãscm_conf@270sysconsimple-bus�p0+ p0ãpbias_regulator@2b0ti,pbias-omap3ti,pbias-omap�°£pbias_mmc_omap2430ªpbias_mmc_omap2430¹w@Ñ-ÆÀãôclocks+mcbsp5_mux_fck@68éti,composite-mux-clock”ö�hã mcbsp5_fckéti,composite-clock” ãÿmcbsp1_mux_fck@4éti,composite-mux-clock”ö�ã mcbsp1_fckéti,composite-clock” ãúmcbsp2_mux_fck@4éti,composite-mux-clock” ö�ãmcbsp2_fckéti,composite-clock”ãümcbsp3_mux_fck@68éti,composite-mux-clock” �hãmcbsp3_fckéti,composite-clock”ãýmcbsp4_mux_fck@68éti,composite-mux-clock” ö�hãmcbsp4_fckéti,composite-clock”ãþclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single� \+'<Zÿpinmux_twl4030_vpins �ãìtarget-module@480a6000ti,sysc-omap2ti,sysc�H `DH `HH `Lrevsyscsyss  (”›ick+ H ` aes1@0 ti,omap3-aes�Pë5  :txrxtarget-module@480c5000ti,sysc-omap2ti,sysc�H PDH PHH PLrevsyscsyss  (”›ick+ H P aes2@0 ti,omap3-aes�Pë5AB:txrxprm@48306000 ti,omap3-prm�H0`@ë clocks+virt_16_8m_cké fixed-clockDYãosc_sys_ck@d40é ti,mux-clock”� @ãsys_ck@1270éti,divider-clock”öT�p_ã"sys_clkout1@d70éti,gate-clock”� pödpll3_x2_ckéfixed-factor-clock”v�dpll3_m2x2_ckéfixed-factor-clock”v�ã!dpll4_x2_ckéfixed-factor-clock” v�corex2_fckéfixed-factor-clock”!v�ã#wkup_l4_ickéfixed-factor-clock”"v�ãRcorex2_d3_fckéfixed-factor-clock”#v�ã‰corex2_d5_fckéfixed-factor-clock”#v�ãŠclockdomainscm@48004000 ti,omap3-cm�H@@clocks+dummy_apb_pclké fixed-clockDomap_32k_fcké fixed-clockD€ãDvirt_12m_cké fixed-clockD·ãvirt_13m_cké fixed-clockDÆ]@ãvirt_19200000_cké fixed-clockD$øãvirt_26000000_cké fixed-clockDŒº€ãvirt_38_4m_cké fixed-clockDIðãdpll4_ck@d00éti,omap3-dpll-per-j-type-clock”""� D 0ã dpll4_m2_ck@d48éti,divider-clock” T?� H_ã$dpll4_m2x2_mul_ckéfixed-factor-clock”$v�ã%dpll4_m2x2_ck@d00éti,hsdiv-gate-clock”%ö� ‹ã&omap_96m_alwon_fckéfixed-factor-clock”&v�ã-dpll3_ck@d00éti,omap3-dpll-core-clock”""� @ 0ãdpll3_m3_ck@1140éti,divider-clock”öT�@_ã'dpll3_m3x2_mul_ckéfixed-factor-clock”'v�ã(dpll3_m3x2_ck@d00éti,hsdiv-gate-clock”(ö � ‹ã)emu_core_alwon_ckéfixed-factor-clock”)v�ãfsys_altclké fixed-clockDã2mcbsp_clksé fixed-clockDãdpll3_m2_ck@d40éti,divider-clock”öT� @_ãcore_ckéfixed-factor-clock”v�ã*dpll1_fck@940éti,divider-clock”*öT� @_ã+dpll1_ck@904éti,omap3-dpll-clock”"+�  $ @ 4ãdpll1_x2_ckéfixed-factor-clock”v�ã,dpll1_x2m2_ck@944éti,divider-clock”,T� D_ã@cm_96m_fckéfixed-factor-clock”-v�ã.omap_96m_fck@d40é ti,mux-clock”."ö� @ãIdpll4_m3_ck@e40éti,divider-clock” öT �@_ã/dpll4_m3x2_mul_ckéfixed-factor-clock”/v�ã0dpll4_m3x2_ck@d00éti,hsdiv-gate-clock”0ö� ‹ã1omap_54m_fck@d40é ti,mux-clock”12ö� @ã<cm_96m_d2_fckéfixed-factor-clock”.v�ã3omap_48m_fck@d40é ti,mux-clock”32ö� @ã4omap_12m_fckéfixed-factor-clock”4v�ãKdpll4_m4_ck@e40éti,divider-clock” T�@_ã5dpll4_m4x2_mul_ckéti,fixed-factor-clock”5¡¯¼ã6dpll4_m4x2_ck@d00éti,gate-clock”6ö� ‹¼ã�dpll4_m5_ck@f40éti,divider-clock” T?�@_ã7dpll4_m5x2_mul_ckéti,fixed-factor-clock”7¡¯¼ã8dpll4_m5x2_ck@d00éti,hsdiv-gate-clock”8ö� ‹¼ãndpll4_m6_ck@1140éti,divider-clock” öT?�@_ã9dpll4_m6x2_mul_ckéfixed-factor-clock”9v�ã:dpll4_m6x2_ck@d00éti,hsdiv-gate-clock”:ö� ‹ã;emu_per_alwon_ckéfixed-factor-clock”;v�ãgclkout2_src_gate_ck@d70é ti,composite-no-wait-gate-clock”*ö� pã=clkout2_src_mux_ck@d70éti,composite-mux-clock”*".<� pã>clkout2_src_ckéti,composite-clock”=>ã?sys_clkout2@d70éti,divider-clock”?öT@� pÏmpu_ckéfixed-factor-clock”@v�ãAarm_fck@924éti,divider-clock”A� $Temu_mpu_alwon_ckéfixed-factor-clock”Av�ãhl3_ick@a40éti,divider-clock”*T� @_ãBl4_ick@a40éti,divider-clock”BöT� @_ãCrm_ick@c40éti,divider-clock”CöT� @_gpt10_gate_fck@a00éti,composite-gate-clock”"ö � ãEgpt10_mux_fck@a40éti,composite-mux-clock”D"ö� @ãFgpt10_fckéti,composite-clock”EFgpt11_gate_fck@a00éti,composite-gate-clock”"ö � ãGgpt11_mux_fck@a40éti,composite-mux-clock”D"ö� @ãHgpt11_fckéti,composite-clock”GHcore_96m_fckéfixed-factor-clock”Iv�ãmmchs2_fck@a00éti,wait-gate-clock”� öã¹mmchs1_fck@a00éti,wait-gate-clock”� öãºi2c3_fck@a00éti,wait-gate-clock”� öã»i2c2_fck@a00éti,wait-gate-clock”� öã¼i2c1_fck@a00éti,wait-gate-clock”� öã½mcbsp5_gate_fck@a00éti,composite-gate-clock”ö � ã mcbsp1_gate_fck@a00éti,composite-gate-clock”ö � ã core_48m_fckéfixed-factor-clock”4v�ãJmcspi4_fck@a00éti,wait-gate-clock”J� öã¾mcspi3_fck@a00éti,wait-gate-clock”J� öã¿mcspi2_fck@a00éti,wait-gate-clock”J� öãÀmcspi1_fck@a00éti,wait-gate-clock”J� öãÁuart2_fck@a00éti,wait-gate-clock”J� öãÂuart1_fck@a00éti,wait-gate-clock”J� ö ãÃcore_12m_fckéfixed-factor-clock”Kv�ãLhdq_fck@a00éti,wait-gate-clock”L� öãÄcore_l3_ickéfixed-factor-clock”Bv�ãMsdrc_ick@a10éti,wait-gate-clock”M� öãŽgpmc_fckéfixed-factor-clock”Mv�core_l4_ickéfixed-factor-clock”Cv�ãNmmchs2_ick@a10éti,omap3-interface-clock”N� öãÅmmchs1_ick@a10éti,omap3-interface-clock”N� öãÆhdq_ick@a10éti,omap3-interface-clock”N� öãÇmcspi4_ick@a10éti,omap3-interface-clock”N� öãÈmcspi3_ick@a10éti,omap3-interface-clock”N� öãÉmcspi2_ick@a10éti,omap3-interface-clock”N� öãÊmcspi1_ick@a10éti,omap3-interface-clock”N� öãËi2c3_ick@a10éti,omap3-interface-clock”N� öãÌi2c2_ick@a10éti,omap3-interface-clock”N� öãÍi2c1_ick@a10éti,omap3-interface-clock”N� öãÎuart2_ick@a10éti,omap3-interface-clock”N� öãÏuart1_ick@a10éti,omap3-interface-clock”N� ö ãÐgpt11_ick@a10éti,omap3-interface-clock”N� ö ãÑgpt10_ick@a10éti,omap3-interface-clock”N� ö ãÒmcbsp5_ick@a10éti,omap3-interface-clock”N� ö ãÓmcbsp1_ick@a10éti,omap3-interface-clock”N� ö ãÔomapctrl_ick@a10éti,omap3-interface-clock”N� öãÕdss_tv_fck@e00éti,gate-clock”<�öã´dss_96m_fck@e00éti,gate-clock”I�öãµdss2_alwon_fck@e00éti,gate-clock”"�öã¶dummy_cké fixed-clockDgpt1_gate_fck@c00éti,composite-gate-clock”"ö� ãOgpt1_mux_fck@c40éti,composite-mux-clock”D"� @ãPgpt1_fckéti,composite-clock”OPãaes2_ick@a10éti,omap3-interface-clock”Nö� ãwkup_32k_fckéfixed-factor-clock”Dv�ãQgpio1_dbck@c00éti,gate-clock”Q� öã«sha12_ick@a10éti,omap3-interface-clock”N� öãÖwdt2_fck@c00éti,wait-gate-clock”Q� öã¬wdt2_ick@c10éti,omap3-interface-clock”R� öã­wdt1_ick@c10éti,omap3-interface-clock”R� öã®gpio1_ick@c10éti,omap3-interface-clock”R� öã¯omap_32ksync_ick@c10éti,omap3-interface-clock”R� öã°gpt12_ick@c10éti,omap3-interface-clock”R� öã±gpt1_ick@c10éti,omap3-interface-clock”R� öã²per_96m_fckéfixed-factor-clock”-v�ã per_48m_fckéfixed-factor-clock”4v�ãSuart3_fck@1000éti,wait-gate-clock”S�ö ã�gpt2_gate_fck@1000éti,composite-gate-clock”"ö�ãTgpt2_mux_fck@1040éti,composite-mux-clock”D"�@ãUgpt2_fckéti,composite-clock”TUãgpt3_gate_fck@1000éti,composite-gate-clock”"ö�ãVgpt3_mux_fck@1040éti,composite-mux-clock”D"ö�@ãWgpt3_fckéti,composite-clock”VWgpt4_gate_fck@1000éti,composite-gate-clock”"ö�ãXgpt4_mux_fck@1040éti,composite-mux-clock”D"ö�@ãYgpt4_fckéti,composite-clock”XYgpt5_gate_fck@1000éti,composite-gate-clock”"ö�ãZgpt5_mux_fck@1040éti,composite-mux-clock”D"ö�@ã[gpt5_fckéti,composite-clock”Z[gpt6_gate_fck@1000éti,composite-gate-clock”"ö�ã\gpt6_mux_fck@1040éti,composite-mux-clock”D"ö�@ã]gpt6_fckéti,composite-clock”\]gpt7_gate_fck@1000éti,composite-gate-clock”"ö�ã^gpt7_mux_fck@1040éti,composite-mux-clock”D"ö�@ã_gpt7_fckéti,composite-clock”^_gpt8_gate_fck@1000éti,composite-gate-clock”"ö �ã`gpt8_mux_fck@1040éti,composite-mux-clock”D"ö�@ãagpt8_fckéti,composite-clock”`agpt9_gate_fck@1000éti,composite-gate-clock”"ö �ãbgpt9_mux_fck@1040éti,composite-mux-clock”D"ö�@ãcgpt9_fckéti,composite-clock”bcper_32k_alwon_fckéfixed-factor-clock”Dv�ãdgpio6_dbck@1000éti,gate-clock”d�öã‘gpio5_dbck@1000éti,gate-clock”d�öã’gpio4_dbck@1000éti,gate-clock”d�öã“gpio3_dbck@1000éti,gate-clock”d�öã”gpio2_dbck@1000éti,gate-clock”d�ö ã•wdt3_fck@1000éti,wait-gate-clock”d�ö ã–per_l4_ickéfixed-factor-clock”Cv�ãegpio6_ick@1010éti,omap3-interface-clock”e�öã—gpio5_ick@1010éti,omap3-interface-clock”e�öã˜gpio4_ick@1010éti,omap3-interface-clock”e�öã™gpio3_ick@1010éti,omap3-interface-clock”e�öãšgpio2_ick@1010éti,omap3-interface-clock”e�ö ã›wdt3_ick@1010éti,omap3-interface-clock”e�ö ãœuart3_ick@1010éti,omap3-interface-clock”e�ö ã�uart4_ick@1010éti,omap3-interface-clock”e�öãžgpt9_ick@1010éti,omap3-interface-clock”e�ö ãŸgpt8_ick@1010éti,omap3-interface-clock”e�ö ã gpt7_ick@1010éti,omap3-interface-clock”e�öã¡gpt6_ick@1010éti,omap3-interface-clock”e�öã¢gpt5_ick@1010éti,omap3-interface-clock”e�öã£gpt4_ick@1010éti,omap3-interface-clock”e�öã¤gpt3_ick@1010éti,omap3-interface-clock”e�öã¥gpt2_ick@1010éti,omap3-interface-clock”e�öã¦mcbsp2_ick@1010éti,omap3-interface-clock”e�öã§mcbsp3_ick@1010éti,omap3-interface-clock”e�öã¨mcbsp4_ick@1010éti,omap3-interface-clock”e�öã©mcbsp2_gate_fck@1000éti,composite-gate-clock”ö�ãmcbsp3_gate_fck@1000éti,composite-gate-clock”ö�ãmcbsp4_gate_fck@1000éti,composite-gate-clock”ö�ãemu_src_mux_ck@1140é ti,mux-clock”"fgh�@ãiemu_src_ckéti,clkdm-gate-clock”iãjpclk_fck@1140éti,divider-clock”jöT�@_pclkx2_fck@1140éti,divider-clock”jöT�@_atclk_fck@1140éti,divider-clock”jöT�@_traceclk_src_fck@1140é ti,mux-clock”"fghö�@ãktraceclk_fck@1140éti,divider-clock”kö T�@_secure_32k_fcké fixed-clockD€ãlgpt12_fckéfixed-factor-clock”lv�ãwdt1_fckéfixed-factor-clock”lv�security_l4_ick2éfixed-factor-clock”Cv�ãmaes1_ick@a14éti,omap3-interface-clock”mö� ãrng_ick@a14éti,omap3-interface-clock”m� öãûsha11_ick@a14éti,omap3-interface-clock”m� ödes1_ick@a14éti,omap3-interface-clock”m� öcam_mclk@f00éti,gate-clock”nö�¼cam_ick@f10é!ti,omap3-no-wait-interface-clock”C�öãÝcsi2_96m_fck@f00éti,gate-clock”�öãÞsecurity_l3_ickéfixed-factor-clock”Bv�ãopka_ick@a14éti,omap3-interface-clock”o� öicr_ick@a10éti,omap3-interface-clock”N� ödes2_ick@a10éti,omap3-interface-clock”N� ömspro_ick@a10éti,omap3-interface-clock”N� ömailboxes_ick@a10éti,omap3-interface-clock”N� össi_l4_ickéfixed-factor-clock”Cv�ãvsr1_fck@c00éti,wait-gate-clock”"� öã sr2_fck@c00éti,wait-gate-clock”"� öã sr_l4_ickéfixed-factor-clock”Cv�dpll2_fck@40éti,divider-clock”*öT�@_ãpdpll2_ck@4éti,omap3-dpll-clock”"p�$@4å÷ÿãqdpll2_m2_ck@44éti,divider-clock”qT�D_ãriva2_ck@0éti,wait-gate-clock”r�öãßmodem_fck@a00éti,omap3-interface-clock”"� öãàsad2d_ick@a10éti,omap3-interface-clock”B� öãámad2d_ick@a18éti,omap3-interface-clock”B� öãâmspro_fck@a00éti,wait-gate-clock”� össi_ssr_gate_fck_3430es2@a00é ti,composite-no-wait-gate-clock”#ö� ãsssi_ssr_div_fck_3430es2@a40éti,composite-divider-clock”#ö� @$ãtssi_ssr_fck_3430es2éti,composite-clock”stãussi_sst_fck_3430es2éfixed-factor-clock”uv�ãhsotgusb_ick_3430es2@a10é"ti,omap3-hsotgusb-interface-clock”M� öã�ssi_ick_3430es2@a10éti,omap3-ssi-interface-clock”v� öã usim_gate_fck@c00éti,composite-gate-clock”Iö � ã�sys_d2_ckéfixed-factor-clock”"v�ãxomap_96m_d2_fckéfixed-factor-clock”Iv�ãyomap_96m_d4_fckéfixed-factor-clock”Iv�ãzomap_96m_d8_fckéfixed-factor-clock”Iv�ã{omap_96m_d10_fckéfixed-factor-clock”Iv� ã|dpll5_m2_d4_ckéfixed-factor-clock”wv�ã}dpll5_m2_d8_ckéfixed-factor-clock”wv�ã~dpll5_m2_d16_ckéfixed-factor-clock”wv�ãdpll5_m2_d20_ckéfixed-factor-clock”wv�ã€usim_mux_fck@c40éti,composite-mux-clock(”"xyz{|}~€ö� @_ã‚usim_fckéti,composite-clock”�‚usim_ick@c10éti,omap3-interface-clock”R� ö ã³dpll5_ck@d04éti,omap3-dpll-clock”""�  $ L 4å÷ãƒdpll5_m2_ck@d50éti,divider-clock”ƒT� P_ãwsgx_gate_fck@b00éti,composite-gate-clock”*ö� ã‹core_d3_ckéfixed-factor-clock”*v�ã„core_d4_ckéfixed-factor-clock”*v�ã…core_d6_ckéfixed-factor-clock”*v�ã†omap_192m_alwon_fckéfixed-factor-clock”&v�ã‡core_d2_ckéfixed-factor-clock”*v�ãˆsgx_mux_fck@b40éti,composite-mux-clock ”„…†.‡ˆ‰Š� @ãŒsgx_fckéti,composite-clock”‹Œãsgx_ick@b10éti,wait-gate-clock”B� öããcpefuse_fck@a08éti,gate-clock”"� öã×ts_fck@a08éti,gate-clock”D� öãØusbtll_fck@a08éti,wait-gate-clock”w� öãÙusbtll_ick@a18éti,omap3-interface-clock”N� öãÚmmchs3_ick@a10éti,omap3-interface-clock”N� öãÛmmchs3_fck@a00éti,wait-gate-clock”� öãÜdss1_alwon_fck_3430es2@e00éti,dss-gate-clock”�ö�¼ã·dss_ick_3430es2@e10éti,omap3-dss-interface-clock”C�öã¸usbhost_120m_fck@1400éti,gate-clock”w�öãäusbhost_48m_fck@1400éti,dss-gate-clock”4�öãåusbhost_ick@1410éti,omap3-dss-interface-clock”C�öãæuart4_fck@1000éti,wait-gate-clock”S�öãªclockdomainscore_l3_clkdmti,clockdomain”Ž�dpll3_clkdmti,clockdomain”dpll1_clkdmti,clockdomain”per_clkdmti,clockdomainl”�‘’“”•–—˜™š›œ�žŸ ¡¢£¤¥¦§¨©ªemu_clkdmti,clockdomain”jdpll4_clkdmti,clockdomain” wkup_clkdmti,clockdomain$”«¬­®¯°±²³dss_clkdmti,clockdomain”´µ¶·¸core_l4_clkdmti,clockdomain””¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖרÙÚÛÜcam_clkdmti,clockdomain”ÝÞiva2_clkdmti,clockdomain”ßdpll2_clkdmti,clockdomain”qd2d_clkdmti,clockdomain ”àáâdpll5_clkdmti,clockdomain”ƒsgx_clkdmti,clockdomain”ãusbhost_clkdmti,clockdomain ”äåætarget-module@48320000ti,sysc-omap2ti,sysc�H2H2 revsysc”Q°›fckick+ H2counter@0ti,omap-counter32k� interrupt-controller@48200000ti,omap3-intc'�H ãtarget-module@48056000ti,sysc-omap2ti,sysc�H`H`,H`(revsyscsyss #  (”M›ick+ H`dma-controller@0ti,omap3630-sdmati,omap-sdma�ë -8 E`ãgpio@48310000ti,omap3-gpio�H1ëögpio1Rdt'ãgpio@49050000ti,omap3-gpio�Iëögpio2dt'ãgpio@49052000ti,omap3-gpio�I ëögpio3dt'gpio@49054000ti,omap3-gpio�I@ë ögpio4dt'gpio@49056000ti,omap3-gpio�I`ë!ögpio5dt'gpio@49058000ti,omap3-gpio�I€ë"ögpio6dt'ãserial@4806a000ti,omap3-uart�H  €H512:txrxöuart1DÜlserial@4806c000ti,omap3-uart�HÀ€I534:txrxöuart2DÜlwdefault…çserial@49020000ti,omap3-uart�I€Jèn556:txrxöuart3DÜlwdefault…éi2c@48070000 ti,omap3-i2c�H€ë85:txrx+öi2c1wdefault…êD'¬@twl@48�Hë  ti,twl4030'wdefault…ëìaudioti,twl4030-audiocodecrtcti,twl4030-rtcë bciti,twl4030-bcië ”í¢î ®vacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1¹ 'ÀÑ regulator-vdacti,twl4030-vdac¹w@Ñw@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1¹:�Ñ0°ãöregulator-vmmc2ti,twl4030-vmmc2¹:�Ñ0°regulator-vusb1v5ti,twl4030-vusb1v5ãïregulator-vusb1v8ti,twl4030-vusb1v8ãðregulator-vusb3v1ti,twl4030-vusb3v1ãíregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2¹w@Ñw@¿regulator-vsimti,twl4030-vsim¹w@Ñ-ÆÀgpioti,twl4030-gpiodt'Ótwl4030-usbti,twl4030-usbë ßïíðûí ãpwmti,twl4030-pwmpwmledti,twl4030-pwmledãpwrbuttonti,twl4030-pwrbuttonëkeypadti,twl4030-keypadë(8madcti,twl4030-madcëKãîi2c@48072000 ti,omap3-i2c�H €ë95:txrx+öi2c2 ]disabledi2c@48060000 ti,omap3-i2c�H€ë=5:txrx+öi2c3wdefault…ñD† ãeeprom@51 atmel,24c01�Qdlis33de@1dst,lis33dest,lis3lv02d�mòx󆘪¼ Î à ò,;JYhxwx†Œ•&¤&³î ]disabledmailbox@48094000ti,omap3-mailboxömailbox�H @ëÂÎàdsp ò ýspi@48098000ti,omap2-mcspi�H €ëA+ömcspi1@5#$%&'()* :tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspi�H  ëB+ömcspi2 5+,-.:tx0rx0tx1rx1spi@480b8000ti,omap2-mcspi�H €ë[+ömcspi3 5:tx0rx0tx1rx1spi@480ba000ti,omap2-mcspi�H  ë0+ömcspi45FG:tx0rx01w@480b2000 ti,omap3-1w�H ë:öhdq1wmmc@4809c000ti,omap3-hsmmc�H ÀëSömmc15=>:txrx#ôwdefault…õ0ö<mmc@480b4000ti,omap3-hsmmc�H @ëVömmc25/0:txrxwdefault…÷0øFù<S`mmc@480ad000ti,omap3-hsmmc�H Ðë^ömmc35MN:txrx ]disabledmmu@480bd400nti,omap2-iommu�H Ô€ëömmu_isp{ã mmu@5d000000nti,omap2-iommu�]€ëömmu_iva ]disabledwdt@48314000 ti,omap3-wdt�H1@€ öwd_timer2mcbsp@48074000ti,omap3-mcbsp�H@ÿmpu ë;< ‹commontxrx›€ömcbsp15 :txrx”ú›fck ]disabledtarget-module@480a0000ti,sysc-omap2ti,sysc�H <H @H Drevsyscsyss (”û›ick+ H rng@0 ti,omap2-rng� ë4mcbsp@49022000ti,omap3-mcbsp�I ÿI€ÿ mpusidetoneë>?‹commontxrxsidetone›ömcbsp2mcbsp2_sidetone5!":txrx”ü§›fckick]okayãmcbsp@49024000ti,omap3-mcbsp�I@ÿI ÿ mpusidetoneëYZ‹commontxrxsidetone›€ömcbsp3mcbsp3_sidetone5:txrx”ý¨›fckick ]disabledmcbsp@49026000ti,omap3-mcbsp�I`ÿmpu ë67 ‹commontxrx›€ömcbsp45:txrx”þ›fckª ]disabledmcbsp@48096000ti,omap3-mcbsp�H `ÿmpu ëQR ‹commontxrx›€ömcbsp55:txrx”ÿ›fck ]disabledsham@480c3000ti,omap3-shamösham�H 0dë15E:rxtarget-module@48318000ti,sysc-omap2-timerti,sysc�H1€H1€H1€revsyscsyss ' (”²›fckick+ H1€»Ïtimer@0ti,omap3430-timer�€”›fckë%ÚéùDtarget-module@49032000ti,sysc-omap2-timerti,sysc�I I I revsyscsyss ' (”¦›fckick+ I timer@0ti,omap3430-timer�ë&timer@49034000ti,omap3430-timer�I@ë'ötimer3timer@49036000ti,omap3430-timer�I`ë(ötimer4timer@49038000ti,omap3430-timer�I€ë)ötimer5timer@4903a000ti,omap3430-timer�I ë*ötimer6timer@4903c000ti,omap3430-timer�IÀë+ötimer7timer@4903e000ti,omap3430-timer�Iàë,ötimer8timer@49040000ti,omap3430-timer�Ië-ötimer9timer@48086000ti,omap3430-timer�H`ë.ötimer10timer@48088000ti,omap3430-timer�H€ë/ötimer11target-module@48304000ti,sysc-omap2-timerti,sysc�H0@H0@H0@revsyscsyss ' (”±›fckick+ H0@timer@0ti,omap3430-timer�ë_Ú*usbhstll@48062000 ti,usbhs-tll�H ëN öusb_tll_hsusbhshost@48064000ti,usbhs-host�H@ öusb_host_hs+ :ehci-phyohci@48064400ti,ohci-omap3�HDëLEehci@48064800 ti,ehci-omap�HHëM]gpmc@6e000000ti,omap3430-gpmcögpmc�nÐë5:rxtxbn+'dt00+,ãnand@0,0ti,omap2-nand€micron,mt29c4g96maz � ë�ž°bch8ÀÑß,ñ,"%,8(G6V@eRvR‡(™+partition@0±SPL�partition@80000±U-Boot�partition@1c0000 ±Environment�$partition@280000±Kernel�(€partition@780000 ±Filesystem�¨usb_otg_hs@480ab000ti,omap3-musb�H °ë\]‹mcdma öusb_otg_hs·ÂÊ Óâ] êusb2-phy ô2dss@48050000 ti,omap3-dss�H]okay ödss_core”·›fck+wdefault…dispc@48050400ti,omap3-dispc�Hë ödss_dispc”·›fckencoder@4804fc00 ti,omap3-dsi�HüHþ@Hÿ protophypllë ]disabled ödss_dsi1”·¶ ›fcksys_clk+encoder@48050800ti,omap3-rfbi�H ]disabled ödss_rfbi”·¸›fckickencoder@48050c00ti,omap3-venc�H  ]disabled ödss_venc”´µ›fcktv_dac_clkportendpointú ãssi-controller@48058000 ti,omap3-ssiössi]okay�H€H�sysgddëG‹gdd_mpu+ ”u  ›ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-port�H H¨txrxëCDssi-port@4805b000ti,omap3-ssi-port�H°H¸txrxëEFserial@49042000ti,omap3-uart�I ëP5QR:txrxöuart4DÜlregulator-abb-mpu ti,abb-v1 ªabb_mpu_iva+�H0rðH0hbase-addressint-address ”" . ?` OsO€7Èûãpinmux@480025a0 ti,omap3-padconfpinctrl-single�H% \+'<Zÿwdefault… pinmux_hsusb2_2_pins0�PRT V X Z ã pinmux_w3cbw003c_2_pins�@ãpinmux_led_pins�Jãisp@480bc000 ti,omap3-isp�H ÀüH Øë [ £ð béports+bandgap@48002524�H%$ti,omap36xx-bandgap nãtarget-module@480cb000ti,sysc-omap3630-srti,syscösmartreflex_core�H °8sysc  ” ›fck+ H °smartreflex@0ti,omap3-smartreflex-core�ëtarget-module@480c9000ti,sysc-omap3630-srti,syscösmartreflex_mpu_iva�H �8sysc  ” ›fck+ H �smartreflex@480c9000ti,omap3-smartreflex-mpu-iva�ëtarget-module@50000000ti,sysc-omap4ti,sysc�PþPþ revsysc  ”ã›fckick+ Popp-tableoperating-points-v2-ti-cpu£ãopp50-300000000 „ᣠ‹ssssss ™ÿÿÿÿ ªopp100-600000000 „#ÃF ‹O€O€O€O€O€O€ ™ÿÿÿÿopp130-800000000 „/¯ ‹7È7È7È7È7È7È ™ÿÿÿÿopp1g-1000000000 „;šÊ ‹ûûûûûû ™ÿÿÿÿ ¶opp_supplyti,omap-opp-supply Áûthermal-zonescpu_thermal Üú òè N  tripscpu_alert 8€ )Ћpassiveãcpu_crit _� )Ð ‹criticalcooling-mapsmap0 4 9ÿÿÿÿÿÿÿÿmemory@0„memory�pwmleds pwm-ledsovero±overo:blue:COM Hw5” M \mmc0soundti,omap-twl4030 rovero {hsusb2_power_regregulator-fixed ªhsusb2_vbus¹LK@ÑLK@ „ ‰p šãhsusb2_phyusb-nop-xceiv ­ ¹ãregulator-w3cbw003c-npoweronregulator-fixedªregulator-w3cbw003c-npoweron¹2Z Ñ2Z  „ šãøregulator-w3cbw003c-wifi-nresetwdefault…regulator-fixed ªregulator-w3cbw003c-wifi-nreset¹2Z Ñ2Z  „ ‰'ãùlis33-3v3-regregulator-fixedªlis33-3v3-reg¹2Z Ñ2Z ãólis33-1v8-regregulator-fixedªlis33-1v8-reg¹w@Ñw@ãòencoder ti,tfp410ports+port@0�endpointúãport@1�endpointúãconnectordvi-connector±dvi Ä Ìportendpointúãleds gpio-ledswdefault…heartbeat±overo:red:gpio21 ³ \heartbeat compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2serial3display0device_typeregclocksclock-namesclock-latencyoperating-points-v2vbb-supply#cooling-cellsphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsstatuspagesizeVdd-supplyVdd_IO-supplyst,click-single-xst,click-single-yst,click-single-zst,click-thresh-xst,click-thresh-yst,click-thresh-zst,irq1-clickst,irq2-clickst,wakeup-x-lost,wakeup-x-hist,wakeup-y-lost,wakeup-y-hist,wakeup-z-lost,wakeup-z-hist,min-limit-xst,min-limit-yst,min-limit-zst,max-limit-xst,max-limit-yst,max-limit-z#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplybus-widthvqmmc-supplycap-sdio-irqnon-removable#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modeti,absolute-max-voltage-uvpolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicepwmsmax-brightnesslinux,default-triggerti,modelti,mcbspgpiostartup-delay-usenable-active-highreset-gpiosvcc-supplydigitalddc-i2c-bus