Ð þíÿÅ8õl( Yõ4"ti,omap3-ldpti,omap3430ti,omap3 +!7TI OMAP3430 LDP (Zoom1 Labrador)chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000 s/displaycpus+cpu@0arm,cortex-a8|cpuˆŒ“cpuŸ“à­ÁÐÜ pmu@54000000arm,cortex-a8-pmuˆT€äïdebugsssocti,omap-inframpu ti,omap3-mpuïmpuiva ti,iva2.2ïivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busˆhä +ùïl3_mainl4@48000000ti,omap3-l4-coresimple-bus+ ùHscm@2000ti,omap3-scmsimple-busˆ + ù pinmux@30 ti,omap3-padconfpinctrl-singleˆ08+ 5SÿÜåpinmux_twl4030_pinsp°AÜæpinmux_gpio_key_pinsHpêìîðòôöøúÜ pinmux_musb_pins`prz|~€‚„†ˆvxtÜþpinmux_mmc1_pins0pÜðscm_conf@270sysconsimple-busˆp0+ ùp0Üpbias_regulator@2b0ti,pbias-omap3ti,pbias-omapˆ°„pbias_mmc_omap2430‹pbias_mmc_omap2430šw@²-ÆÀÜîclocks+mcbsp5_mux_fck@68Êti,composite-mux-clockŒ×ˆhÜ mcbsp5_fckÊti,composite-clockŒ Üömcbsp1_mux_fck@4Êti,composite-mux-clockŒ×ˆÜ mcbsp1_fckÊti,composite-clockŒ Üñmcbsp2_mux_fck@4Êti,composite-mux-clockŒ ׈Ümcbsp2_fckÊti,composite-clockŒ Üómcbsp3_mux_fck@68Êti,composite-mux-clockŒ ˆhÜmcbsp3_fckÊti,composite-clockŒÜômcbsp4_mux_fck@68Êti,composite-mux-clockŒ ׈hÜmcbsp4_fckÊti,composite-clockŒÜõclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singleˆ \+ 5Sÿpinmux_twl4030_vpins pÜçtarget-module@480a6000ti,sysc-omap2ti,syscˆH `DH `HH `Lärevsyscsyssî û Œ“ick+ ùH ` aes1@0 ti,omap3-aesˆPä  txrxtarget-module@480c5000ti,sysc-omap2ti,syscˆH PDH PHH PLärevsyscsyssî û Œ“ick+ ùH P aes2@0 ti,omap3-aesˆPäABtxrxprm@48306000 ti,omap3-prmˆH0`@ä clocks+virt_16_8m_ckÊ fixed-clock%YÜosc_sys_ck@d40Ê ti,mux-clockŒˆ @Üsys_ck@1270Êti,divider-clockŒ×5ˆp@Ü!sys_clkout1@d70Êti,gate-clockŒˆ p×dpll3_x2_ckÊfixed-factor-clockŒWbdpll3_m2x2_ckÊfixed-factor-clockŒWbÜ dpll4_x2_ckÊfixed-factor-clockŒWbcorex2_fckÊfixed-factor-clockŒ WbÜ"wkup_l4_ickÊfixed-factor-clockŒ!WbÜQcorex2_d3_fckÊfixed-factor-clockŒ"Wb܈corex2_d5_fckÊfixed-factor-clockŒ"Wb܉clockdomainscm@48004000 ti,omap3-cmˆH@@clocks+dummy_apb_pclkÊ fixed-clock%omap_32k_fckÊ fixed-clock%€ÜCvirt_12m_ckÊ fixed-clock%·Üvirt_13m_ckÊ fixed-clock%Æ]@Üvirt_19200000_ckÊ fixed-clock%$øÜvirt_26000000_ckÊ fixed-clock%Œº€Üvirt_38_4m_ckÊ fixed-clock%IðÜdpll4_ck@d00Êti,omap3-dpll-per-clockŒ!!ˆ D 0Üdpll4_m2_ck@d48Êti,divider-clockŒ5?ˆ H@Ü#dpll4_m2x2_mul_ckÊfixed-factor-clockŒ#WbÜ$dpll4_m2x2_ck@d00Êti,gate-clockŒ$׈ lÜ%omap_96m_alwon_fckÊfixed-factor-clockŒ%WbÜ,dpll3_ck@d00Êti,omap3-dpll-core-clockŒ!!ˆ @ 0Üdpll3_m3_ck@1140Êti,divider-clockŒ×5ˆ@@Ü&dpll3_m3x2_mul_ckÊfixed-factor-clockŒ&WbÜ'dpll3_m3x2_ck@d00Êti,gate-clockŒ'× ˆ lÜ(emu_core_alwon_ckÊfixed-factor-clockŒ(WbÜesys_altclkÊ fixed-clock%Ü1mcbsp_clksÊ fixed-clock%Üdpll3_m2_ck@d40Êti,divider-clockŒ×5ˆ @@Ücore_ckÊfixed-factor-clockŒWbÜ)dpll1_fck@940Êti,divider-clockŒ)×5ˆ @@Ü*dpll1_ck@904Êti,omap3-dpll-clockŒ!*ˆ  $ @ 4Üdpll1_x2_ckÊfixed-factor-clockŒWbÜ+dpll1_x2m2_ck@944Êti,divider-clockŒ+5ˆ D@Ü?cm_96m_fckÊfixed-factor-clockŒ,WbÜ-omap_96m_fck@d40Ê ti,mux-clockŒ-!׈ @ÜHdpll4_m3_ck@e40Êti,divider-clockŒ×5 ˆ@@Ü.dpll4_m3x2_mul_ckÊfixed-factor-clockŒ.WbÜ/dpll4_m3x2_ck@d00Êti,gate-clockŒ/׈ lÜ0omap_54m_fck@d40Ê ti,mux-clockŒ01׈ @Ü;cm_96m_d2_fckÊfixed-factor-clockŒ-WbÜ2omap_48m_fck@d40Ê ti,mux-clockŒ21׈ @Ü3omap_12m_fckÊfixed-factor-clockŒ3WbÜJdpll4_m4_ck@e40Êti,divider-clockŒ5ˆ@@Ü4dpll4_m4x2_mul_ckÊti,fixed-factor-clockŒ4‚��Ü5dpll4_m4x2_ck@d00Êti,gate-clockŒ5׈ l�ÜŒdpll4_m5_ck@f40Êti,divider-clockŒ5?ˆ@@Ü6dpll4_m5x2_mul_ckÊti,fixed-factor-clockŒ6‚��Ü7dpll4_m5x2_ck@d00Êti,gate-clockŒ7׈ l�Ümdpll4_m6_ck@1140Êti,divider-clockŒ×5?ˆ@@Ü8dpll4_m6x2_mul_ckÊfixed-factor-clockŒ8WbÜ9dpll4_m6x2_ck@d00Êti,gate-clockŒ9׈ lÜ:emu_per_alwon_ckÊfixed-factor-clockŒ:WbÜfclkout2_src_gate_ck@d70Ê ti,composite-no-wait-gate-clockŒ)׈ pÜ<clkout2_src_mux_ck@d70Êti,composite-mux-clockŒ)!-;ˆ pÜ=clkout2_src_ckÊti,composite-clockŒ<=Ü>sys_clkout2@d70Êti,divider-clockŒ>×5@ˆ p°mpu_ckÊfixed-factor-clockŒ?WbÜ@arm_fck@924Êti,divider-clockŒ@ˆ $5emu_mpu_alwon_ckÊfixed-factor-clockŒ@WbÜgl3_ick@a40Êti,divider-clockŒ)5ˆ @@ÜAl4_ick@a40Êti,divider-clockŒA×5ˆ @@ÜBrm_ick@c40Êti,divider-clockŒB×5ˆ @@gpt10_gate_fck@a00Êti,composite-gate-clockŒ!× ˆ ÜDgpt10_mux_fck@a40Êti,composite-mux-clockŒC!׈ @ÜEgpt10_fckÊti,composite-clockŒDEgpt11_gate_fck@a00Êti,composite-gate-clockŒ!× ˆ ÜFgpt11_mux_fck@a40Êti,composite-mux-clockŒC!׈ @ÜGgpt11_fckÊti,composite-clockŒFGcore_96m_fckÊfixed-factor-clockŒHWbÜmmchs2_fck@a00Êti,wait-gate-clockŒˆ ×Ü·mmchs1_fck@a00Êti,wait-gate-clockŒˆ ×ܸi2c3_fck@a00Êti,wait-gate-clockŒˆ ×ܹi2c2_fck@a00Êti,wait-gate-clockŒˆ ×ܺi2c1_fck@a00Êti,wait-gate-clockŒˆ ×Ü»mcbsp5_gate_fck@a00Êti,composite-gate-clockŒ× ˆ Ümcbsp1_gate_fck@a00Êti,composite-gate-clockŒ× ˆ Ü core_48m_fckÊfixed-factor-clockŒ3WbÜImcspi4_fck@a00Êti,wait-gate-clockŒIˆ ×ܼmcspi3_fck@a00Êti,wait-gate-clockŒIˆ ×ܽmcspi2_fck@a00Êti,wait-gate-clockŒIˆ ×ܾmcspi1_fck@a00Êti,wait-gate-clockŒIˆ ×Ü¿uart2_fck@a00Êti,wait-gate-clockŒIˆ ×ÜÀuart1_fck@a00Êti,wait-gate-clockŒIˆ × ÜÁcore_12m_fckÊfixed-factor-clockŒJWbÜKhdq_fck@a00Êti,wait-gate-clockŒKˆ ×ÜÂcore_l3_ickÊfixed-factor-clockŒAWbÜLsdrc_ick@a10Êti,wait-gate-clockŒLˆ ×Ü�gpmc_fckÊfixed-factor-clockŒLWbcore_l4_ickÊfixed-factor-clockŒBWbÜMmmchs2_ick@a10Êti,omap3-interface-clockŒMˆ ×ÜÃmmchs1_ick@a10Êti,omap3-interface-clockŒMˆ ×ÜÄhdq_ick@a10Êti,omap3-interface-clockŒMˆ ×ÜÅmcspi4_ick@a10Êti,omap3-interface-clockŒMˆ ×ÜÆmcspi3_ick@a10Êti,omap3-interface-clockŒMˆ ×ÜÇmcspi2_ick@a10Êti,omap3-interface-clockŒMˆ ×ÜÈmcspi1_ick@a10Êti,omap3-interface-clockŒMˆ ×ÜÉi2c3_ick@a10Êti,omap3-interface-clockŒMˆ ×ÜÊi2c2_ick@a10Êti,omap3-interface-clockŒMˆ ×ÜËi2c1_ick@a10Êti,omap3-interface-clockŒMˆ ×ÜÌuart2_ick@a10Êti,omap3-interface-clockŒMˆ ×ÜÍuart1_ick@a10Êti,omap3-interface-clockŒMˆ × ÜÎgpt11_ick@a10Êti,omap3-interface-clockŒMˆ × ÜÏgpt10_ick@a10Êti,omap3-interface-clockŒMˆ × ÜÐmcbsp5_ick@a10Êti,omap3-interface-clockŒMˆ × ÜÑmcbsp1_ick@a10Êti,omap3-interface-clockŒMˆ × ÜÒomapctrl_ick@a10Êti,omap3-interface-clockŒMˆ ×ÜÓdss_tv_fck@e00Êti,gate-clockŒ;ˆ×ܲdss_96m_fck@e00Êti,gate-clockŒHˆ×ܳdss2_alwon_fck@e00Êti,gate-clockŒ!ˆ×Ü´dummy_ckÊ fixed-clock%gpt1_gate_fck@c00Êti,composite-gate-clockŒ!׈ ÜNgpt1_mux_fck@c40Êti,composite-mux-clockŒC!ˆ @ÜOgpt1_fckÊti,composite-clockŒNOÜ÷aes2_ick@a10Êti,omap3-interface-clockŒM׈ Üwkup_32k_fckÊfixed-factor-clockŒCWbÜPgpio1_dbck@c00Êti,gate-clockŒPˆ ×Ü©sha12_ick@a10Êti,omap3-interface-clockŒMˆ ×ÜÔwdt2_fck@c00Êti,wait-gate-clockŒPˆ ×ܪwdt2_ick@c10Êti,omap3-interface-clockŒQˆ ×Ü«wdt1_ick@c10Êti,omap3-interface-clockŒQˆ ×ܬgpio1_ick@c10Êti,omap3-interface-clockŒQˆ ×Ü­omap_32ksync_ick@c10Êti,omap3-interface-clockŒQˆ ×Ü®gpt12_ick@c10Êti,omap3-interface-clockŒQˆ ×ܯgpt1_ick@c10Êti,omap3-interface-clockŒQˆ ×ܰper_96m_fckÊfixed-factor-clockŒ,WbÜ per_48m_fckÊfixed-factor-clockŒ3WbÜRuart3_fck@1000Êti,wait-gate-clockŒRˆ× Ü�gpt2_gate_fck@1000Êti,composite-gate-clockŒ!׈ÜSgpt2_mux_fck@1040Êti,composite-mux-clockŒC!ˆ@ÜTgpt2_fckÊti,composite-clockŒSTÜøgpt3_gate_fck@1000Êti,composite-gate-clockŒ!׈ÜUgpt3_mux_fck@1040Êti,composite-mux-clockŒC!׈@ÜVgpt3_fckÊti,composite-clockŒUVgpt4_gate_fck@1000Êti,composite-gate-clockŒ!׈ÜWgpt4_mux_fck@1040Êti,composite-mux-clockŒC!׈@ÜXgpt4_fckÊti,composite-clockŒWXgpt5_gate_fck@1000Êti,composite-gate-clockŒ!׈ÜYgpt5_mux_fck@1040Êti,composite-mux-clockŒC!׈@ÜZgpt5_fckÊti,composite-clockŒYZgpt6_gate_fck@1000Êti,composite-gate-clockŒ!׈Ü[gpt6_mux_fck@1040Êti,composite-mux-clockŒC!׈@Ü\gpt6_fckÊti,composite-clockŒ[\gpt7_gate_fck@1000Êti,composite-gate-clockŒ!׈Ü]gpt7_mux_fck@1040Êti,composite-mux-clockŒC!׈@Ü^gpt7_fckÊti,composite-clockŒ]^gpt8_gate_fck@1000Êti,composite-gate-clockŒ!× ˆÜ_gpt8_mux_fck@1040Êti,composite-mux-clockŒC!׈@Ü`gpt8_fckÊti,composite-clockŒ_`gpt9_gate_fck@1000Êti,composite-gate-clockŒ!× ˆÜagpt9_mux_fck@1040Êti,composite-mux-clockŒC!׈@Übgpt9_fckÊti,composite-clockŒabper_32k_alwon_fckÊfixed-factor-clockŒCWbÜcgpio6_dbck@1000Êti,gate-clockŒcˆ×Ü�gpio5_dbck@1000Êti,gate-clockŒcˆ×Ü‘gpio4_dbck@1000Êti,gate-clockŒcˆ×Ü’gpio3_dbck@1000Êti,gate-clockŒcˆ×Ü“gpio2_dbck@1000Êti,gate-clockŒcˆ× Ü”wdt3_fck@1000Êti,wait-gate-clockŒcˆ× Ü•per_l4_ickÊfixed-factor-clockŒBWbÜdgpio6_ick@1010Êti,omap3-interface-clockŒdˆ×Ü–gpio5_ick@1010Êti,omap3-interface-clockŒdˆ×Ü—gpio4_ick@1010Êti,omap3-interface-clockŒdˆ×ܘgpio3_ick@1010Êti,omap3-interface-clockŒdˆ×Ü™gpio2_ick@1010Êti,omap3-interface-clockŒdˆ× Üšwdt3_ick@1010Êti,omap3-interface-clockŒdˆ× Ü›uart3_ick@1010Êti,omap3-interface-clockŒdˆ× Üœuart4_ick@1010Êti,omap3-interface-clockŒdˆ×Ü�gpt9_ick@1010Êti,omap3-interface-clockŒdˆ× Üžgpt8_ick@1010Êti,omap3-interface-clockŒdˆ× ÜŸgpt7_ick@1010Êti,omap3-interface-clockŒdˆ×Ü gpt6_ick@1010Êti,omap3-interface-clockŒdˆ×Ü¡gpt5_ick@1010Êti,omap3-interface-clockŒdˆ×Ü¢gpt4_ick@1010Êti,omap3-interface-clockŒdˆ×Ü£gpt3_ick@1010Êti,omap3-interface-clockŒdˆ×ܤgpt2_ick@1010Êti,omap3-interface-clockŒdˆ×Ü¥mcbsp2_ick@1010Êti,omap3-interface-clockŒdˆ×ܦmcbsp3_ick@1010Êti,omap3-interface-clockŒdˆ×ܧmcbsp4_ick@1010Êti,omap3-interface-clockŒdˆ×ܨmcbsp2_gate_fck@1000Êti,composite-gate-clockŒ×ˆÜ mcbsp3_gate_fck@1000Êti,composite-gate-clockŒ×ˆÜmcbsp4_gate_fck@1000Êti,composite-gate-clockŒ×ˆÜemu_src_mux_ck@1140Ê ti,mux-clockŒ!efgˆ@Ühemu_src_ckÊti,clkdm-gate-clockŒhÜipclk_fck@1140Êti,divider-clockŒi×5ˆ@@pclkx2_fck@1140Êti,divider-clockŒi×5ˆ@@atclk_fck@1140Êti,divider-clockŒi×5ˆ@@traceclk_src_fck@1140Ê ti,mux-clockŒ!efg׈@Üjtraceclk_fck@1140Êti,divider-clockŒj× 5ˆ@@secure_32k_fckÊ fixed-clock%€Ükgpt12_fckÊfixed-factor-clockŒkWbÜùwdt1_fckÊfixed-factor-clockŒkWbsecurity_l4_ick2Êfixed-factor-clockŒBWbÜlaes1_ick@a14Êti,omap3-interface-clockŒl׈ Ürng_ick@a14Êti,omap3-interface-clockŒlˆ ×Üòsha11_ick@a14Êti,omap3-interface-clockŒlˆ ×des1_ick@a14Êti,omap3-interface-clockŒlˆ ×cam_mclk@f00Êti,gate-clockŒm׈�cam_ick@f10Ê!ti,omap3-no-wait-interface-clockŒBˆ×ÜÛcsi2_96m_fck@f00Êti,gate-clockŒˆ×ÜÜsecurity_l3_ickÊfixed-factor-clockŒAWbÜnpka_ick@a14Êti,omap3-interface-clockŒnˆ ×icr_ick@a10Êti,omap3-interface-clockŒMˆ ×des2_ick@a10Êti,omap3-interface-clockŒMˆ ×mspro_ick@a10Êti,omap3-interface-clockŒMˆ ×mailboxes_ick@a10Êti,omap3-interface-clockŒMˆ ×ssi_l4_ickÊfixed-factor-clockŒBWbÜusr1_fck@c00Êti,wait-gate-clockŒ!ˆ ×Üsr2_fck@c00Êti,wait-gate-clockŒ!ˆ ×Üsr_l4_ickÊfixed-factor-clockŒBWbdpll2_fck@40Êti,divider-clockŒ)×5ˆ@@Üodpll2_ck@4Êti,omap3-dpll-clockŒ!oˆ$@4ÆØàÜpdpll2_m2_ck@44Êti,divider-clockŒp5ˆD@Üqiva2_ck@0Êti,wait-gate-clockŒqˆ×ÜÝmodem_fck@a00Êti,omap3-interface-clockŒ!ˆ ×ÜÞsad2d_ick@a10Êti,omap3-interface-clockŒAˆ ×Üßmad2d_ick@a18Êti,omap3-interface-clockŒAˆ ×Üàmspro_fck@a00Êti,wait-gate-clockŒˆ ×ssi_ssr_gate_fck_3430es2@a00Ê ti,composite-no-wait-gate-clockŒ"׈ Ürssi_ssr_div_fck_3430es2@a40Êti,composite-divider-clockŒ"׈ @$ôÜsssi_ssr_fck_3430es2Êti,composite-clockŒrsÜtssi_sst_fck_3430es2Êfixed-factor-clockŒtWbÜhsotgusb_ick_3430es2@a10Ê"ti,omap3-hsotgusb-interface-clockŒLˆ ×ÜŽssi_ick_3430es2@a10Êti,omap3-ssi-interface-clockŒuˆ ×Üusim_gate_fck@c00Êti,composite-gate-clockŒH× ˆ Ü€sys_d2_ckÊfixed-factor-clockŒ!WbÜwomap_96m_d2_fckÊfixed-factor-clockŒHWbÜxomap_96m_d4_fckÊfixed-factor-clockŒHWbÜyomap_96m_d8_fckÊfixed-factor-clockŒHWbÜzomap_96m_d10_fckÊfixed-factor-clockŒHWb Ü{dpll5_m2_d4_ckÊfixed-factor-clockŒvWbÜ|dpll5_m2_d8_ckÊfixed-factor-clockŒvWbÜ}dpll5_m2_d16_ckÊfixed-factor-clockŒvWbÜ~dpll5_m2_d20_ckÊfixed-factor-clockŒvWbÜusim_mux_fck@c40Êti,composite-mux-clock(Œ!wxyz{|}~׈ @@Ü�usim_fckÊti,composite-clockŒ€�usim_ick@c10Êti,omap3-interface-clockŒQˆ × ܱdpll5_ck@d04Êti,omap3-dpll-clockŒ!!ˆ  $ L 4ÆØÜ‚dpll5_m2_ck@d50Êti,divider-clockŒ‚5ˆ P@Üvsgx_gate_fck@b00Êti,composite-gate-clockŒ)׈ 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-points-v2#cooling-cellscpu0-supplyphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0ti,use_poweroffbci3v1-supplyio-channelsio-channel-namesregulator-always-onusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xywakeup-sourcependown-gpioti,dual-voltpbias-supplyvmmc-supplybus-widthstatus#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addresslinux,mtd-namenand-bus-widthti,nand-ecc-optgpmc,sync-clk-pslabelmultipointnum-epsram-bitsinterface-typeusb-phypowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicegpioslinux,codedefault-onstartup-delay-uspower-supplyenvdd-supplyenable-gpiosreset-gpiosmode-gpios