Ð þíþ8÷ì( ÷´5isee,omap3-igep0030ti,omap3630ti,omap36xxti,omap3 +*7IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)chosen=/ocp@68000000/serial@49020000aliasesI/ocp@68000000/i2c@48070000N/ocp@68000000/i2c@48072000S/ocp@68000000/i2c@48060000X/ocp@68000000/mmc@4809c000]/ocp@68000000/mmc@480b4000b/ocp@68000000/mmc@480ad000g/ocp@68000000/serial@4806a000o/ocp@68000000/serial@4806c000w/ocp@68000000/serial@49020000/ocp@68000000/serial@49042000cpus+cpu@0arm,cortex-a8‡cpu“—žcpuª“à¸Ì׿pmu@54000000arm,cortex-a8-pmu“T€îùdebugsssocti,omap-inframpu ti,omap3-mpuùmpuiva ti,iva2.2ùivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus“hî +ùl3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus“ +  pinmux@30 ti,omap3-padconfpinctrl-single“08+ *?]ÿzdefaultˆpinmux_gpmc_pins’Žæpinmux_uart1_pins’RLæçpinmux_uart3_pins’npæépinmux_mcbsp2_pins ’ æþpinmux_mmc1_pins0’æópinmux_mmc2_pins0’(*,.02æ÷pinmux_i2c1_pins’ŠŒæêpinmux_i2c3_pins’’”æñpinmux_twl4030_pins’°Aæëpinmux_hsusb2_pins0’¤ ¦ ¨ ª ¬ ® æpinmux_uart2_pins ’<>@Bæèpinmux_lbee1usjyc_pins’68:æøscm_conf@270sysconsimple-bus“p0+ p0æpbias_regulator@2b0ti,pbias-omap3ti,pbias-omap“°¦pbias_mmc_omap2430­pbias_mmc_omap2430¼w@Ô-ÆÀæòclocks+mcbsp5_mux_fck@68ìti,composite-mux-clock—ù“hæ mcbsp5_fckìti,composite-clock— æmcbsp1_mux_fck@4ìti,composite-mux-clock—ù“æ mcbsp1_fckìti,composite-clock— æûmcbsp2_mux_fck@4ìti,composite-mux-clock— ù“æmcbsp2_fckìti,composite-clock—æýmcbsp3_mux_fck@68ìti,composite-mux-clock— “hæmcbsp3_fckìti,composite-clock—æÿmcbsp4_mux_fck@68ìti,composite-mux-clock— ù“hæmcbsp4_fckìti,composite-clock—æclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single“ \+ *?]ÿpinmux_twl4030_vpins ’æìtarget-module@480a6000ti,sysc-omap2ti,sysc“H `DH `HH `Lrevsyscsyss +—žick+ H ` aes1@0 ti,omap3-aes“Pî8  =txrxtarget-module@480c5000ti,sysc-omap2ti,sysc“H PDH PHH PLrevsyscsyss +—žick+ H P aes2@0 ti,omap3-aes“Pî8AB=txrxprm@48306000 ti,omap3-prm“H0`@î clocks+virt_16_8m_ckì fixed-clockGYæosc_sys_ck@d40ì ti,mux-clock—“ @æsys_ck@1270ìti,divider-clock—ùW“pbæ"sys_clkout1@d70ìti,gate-clock—“ pùdpll3_x2_ckìfixed-factor-clock—y„dpll3_m2x2_ckìfixed-factor-clock—y„æ!dpll4_x2_ckìfixed-factor-clock— y„corex2_fckìfixed-factor-clock—!y„æ#wkup_l4_ickìfixed-factor-clock—"y„æRcorex2_d3_fckìfixed-factor-clock—#y„æ‰corex2_d5_fckìfixed-factor-clock—#y„æŠclockdomainscm@48004000 ti,omap3-cm“H@@clocks+dummy_apb_pclkì fixed-clockGomap_32k_fckì fixed-clockG€æDvirt_12m_ckì fixed-clockG·ævirt_13m_ckì fixed-clockGÆ]@ævirt_19200000_ckì fixed-clockG$øævirt_26000000_ckì fixed-clockGŒº€ævirt_38_4m_ckì fixed-clockGIðædpll4_ck@d00ìti,omap3-dpll-per-j-type-clock—""“ D 0æ dpll4_m2_ck@d48ìti,divider-clock— W?“ Hbæ$dpll4_m2x2_mul_ckìfixed-factor-clock—$y„æ%dpll4_m2x2_ck@d00ìti,hsdiv-gate-clock—%ù“ Žæ&omap_96m_alwon_fckìfixed-factor-clock—&y„æ-dpll3_ck@d00ìti,omap3-dpll-core-clock—""“ @ 0ædpll3_m3_ck@1140ìti,divider-clock—ùW“@bæ'dpll3_m3x2_mul_ckìfixed-factor-clock—'y„æ(dpll3_m3x2_ck@d00ìti,hsdiv-gate-clock—(ù “ Žæ)emu_core_alwon_ckìfixed-factor-clock—)y„æfsys_altclkì fixed-clockGæ2mcbsp_clksì fixed-clockGædpll3_m2_ck@d40ìti,divider-clock—ùW“ @bæcore_ckìfixed-factor-clock—y„æ*dpll1_fck@940ìti,divider-clock—*ùW“ @bæ+dpll1_ck@904ìti,omap3-dpll-clock—"+“  $ @ 4ædpll1_x2_ckìfixed-factor-clock—y„æ,dpll1_x2m2_ck@944ìti,divider-clock—,W“ Dbæ@cm_96m_fckìfixed-factor-clock—-y„æ.omap_96m_fck@d40ì ti,mux-clock—."ù“ @æIdpll4_m3_ck@e40ìti,divider-clock— ùW “@bæ/dpll4_m3x2_mul_ckìfixed-factor-clock—/y„æ0dpll4_m3x2_ck@d00ìti,hsdiv-gate-clock—0ù“ Žæ1omap_54m_fck@d40ì ti,mux-clock—12ù“ @æ<cm_96m_d2_fckìfixed-factor-clock—.y„æ3omap_48m_fck@d40ì ti,mux-clock—32ù“ @æ4omap_12m_fckìfixed-factor-clock—4y„æKdpll4_m4_ck@e40ìti,divider-clock— W“@bæ5dpll4_m4x2_mul_ckìti,fixed-factor-clock—5¤²¿æ6dpll4_m4x2_ck@d00ìti,gate-clock—6ù“ Ž¿æ�dpll4_m5_ck@f40ìti,divider-clock— W?“@bæ7dpll4_m5x2_mul_ckìti,fixed-factor-clock—7¤²¿æ8dpll4_m5x2_ck@d00ìti,hsdiv-gate-clock—8ù“ Ž¿ændpll4_m6_ck@1140ìti,divider-clock— ùW?“@bæ9dpll4_m6x2_mul_ckìfixed-factor-clock—9y„æ:dpll4_m6x2_ck@d00ìti,hsdiv-gate-clock—:ù“ Žæ;emu_per_alwon_ckìfixed-factor-clock—;y„ægclkout2_src_gate_ck@d70ì ti,composite-no-wait-gate-clock—*ù“ pæ=clkout2_src_mux_ck@d70ìti,composite-mux-clock—*".<“ pæ>clkout2_src_ckìti,composite-clock—=>æ?sys_clkout2@d70ìti,divider-clock—?ùW@“ pÒmpu_ckìfixed-factor-clock—@y„æAarm_fck@924ìti,divider-clock—A“ $Wemu_mpu_alwon_ckìfixed-factor-clock—Ay„æhl3_ick@a40ìti,divider-clock—*W“ @bæBl4_ick@a40ìti,divider-clock—BùW“ @bæCrm_ick@c40ìti,divider-clock—CùW“ @bgpt10_gate_fck@a00ìti,composite-gate-clock—"ù “ æEgpt10_mux_fck@a40ìti,composite-mux-clock—D"ù“ @æFgpt10_fckìti,composite-clock—EFgpt11_gate_fck@a00ìti,composite-gate-clock—"ù “ æGgpt11_mux_fck@a40ìti,composite-mux-clock—D"ù“ @æHgpt11_fckìti,composite-clock—GHcore_96m_fckìfixed-factor-clock—Iy„æmmchs2_fck@a00ìti,wait-gate-clock—“ ùæ¹mmchs1_fck@a00ìti,wait-gate-clock—“ ùæºi2c3_fck@a00ìti,wait-gate-clock—“ ùæ»i2c2_fck@a00ìti,wait-gate-clock—“ ùæ¼i2c1_fck@a00ìti,wait-gate-clock—“ ùæ½mcbsp5_gate_fck@a00ìti,composite-gate-clock—ù “ æ mcbsp1_gate_fck@a00ìti,composite-gate-clock—ù “ æ core_48m_fckìfixed-factor-clock—4y„æJmcspi4_fck@a00ìti,wait-gate-clock—J“ ùæ¾mcspi3_fck@a00ìti,wait-gate-clock—J“ ùæ¿mcspi2_fck@a00ìti,wait-gate-clock—J“ ùæÀmcspi1_fck@a00ìti,wait-gate-clock—J“ ùæÁuart2_fck@a00ìti,wait-gate-clock—J“ ùæÂuart1_fck@a00ìti,wait-gate-clock—J“ ù æÃcore_12m_fckìfixed-factor-clock—Ky„æLhdq_fck@a00ìti,wait-gate-clock—L“ ùæÄcore_l3_ickìfixed-factor-clock—By„æMsdrc_ick@a10ìti,wait-gate-clock—M“ ùæŽgpmc_fckìfixed-factor-clock—My„core_l4_ickìfixed-factor-clock—Cy„æNmmchs2_ick@a10ìti,omap3-interface-clock—N“ ùæÅmmchs1_ick@a10ìti,omap3-interface-clock—N“ ùæÆhdq_ick@a10ìti,omap3-interface-clock—N“ ùæÇmcspi4_ick@a10ìti,omap3-interface-clock—N“ ùæÈmcspi3_ick@a10ìti,omap3-interface-clock—N“ ùæÉmcspi2_ick@a10ìti,omap3-interface-clock—N“ ùæÊmcspi1_ick@a10ìti,omap3-interface-clock—N“ ùæËi2c3_ick@a10ìti,omap3-interface-clock—N“ ùæÌi2c2_ick@a10ìti,omap3-interface-clock—N“ ùæÍi2c1_ick@a10ìti,omap3-interface-clock—N“ ùæÎuart2_ick@a10ìti,omap3-interface-clock—N“ ùæÏuart1_ick@a10ìti,omap3-interface-clock—N“ ù æÐgpt11_ick@a10ìti,omap3-interface-clock—N“ ù æÑgpt10_ick@a10ìti,omap3-interface-clock—N“ ù æÒmcbsp5_ick@a10ìti,omap3-interface-clock—N“ ù æÓmcbsp1_ick@a10ìti,omap3-interface-clock—N“ ù æÔomapctrl_ick@a10ìti,omap3-interface-clock—N“ ùæÕdss_tv_fck@e00ìti,gate-clock—<“ùæ´dss_96m_fck@e00ìti,gate-clock—I“ùæµdss2_alwon_fck@e00ìti,gate-clock—"“ùæ¶dummy_ckì fixed-clockGgpt1_gate_fck@c00ìti,composite-gate-clock—"ù“ æOgpt1_mux_fck@c40ìti,composite-mux-clock—D"“ @æPgpt1_fckìti,composite-clock—OPæaes2_ick@a10ìti,omap3-interface-clock—Nù“ æwkup_32k_fckìfixed-factor-clock—Dy„æQgpio1_dbck@c00ìti,gate-clock—Q“ ùæ«sha12_ick@a10ìti,omap3-interface-clock—N“ ùæÖwdt2_fck@c00ìti,wait-gate-clock—Q“ ùæ¬wdt2_ick@c10ìti,omap3-interface-clock—R“ ùæ­wdt1_ick@c10ìti,omap3-interface-clock—R“ ùæ®gpio1_ick@c10ìti,omap3-interface-clock—R“ ùæ¯omap_32ksync_ick@c10ìti,omap3-interface-clock—R“ ùæ°gpt12_ick@c10ìti,omap3-interface-clock—R“ ùæ±gpt1_ick@c10ìti,omap3-interface-clock—R“ ùæ²per_96m_fckìfixed-factor-clock—-y„æ per_48m_fckìfixed-factor-clock—4y„æSuart3_fck@1000ìti,wait-gate-clock—S“ù æ�gpt2_gate_fck@1000ìti,composite-gate-clock—"ù“æTgpt2_mux_fck@1040ìti,composite-mux-clock—D"“@æUgpt2_fckìti,composite-clock—TUægpt3_gate_fck@1000ìti,composite-gate-clock—"ù“æVgpt3_mux_fck@1040ìti,composite-mux-clock—D"ù“@æWgpt3_fckìti,composite-clock—VWgpt4_gate_fck@1000ìti,composite-gate-clock—"ù“æXgpt4_mux_fck@1040ìti,composite-mux-clock—D"ù“@æYgpt4_fckìti,composite-clock—XYgpt5_gate_fck@1000ìti,composite-gate-clock—"ù“æZgpt5_mux_fck@1040ìti,composite-mux-clock—D"ù“@æ[gpt5_fckìti,composite-clock—Z[gpt6_gate_fck@1000ìti,composite-gate-clock—"ù“æ\gpt6_mux_fck@1040ìti,composite-mux-clock—D"ù“@æ]gpt6_fckìti,composite-clock—\]gpt7_gate_fck@1000ìti,composite-gate-clock—"ù“æ^gpt7_mux_fck@1040ìti,composite-mux-clock—D"ù“@æ_gpt7_fckìti,composite-clock—^_gpt8_gate_fck@1000ìti,composite-gate-clock—"ù “æ`gpt8_mux_fck@1040ìti,composite-mux-clock—D"ù“@æagpt8_fckìti,composite-clock—`agpt9_gate_fck@1000ìti,composite-gate-clock—"ù “æbgpt9_mux_fck@1040ìti,composite-mux-clock—D"ù“@æcgpt9_fckìti,composite-clock—bcper_32k_alwon_fckìfixed-factor-clock—Dy„ædgpio6_dbck@1000ìti,gate-clock—d“ùæ‘gpio5_dbck@1000ìti,gate-clock—d“ùæ’gpio4_dbck@1000ìti,gate-clock—d“ùæ“gpio3_dbck@1000ìti,gate-clock—d“ùæ”gpio2_dbck@1000ìti,gate-clock—d“ù æ•wdt3_fck@1000ìti,wait-gate-clock—d“ù æ–per_l4_ickìfixed-factor-clock—Cy„æegpio6_ick@1010ìti,omap3-interface-clock—e“ùæ—gpio5_ick@1010ìti,omap3-interface-clock—e“ùæ˜gpio4_ick@1010ìti,omap3-interface-clock—e“ùæ™gpio3_ick@1010ìti,omap3-interface-clock—e“ùæšgpio2_ick@1010ìti,omap3-interface-clock—e“ù æ›wdt3_ick@1010ìti,omap3-interface-clock—e“ù æœuart3_ick@1010ìti,omap3-interface-clock—e“ù æ�uart4_ick@1010ìti,omap3-interface-clock—e“ùæžgpt9_ick@1010ìti,omap3-interface-clock—e“ù æŸgpt8_ick@1010ìti,omap3-interface-clock—e“ù æ gpt7_ick@1010ìti,omap3-interface-clock—e“ùæ¡gpt6_ick@1010ìti,omap3-interface-clock—e“ùæ¢gpt5_ick@1010ìti,omap3-interface-clock—e“ùæ£gpt4_ick@1010ìti,omap3-interface-clock—e“ùæ¤gpt3_ick@1010ìti,omap3-interface-clock—e“ùæ¥gpt2_ick@1010ìti,omap3-interface-clock—e“ùæ¦mcbsp2_ick@1010ìti,omap3-interface-clock—e“ùæ§mcbsp3_ick@1010ìti,omap3-interface-clock—e“ùæ¨mcbsp4_ick@1010ìti,omap3-interface-clock—e“ùæ©mcbsp2_gate_fck@1000ìti,composite-gate-clock—ù“æmcbsp3_gate_fck@1000ìti,composite-gate-clock—ù“æmcbsp4_gate_fck@1000ìti,composite-gate-clock—ù“æemu_src_mux_ck@1140ì ti,mux-clock—"fgh“@æiemu_src_ckìti,clkdm-gate-clock—iæjpclk_fck@1140ìti,divider-clock—jùW“@bpclkx2_fck@1140ìti,divider-clock—jùW“@batclk_fck@1140ìti,divider-clock—jùW“@btraceclk_src_fck@1140ì ti,mux-clock—"fghù“@æktraceclk_fck@1140ìti,divider-clock—kù W“@bsecure_32k_fckì fixed-clockG€ælgpt12_fckìfixed-factor-clock—ly„æwdt1_fckìfixed-factor-clock—ly„security_l4_ick2ìfixed-factor-clock—Cy„æmaes1_ick@a14ìti,omap3-interface-clock—mù“ ærng_ick@a14ìti,omap3-interface-clock—m“ ùæüsha11_ick@a14ìti,omap3-interface-clock—m“ ùdes1_ick@a14ìti,omap3-interface-clock—m“ ùcam_mclk@f00ìti,gate-clock—nù“¿cam_ick@f10ì!ti,omap3-no-wait-interface-clock—C“ùæÝcsi2_96m_fck@f00ìti,gate-clock—“ùæÞsecurity_l3_ickìfixed-factor-clock—By„æopka_ick@a14ìti,omap3-interface-clock—o“ ùicr_ick@a10ìti,omap3-interface-clock—N“ ùdes2_ick@a10ìti,omap3-interface-clock—N“ ùmspro_ick@a10ìti,omap3-interface-clock—N“ ùmailboxes_ick@a10ìti,omap3-interface-clock—N“ ùssi_l4_ickìfixed-factor-clock—Cy„ævsr1_fck@c00ìti,wait-gate-clock—"“ ùæsr2_fck@c00ìti,wait-gate-clock—"“ ùæ sr_l4_ickìfixed-factor-clock—Cy„dpll2_fck@40ìti,divider-clock—*ùW“@bæpdpll2_ck@4ìti,omap3-dpll-clock—"p“$@4èúæqdpll2_m2_ck@44ìti,divider-clock—qW“Dbæriva2_ck@0ìti,wait-gate-clock—r“ùæßmodem_fck@a00ìti,omap3-interface-clock—"“ ùæàsad2d_ick@a10ìti,omap3-interface-clock—B“ ùæámad2d_ick@a18ìti,omap3-interface-clock—B“ ùæâmspro_fck@a00ìti,wait-gate-clock—“ ùssi_ssr_gate_fck_3430es2@a00ì ti,composite-no-wait-gate-clock—#ù“ æsssi_ssr_div_fck_3430es2@a40ìti,composite-divider-clock—#ù“ @$ætssi_ssr_fck_3430es2ìti,composite-clock—stæussi_sst_fck_3430es2ìfixed-factor-clock—uy„æ hsotgusb_ick_3430es2@a10ì"ti,omap3-hsotgusb-interface-clock—M“ ùæ�ssi_ick_3430es2@a10ìti,omap3-ssi-interface-clock—v“ ùæ usim_gate_fck@c00ìti,composite-gate-clock—Iù “ æ�sys_d2_ckìfixed-factor-clock—"y„æxomap_96m_d2_fckìfixed-factor-clock—Iy„æyomap_96m_d4_fckìfixed-factor-clock—Iy„æzomap_96m_d8_fckìfixed-factor-clock—Iy„æ{omap_96m_d10_fckìfixed-factor-clock—Iy„ æ|dpll5_m2_d4_ckìfixed-factor-clock—wy„æ}dpll5_m2_d8_ckìfixed-factor-clock—wy„æ~dpll5_m2_d16_ckìfixed-factor-clock—wy„ædpll5_m2_d20_ckìfixed-factor-clock—wy„æ€usim_mux_fck@c40ìti,composite-mux-clock(—"xyz{|}~€ù“ @bæ‚usim_fckìti,composite-clock—�‚usim_ick@c10ìti,omap3-interface-clock—R“ ù æ³dpll5_ck@d04ìti,omap3-dpll-clock—""“  $ L 4èúæƒdpll5_m2_ck@d50ìti,divider-clock—ƒW“ Pbæwsgx_gate_fck@b00ìti,composite-gate-clock—*ù“ æ‹core_d3_ckìfixed-factor-clock—*y„æ„core_d4_ckìfixed-factor-clock—*y„æ…core_d6_ckìfixed-factor-clock—*y„æ†omap_192m_alwon_fckìfixed-factor-clock—&y„æ‡core_d2_ckìfixed-factor-clock—*y„æˆsgx_mux_fck@b40ìti,composite-mux-clock —„…†.‡ˆ‰Š“ @æŒsgx_fckìti,composite-clock—‹Œæsgx_ick@b10ìti,wait-gate-clock—B“ ùæãcpefuse_fck@a08ìti,gate-clock—"“ ùæ×ts_fck@a08ìti,gate-clock—D“ ùæØusbtll_fck@a08ìti,wait-gate-clock—w“ ùæÙusbtll_ick@a18ìti,omap3-interface-clock—N“ ùæÚmmchs3_ick@a10ìti,omap3-interface-clock—N“ ùæÛmmchs3_fck@a00ìti,wait-gate-clock—“ ùæÜdss1_alwon_fck_3430es2@e00ìti,dss-gate-clock—�ù“¿æ·dss_ick_3430es2@e10ìti,omap3-dss-interface-clock—C“ùæ¸usbhost_120m_fck@1400ìti,gate-clock—w“ùæäusbhost_48m_fck@1400ìti,dss-gate-clock—4“ùæåusbhost_ick@1410ìti,omap3-dss-interface-clock—C“ùææuart4_fck@1000ìti,wait-gate-clock—S“ùæªclockdomainscore_l3_clkdmti,clockdomain—Ž�dpll3_clkdmti,clockdomain—dpll1_clkdmti,clockdomain—per_clkdmti,clockdomainl—�‘’“”•–—˜™š›œ�žŸ ¡¢£¤¥¦§¨©ªemu_clkdmti,clockdomain—jdpll4_clkdmti,clockdomain— wkup_clkdmti,clockdomain$—«¬­®¯°±²³dss_clkdmti,clockdomain—´µ¶·¸core_l4_clkdmti,clockdomain”—¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖרÙÚÛÜcam_clkdmti,clockdomain—ÝÞiva2_clkdmti,clockdomain—ßdpll2_clkdmti,clockdomain—qd2d_clkdmti,clockdomain —àáâdpll5_clkdmti,clockdomain—ƒsgx_clkdmti,clockdomain—ãusbhost_clkdmti,clockdomain —äåætarget-module@48320000ti,sysc-omap2ti,sysc“H2H2 revsysc—Q°žfckick+ H2counter@0ti,omap-counter32k“ interrupt-controller@48200000ti,omap3-intc*“H ætarget-module@48056000ti,sysc-omap2ti,sysc“H`H`,H`(revsyscsyss# " +—Mžick+ H`dma-controller@0ti,omap3630-sdmati,omap-sdma“î 0; H`ægpio@48310000ti,omap3-gpio“H1îùgpio1Ugw*ægpio@49050000ti,omap3-gpio“Iîùgpio2gw*ægpio@49052000ti,omap3-gpio“I îùgpio3gw*gpio@49054000ti,omap3-gpio“I@î ùgpio4gw*gpio@49056000ti,omap3-gpio“I`î!ùgpio5gw*ægpio@49058000ti,omap3-gpio“I€î"ùgpio6gw*serial@4806a000ti,omap3-uart“H  ƒH812=txrxùuart1GÜlzdefaultˆçserial@4806c000ti,omap3-uart“HÀƒI834=txrxùuart2GÜlzdefaultˆèserial@49020000ti,omap3-uart“IƒJ856=txrxùuart3GÜlzdefaultˆéi2c@48070000 ti,omap3-i2c“H€î88=txrx+ùi2c1zdefaultˆêG'¬@twl@48“Hî  ti,twl4030*zdefaultˆëìaudioti,twl4030-audiocodecrtcti,twl4030-rtcî bciti,twl4030-bciî —í¥î ±vacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1¼ 'ÀÔ regulator-vdacti,twl4030-vdac¼w@Ôw@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1¼:�Ô0°æôregulator-vmmc2ti,twl4030-vmmc2¼:�Ô0°regulator-vusb1v5ti,twl4030-vusb1v5æïregulator-vusb1v8ti,twl4030-vusb1v8æðregulator-vusb3v1ti,twl4030-vusb3v1æíregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2¼w@Ôw@regulator-vsimti,twl4030-vsim¼w@Ô-ÆÀæõgpioti,twl4030-gpiogw*Âæötwl4030-usbti,twl4030-usbî ÎïÜðêíøæpwmti,twl4030-pwm pwmledti,twl4030-pwmled pwrbuttonti,twl4030-pwrbuttonîkeypadti,twl4030-keypadî'madcti,twl4030-madcî:æîi2c@48072000 ti,omap3-i2c“H €î98=txrx+ùi2c2i2c@48060000 ti,omap3-i2c“H€î=8=txrx+ùi2c3zdefaultˆñmailbox@48094000ti,omap3-mailboxùmailbox“H @îLXjdsp | ‡spi@48098000ti,omap2-mcspi“H €îA+ùmcspi1’@8#$%&'()* =tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspi“H  îB+ùmcspi2’ 8+,-.=tx0rx0tx1rx1spi@480b8000ti,omap2-mcspi“H €î[+ùmcspi3’ 8=tx0rx0tx1rx1spi@480ba000ti,omap2-mcspi“H  î0+ùmcspi4’8FG=tx0rx01w@480b2000 ti,omap3-1w“H î:ùhdq1wmmc@4809c000ti,omap3-hsmmc“H ÀîSùmmc1 8=>=txrx­òzdefaultˆóºôÆõÖ àömmc@480b4000ti,omap3-hsmmc“H @îVùmmc28/0=txrxzdefaultˆ÷øºùéúÖômmc@480ad000ti,omap3-hsmmc“H Ðî^ùmmc38MN=txrx disabledmmu@480bd400 ti,omap2-iommu“H Ô€îùmmu_ispæ mmu@5d000000 ti,omap2-iommu“]€îùmmu_iva disabledwdt@48314000 ti,omap3-wdt“H1@€ ùwd_timer2mcbsp@48074000ti,omap3-mcbsp“H@ÿmpu î;< &commontxrx6€ùmcbsp18 =txrx—ûžfck disabledtarget-module@480a0000ti,sysc-omap2ti,sysc“H <H @H Drevsyscsyss+—üžick+ H rng@0 ti,omap2-rng“ î4mcbsp@49022000ti,omap3-mcbsp“I ÿI€ÿ mpusidetoneî>?&commontxrxsidetone6ùmcbsp2mcbsp2_sidetone8!"=txrx—ý§žfckickokayzdefaultˆþæmcbsp@49024000ti,omap3-mcbsp“I@ÿI ÿ mpusidetoneîYZ&commontxrxsidetone6€ùmcbsp3mcbsp3_sidetone8=txrx—ÿ¨žfckick disabledmcbsp@49026000ti,omap3-mcbsp“I`ÿmpu î67 &commontxrx6€ùmcbsp48=txrx—žfckE disabledmcbsp@48096000ti,omap3-mcbsp“H `ÿmpu îQR &commontxrx6€ùmcbsp58=txrx—žfck disabledsham@480c3000ti,omap3-shamùsham“H 0dî18E=rxtarget-module@48318000ti,sysc-omap2-timerti,sysc“H1€H1€H1€revsyscsyss' +—²žfckick+ H1€Vjtimer@0ti,omap3430-timer“€—žfckî%u„”Dtarget-module@49032000ti,sysc-omap2-timerti,sysc“I I I revsyscsyss' +—¦žfckick+ I timer@0ti,omap3430-timer“î&timer@49034000ti,omap3430-timer“I@î'ùtimer3timer@49036000ti,omap3430-timer“I`î(ùtimer4timer@49038000ti,omap3430-timer“I€î)ùtimer5«timer@4903a000ti,omap3430-timer“I î*ùtimer6«timer@4903c000ti,omap3430-timer“IÀî+ùtimer7«timer@4903e000ti,omap3430-timer“Iàî,ùtimer8¸«timer@49040000ti,omap3430-timer“Iî-ùtimer9¸timer@48086000ti,omap3430-timer“H`î.ùtimer10¸timer@48088000ti,omap3430-timer“H€î/ùtimer11¸target-module@48304000ti,sysc-omap2-timerti,sysc“H0@H0@H0@revsyscsyss' +—±žfckick+ H0@timer@0ti,omap3430-timer“î_uÅusbhstll@48062000 ti,usbhs-tll“H îN ùusb_tll_hsusbhshost@48064000ti,usbhs-host“H@ ùusb_host_hs+ Õehci-phyohci@48064400ti,ohci-omap3“HDîLàehci@48064800 ti,ehci-omap“HHîMøgpmc@6e000000ti,omap3430-gpmcùgpmc“nÐî8=rxtxý +*gwzdefaultˆ0ænand@0,0ti,omap2-nand “ îmicron,mt29c4g96maz*9Kbch8[lz,Œ,ž­"À,Ó(â6ñ@RR"(4+okayonenand@0,0ti,omap2-onenand “L[k}��9®lz`Œ`ž­ À Àâ`ÎÓ`rrñZÜ ö '?4"Z[.à+ disabledusb_otg_hs@480ab000ti,omap3-musb“H °î\]&mcdma ùusb_otg_hsVai r�ø ‰usb2-phyü“2dss@48050000 ti,omap3-dss“H disabled ùdss_core—·žfck+dispc@48050400ti,omap3-dispc“Hî ùdss_dispc—·žfckencoder@4804fc00 ti,omap3-dsi“HüHþ@Hÿ protophypllî disabled ùdss_dsi1—·¶ žfcksys_clk+encoder@48050800ti,omap3-rfbi“H disabled ùdss_rfbi—·¸žfckickencoder@48050c00ti,omap3-venc“H  disabled ùdss_venc—´µžfcktv_dac_clkssi-controller@48058000 ti,omap3-ssiùssiokay“H€H�sysgddîG&gdd_mpu+ —u   žssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-port“H H¨txrxîCDssi-port@4805b000ti,omap3-ssi-port“H°H¸txrxîEFserial@49042000ti,omap3-uart“I îP8QR=txrxùuart4GÜlregulator-abb-mpu ti,abb-v1 ­abb_mpu_iva+“H0rðH0hbase-addressint-address™—"²Ã`ÓsO€7Èûæpinmux@480025a0 ti,omap3-padconfpinctrl-single“H% \+ *?]ÿzdefaultˆ pinmux_hsusb2_core2_pins0’PRT V X Z æ pinmux_leds_core2_pins’@æisp@480bc000 ti,omap3-isp“H ÀüH Øîß ¦ðæìports+bandgap@48002524“H%$ti,omap36xx-bandgapòætarget-module@480cb000ti,sysc-omap3630-srti,syscùsmartreflex_core“H °8sysc — žfck+ H °smartreflex@0ti,omap3-smartreflex-core“îtarget-module@480c9000ti,sysc-omap3630-srti,syscùsmartreflex_mpu_iva“H �8sysc —žfck+ H �smartreflex@480c9000ti,omap3-smartreflex-mpu-iva“îtarget-module@50000000ti,sysc-omap4ti,sysc“PþPþ revsysc " —ãžfckick+ Popp-tableoperating-points-v2-ti-cpu¦æopp50-300000000 ᣠssssss ÿÿÿÿ .opp100-600000000 #ÃF O€O€O€O€O€O€ ÿÿÿÿopp130-800000000 /¯ 7È7È7È7È7È7È ÿÿÿÿopp1g-1000000000 ;šÊ ûûûûûû ÿÿÿÿ :opp_supplyti,omap-opp-supply Eûthermal-zonescpu_thermal `ú vè „N  ‘tripscpu_alert ¡8€ ­ÐŽpassiveæcpu_crit ¡_� ­Ð Žcriticalcooling-mapsmap0 ¸ ½ÿÿÿÿÿÿÿÿmemory@80000000‡memory“€ soundti,omap-twl4030 Ìigep2 Õregulator-vdd33regulator-fixed­vdd33 Þgpio_leds gpio-ledszdefaultˆuser0 òomap3:red:user0 ãö øoffuser1 òomap3:green:user1 ãö øoffuser2 òomap3:red:user1 ã øoffboot òomap3:green:boot ãö  øonhsusb2_phyusb-nop-xceiv æfixedregulator-mmcsdioregulator-fixed­vmmcsdio_fixed¼2Z Ô2Z æùmmc2_pwrseqmmc-pwrseq-simple   æú compatibleinterrupt-parent#address-cells#size-cellsmodelstdout-pathi2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-points-v2vbb-supply#cooling-cellsphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-widthcd-gpiosmmc-pwrseqnon-removablestatus#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nsgpmc,sync-readgpmc,sync-writegpmc,burst-lengthgpmc,burst-wrapgpmc,burst-readgpmc,burst-writegpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modeti,absolute-max-voltage-uvpolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-deviceti,modelti,mcbspregulator-always-onlabeldefault-statereset-gpios