Ð þí Û8ÿà( ûÿ¨5isee,omap3-igep0020ti,omap3630ti,omap36xxti,omap3 +!7IGEPv2 Rev. C (TI OMAP AM/DM37x)chosen=/ocp@68000000/serial@49020000aliasesI/ocp@68000000/i2c@48070000N/ocp@68000000/i2c@48072000S/ocp@68000000/i2c@48060000X/ocp@68000000/mmc@4809c000]/ocp@68000000/mmc@480b4000b/ocp@68000000/mmc@480ad000g/ocp@68000000/serial@4806a000o/ocp@68000000/serial@4806c000w/ocp@68000000/serial@49020000/ocp@68000000/serial@49042000cpus+cpu@0arm,cortex-a8‡cpu“—žcpuª“à¸Ì׿pmu@54000000arm,cortex-a8-pmu“T€îùdebugsssocti,omap-inframpu ti,omap3-mpuùmpuiva ti,iva2.2ùivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus“hî +ùl3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus“ +  pinmux@30 ti,omap3-padconfpinctrl-single“08+ *?]ÿzdefaultˆpinmux_gpmc_pins’Žæ pinmux_uart1_pins’RLæèpinmux_uart3_pins’npæêpinmux_mcbsp2_pins ’ æpinmux_mmc1_pins0’æôpinmux_mmc2_pins0’(*,.02æúpinmux_i2c1_pins’ŠŒæëpinmux_i2c3_pins’’”æòpinmux_twl4030_pins’°Aæìpinmux_tfp410_pins’–æpinmux_dss_dpi_pinsà’¤¦¨ª¬®°²´¶¸º¼¾ÀÂÄÆÈÊÌÎÐÒÔÖØÚæpinmux_uart2_pins ’DFHJæépinmux_smsc9221_pins’¢æ pinmux_lbee1usjyc_pins’68:æûscm_conf@270sysconsimple-bus“p0+ p0æpbias_regulator@2b0ti,pbias-omap3ti,pbias-omap“°¦pbias_mmc_omap2430­pbias_mmc_omap2430¼w@Ô-ÆÀæóclocks+mcbsp5_mux_fck@68ìti,composite-mux-clock— ù“hæ mcbsp5_fckìti,composite-clock— æmcbsp1_mux_fck@4ìti,composite-mux-clock— ù“æ mcbsp1_fckìti,composite-clock— æþmcbsp2_mux_fck@4ìti,composite-mux-clock— ù“æmcbsp2_fckìti,composite-clock—æmcbsp3_mux_fck@68ìti,composite-mux-clock— “hæmcbsp3_fckìti,composite-clock—æmcbsp4_mux_fck@68ìti,composite-mux-clock— ù“hæmcbsp4_fckìti,composite-clock—æclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single“ \+ *?]ÿpinmux_twl4030_vpins ’æítarget-module@480a6000ti,sysc-omap2ti,sysc“H `DH `HH `Lrevsyscsyss +—žick+ H ` aes1@0 ti,omap3-aes“Pî8  =txrxtarget-module@480c5000ti,sysc-omap2ti,sysc“H PDH PHH PLrevsyscsyss +—žick+ H P aes2@0 ti,omap3-aes“Pî8AB=txrxprm@48306000 ti,omap3-prm“H0`@î clocks+virt_16_8m_ckì fixed-clockGYæosc_sys_ck@d40ì ti,mux-clock—“ @æsys_ck@1270ìti,divider-clock—ùW“pbæ#sys_clkout1@d70ìti,gate-clock—“ pùdpll3_x2_ckìfixed-factor-clock—y„dpll3_m2x2_ckìfixed-factor-clock— y„æ"dpll4_x2_ckìfixed-factor-clock—!y„corex2_fckìfixed-factor-clock—"y„æ$wkup_l4_ickìfixed-factor-clock—#y„æScorex2_d3_fckìfixed-factor-clock—$y„æŠcorex2_d5_fckìfixed-factor-clock—$y„æ‹clockdomainscm@48004000 ti,omap3-cm“H@@clocks+dummy_apb_pclkì fixed-clockGomap_32k_fckì fixed-clockG€æEvirt_12m_ckì fixed-clockG·ævirt_13m_ckì fixed-clockGÆ]@ævirt_19200000_ckì fixed-clockG$øævirt_26000000_ckì fixed-clockGŒº€ævirt_38_4m_ckì fixed-clockGIðædpll4_ck@d00ìti,omap3-dpll-per-j-type-clock—##“ D 0æ!dpll4_m2_ck@d48ìti,divider-clock—!W?“ Hbæ%dpll4_m2x2_mul_ckìfixed-factor-clock—%y„æ&dpll4_m2x2_ck@d00ìti,hsdiv-gate-clock—&ù“ Žæ'omap_96m_alwon_fckìfixed-factor-clock—'y„æ.dpll3_ck@d00ìti,omap3-dpll-core-clock—##“ @ 0ædpll3_m3_ck@1140ìti,divider-clock—ùW“@bæ(dpll3_m3x2_mul_ckìfixed-factor-clock—(y„æ)dpll3_m3x2_ck@d00ìti,hsdiv-gate-clock—)ù “ Žæ*emu_core_alwon_ckìfixed-factor-clock—*y„ægsys_altclkì fixed-clockGæ3mcbsp_clksì fixed-clockGæ dpll3_m2_ck@d40ìti,divider-clock—ùW“ @bæ core_ckìfixed-factor-clock— y„æ+dpll1_fck@940ìti,divider-clock—+ùW“ @bæ,dpll1_ck@904ìti,omap3-dpll-clock—#,“  $ @ 4ædpll1_x2_ckìfixed-factor-clock—y„æ-dpll1_x2m2_ck@944ìti,divider-clock—-W“ DbæAcm_96m_fckìfixed-factor-clock—.y„æ/omap_96m_fck@d40ì ti,mux-clock—/#ù“ @æJdpll4_m3_ck@e40ìti,divider-clock—!ùW “@bæ0dpll4_m3x2_mul_ckìfixed-factor-clock—0y„æ1dpll4_m3x2_ck@d00ìti,hsdiv-gate-clock—1ù“ Žæ2omap_54m_fck@d40ì ti,mux-clock—23ù“ @æ=cm_96m_d2_fckìfixed-factor-clock—/y„æ4omap_48m_fck@d40ì ti,mux-clock—43ù“ @æ5omap_12m_fckìfixed-factor-clock—5y„æLdpll4_m4_ck@e40ìti,divider-clock—!W“@bæ6dpll4_m4x2_mul_ckìti,fixed-factor-clock—6¤²¿æ7dpll4_m4x2_ck@d00ìti,gate-clock—7ù“ Ž¿æŽdpll4_m5_ck@f40ìti,divider-clock—!W?“@bæ8dpll4_m5x2_mul_ckìti,fixed-factor-clock—8¤²¿æ9dpll4_m5x2_ck@d00ìti,hsdiv-gate-clock—9ù“ Ž¿æodpll4_m6_ck@1140ìti,divider-clock—!ùW?“@bæ:dpll4_m6x2_mul_ckìfixed-factor-clock—:y„æ;dpll4_m6x2_ck@d00ìti,hsdiv-gate-clock—;ù“ Žæ<emu_per_alwon_ckìfixed-factor-clock—<y„æhclkout2_src_gate_ck@d70ì ti,composite-no-wait-gate-clock—+ù“ pæ>clkout2_src_mux_ck@d70ìti,composite-mux-clock—+#/=“ pæ?clkout2_src_ckìti,composite-clock—>?æ@sys_clkout2@d70ìti,divider-clock—@ùW@“ pÒmpu_ckìfixed-factor-clock—Ay„æBarm_fck@924ìti,divider-clock—B“ $Wemu_mpu_alwon_ckìfixed-factor-clock—By„æil3_ick@a40ìti,divider-clock—+W“ @bæCl4_ick@a40ìti,divider-clock—CùW“ @bæDrm_ick@c40ìti,divider-clock—DùW“ @bgpt10_gate_fck@a00ìti,composite-gate-clock—#ù “ æFgpt10_mux_fck@a40ìti,composite-mux-clock—E#ù“ @æGgpt10_fckìti,composite-clock—FGgpt11_gate_fck@a00ìti,composite-gate-clock—#ù “ æHgpt11_mux_fck@a40ìti,composite-mux-clock—E#ù“ @æIgpt11_fckìti,composite-clock—HIcore_96m_fckìfixed-factor-clock—Jy„æmmchs2_fck@a00ìti,wait-gate-clock—“ ùæºmmchs1_fck@a00ìti,wait-gate-clock—“ ùæ»i2c3_fck@a00ìti,wait-gate-clock—“ ùæ¼i2c2_fck@a00ìti,wait-gate-clock—“ ùæ½i2c1_fck@a00ìti,wait-gate-clock—“ ùæ¾mcbsp5_gate_fck@a00ìti,composite-gate-clock— ù “ æ mcbsp1_gate_fck@a00ìti,composite-gate-clock— ù “ æ core_48m_fckìfixed-factor-clock—5y„æKmcspi4_fck@a00ìti,wait-gate-clock—K“ ùæ¿mcspi3_fck@a00ìti,wait-gate-clock—K“ ùæÀmcspi2_fck@a00ìti,wait-gate-clock—K“ ùæÁmcspi1_fck@a00ìti,wait-gate-clock—K“ ùæÂuart2_fck@a00ìti,wait-gate-clock—K“ ùæÃuart1_fck@a00ìti,wait-gate-clock—K“ ù æÄcore_12m_fckìfixed-factor-clock—Ly„æMhdq_fck@a00ìti,wait-gate-clock—M“ ùæÅcore_l3_ickìfixed-factor-clock—Cy„æNsdrc_ick@a10ìti,wait-gate-clock—N“ ùæ�gpmc_fckìfixed-factor-clock—Ny„core_l4_ickìfixed-factor-clock—Dy„æOmmchs2_ick@a10ìti,omap3-interface-clock—O“ ùæÆmmchs1_ick@a10ìti,omap3-interface-clock—O“ ùæÇhdq_ick@a10ìti,omap3-interface-clock—O“ ùæÈmcspi4_ick@a10ìti,omap3-interface-clock—O“ ùæÉmcspi3_ick@a10ìti,omap3-interface-clock—O“ ùæÊmcspi2_ick@a10ìti,omap3-interface-clock—O“ ùæËmcspi1_ick@a10ìti,omap3-interface-clock—O“ ùæÌi2c3_ick@a10ìti,omap3-interface-clock—O“ ùæÍi2c2_ick@a10ìti,omap3-interface-clock—O“ ùæÎi2c1_ick@a10ìti,omap3-interface-clock—O“ ùæÏuart2_ick@a10ìti,omap3-interface-clock—O“ ùæÐuart1_ick@a10ìti,omap3-interface-clock—O“ ù æÑgpt11_ick@a10ìti,omap3-interface-clock—O“ ù æÒgpt10_ick@a10ìti,omap3-interface-clock—O“ ù æÓmcbsp5_ick@a10ìti,omap3-interface-clock—O“ ù æÔmcbsp1_ick@a10ìti,omap3-interface-clock—O“ ù æÕomapctrl_ick@a10ìti,omap3-interface-clock—O“ ùæÖdss_tv_fck@e00ìti,gate-clock—=“ùæµdss_96m_fck@e00ìti,gate-clock—J“ùæ¶dss2_alwon_fck@e00ìti,gate-clock—#“ùæ·dummy_ckì fixed-clockGgpt1_gate_fck@c00ìti,composite-gate-clock—#ù“ æPgpt1_mux_fck@c40ìti,composite-mux-clock—E#“ @æQgpt1_fckìti,composite-clock—PQæaes2_ick@a10ìti,omap3-interface-clock—Où“ æwkup_32k_fckìfixed-factor-clock—Ey„æRgpio1_dbck@c00ìti,gate-clock—R“ ùæ¬sha12_ick@a10ìti,omap3-interface-clock—O“ ùæ×wdt2_fck@c00ìti,wait-gate-clock—R“ ùæ­wdt2_ick@c10ìti,omap3-interface-clock—S“ ùæ®wdt1_ick@c10ìti,omap3-interface-clock—S“ ùæ¯gpio1_ick@c10ìti,omap3-interface-clock—S“ ùæ°omap_32ksync_ick@c10ìti,omap3-interface-clock—S“ ùæ±gpt12_ick@c10ìti,omap3-interface-clock—S“ ùæ²gpt1_ick@c10ìti,omap3-interface-clock—S“ ùæ³per_96m_fckìfixed-factor-clock—.y„æper_48m_fckìfixed-factor-clock—5y„æTuart3_fck@1000ìti,wait-gate-clock—T“ù æ‘gpt2_gate_fck@1000ìti,composite-gate-clock—#ù“æUgpt2_mux_fck@1040ìti,composite-mux-clock—E#“@æVgpt2_fckìti,composite-clock—UVægpt3_gate_fck@1000ìti,composite-gate-clock—#ù“æWgpt3_mux_fck@1040ìti,composite-mux-clock—E#ù“@æXgpt3_fckìti,composite-clock—WXgpt4_gate_fck@1000ìti,composite-gate-clock—#ù“æYgpt4_mux_fck@1040ìti,composite-mux-clock—E#ù“@æZgpt4_fckìti,composite-clock—YZgpt5_gate_fck@1000ìti,composite-gate-clock—#ù“æ[gpt5_mux_fck@1040ìti,composite-mux-clock—E#ù“@æ\gpt5_fckìti,composite-clock—[\gpt6_gate_fck@1000ìti,composite-gate-clock—#ù“æ]gpt6_mux_fck@1040ìti,composite-mux-clock—E#ù“@æ^gpt6_fckìti,composite-clock—]^gpt7_gate_fck@1000ìti,composite-gate-clock—#ù“æ_gpt7_mux_fck@1040ìti,composite-mux-clock—E#ù“@æ`gpt7_fckìti,composite-clock—_`gpt8_gate_fck@1000ìti,composite-gate-clock—#ù “æagpt8_mux_fck@1040ìti,composite-mux-clock—E#ù“@æbgpt8_fckìti,composite-clock—abgpt9_gate_fck@1000ìti,composite-gate-clock—#ù “æcgpt9_mux_fck@1040ìti,composite-mux-clock—E#ù“@ædgpt9_fckìti,composite-clock—cdper_32k_alwon_fckìfixed-factor-clock—Ey„æegpio6_dbck@1000ìti,gate-clock—e“ùæ’gpio5_dbck@1000ìti,gate-clock—e“ùæ“gpio4_dbck@1000ìti,gate-clock—e“ùæ”gpio3_dbck@1000ìti,gate-clock—e“ùæ•gpio2_dbck@1000ìti,gate-clock—e“ù æ–wdt3_fck@1000ìti,wait-gate-clock—e“ù æ—per_l4_ickìfixed-factor-clock—Dy„æfgpio6_ick@1010ìti,omap3-interface-clock—f“ùæ˜gpio5_ick@1010ìti,omap3-interface-clock—f“ùæ™gpio4_ick@1010ìti,omap3-interface-clock—f“ùæšgpio3_ick@1010ìti,omap3-interface-clock—f“ùæ›gpio2_ick@1010ìti,omap3-interface-clock—f“ù æœwdt3_ick@1010ìti,omap3-interface-clock—f“ù æ�uart3_ick@1010ìti,omap3-interface-clock—f“ù æžuart4_ick@1010ìti,omap3-interface-clock—f“ùæŸgpt9_ick@1010ìti,omap3-interface-clock—f“ù æ gpt8_ick@1010ìti,omap3-interface-clock—f“ù æ¡gpt7_ick@1010ìti,omap3-interface-clock—f“ùæ¢gpt6_ick@1010ìti,omap3-interface-clock—f“ùæ£gpt5_ick@1010ìti,omap3-interface-clock—f“ùæ¤gpt4_ick@1010ìti,omap3-interface-clock—f“ùæ¥gpt3_ick@1010ìti,omap3-interface-clock—f“ùæ¦gpt2_ick@1010ìti,omap3-interface-clock—f“ùæ§mcbsp2_ick@1010ìti,omap3-interface-clock—f“ùæ¨mcbsp3_ick@1010ìti,omap3-interface-clock—f“ùæ©mcbsp4_ick@1010ìti,omap3-interface-clock—f“ùæªmcbsp2_gate_fck@1000ìti,composite-gate-clock— ù“æmcbsp3_gate_fck@1000ìti,composite-gate-clock— ù“æmcbsp4_gate_fck@1000ìti,composite-gate-clock— ù“æemu_src_mux_ck@1140ì ti,mux-clock—#ghi“@æjemu_src_ckìti,clkdm-gate-clock—jækpclk_fck@1140ìti,divider-clock—kùW“@bpclkx2_fck@1140ìti,divider-clock—kùW“@batclk_fck@1140ìti,divider-clock—kùW“@btraceclk_src_fck@1140ì ti,mux-clock—#ghiù“@æltraceclk_fck@1140ìti,divider-clock—lù W“@bsecure_32k_fckì fixed-clockG€æmgpt12_fckìfixed-factor-clock—my„æwdt1_fckìfixed-factor-clock—my„security_l4_ick2ìfixed-factor-clock—Dy„ænaes1_ick@a14ìti,omap3-interface-clock—nù“ ærng_ick@a14ìti,omap3-interface-clock—n“ ùæÿsha11_ick@a14ìti,omap3-interface-clock—n“ ùdes1_ick@a14ìti,omap3-interface-clock—n“ ùcam_mclk@f00ìti,gate-clock—où“¿cam_ick@f10ì!ti,omap3-no-wait-interface-clock—D“ùæÞcsi2_96m_fck@f00ìti,gate-clock—“ùæßsecurity_l3_ickìfixed-factor-clock—Cy„æppka_ick@a14ìti,omap3-interface-clock—p“ ùicr_ick@a10ìti,omap3-interface-clock—O“ ùdes2_ick@a10ìti,omap3-interface-clock—O“ ùmspro_ick@a10ìti,omap3-interface-clock—O“ ùmailboxes_ick@a10ìti,omap3-interface-clock—O“ ùssi_l4_ickìfixed-factor-clock—Dy„æwsr1_fck@c00ìti,wait-gate-clock—#“ ùæsr2_fck@c00ìti,wait-gate-clock—#“ ùæsr_l4_ickìfixed-factor-clock—Dy„dpll2_fck@40ìti,divider-clock—+ùW“@bæqdpll2_ck@4ìti,omap3-dpll-clock—#q“$@4èúærdpll2_m2_ck@44ìti,divider-clock—rW“Dbæsiva2_ck@0ìti,wait-gate-clock—s“ùæàmodem_fck@a00ìti,omap3-interface-clock—#“ ùæásad2d_ick@a10ìti,omap3-interface-clock—C“ ùæâmad2d_ick@a18ìti,omap3-interface-clock—C“ ùæãmspro_fck@a00ìti,wait-gate-clock—“ ùssi_ssr_gate_fck_3430es2@a00ì ti,composite-no-wait-gate-clock—$ù“ ætssi_ssr_div_fck_3430es2@a40ìti,composite-divider-clock—$ù“ @$æussi_ssr_fck_3430es2ìti,composite-clock—tuævssi_sst_fck_3430es2ìfixed-factor-clock—vy„æhsotgusb_ick_3430es2@a10ì"ti,omap3-hsotgusb-interface-clock—N“ ùæ�ssi_ick_3430es2@a10ìti,omap3-ssi-interface-clock—w“ ùæusim_gate_fck@c00ìti,composite-gate-clock—Jù “ æ‚sys_d2_ckìfixed-factor-clock—#y„æyomap_96m_d2_fckìfixed-factor-clock—Jy„æzomap_96m_d4_fckìfixed-factor-clock—Jy„æ{omap_96m_d8_fckìfixed-factor-clock—Jy„æ|omap_96m_d10_fckìfixed-factor-clock—Jy„ æ}dpll5_m2_d4_ckìfixed-factor-clock—xy„æ~dpll5_m2_d8_ckìfixed-factor-clock—xy„ædpll5_m2_d16_ckìfixed-factor-clock—xy„æ€dpll5_m2_d20_ckìfixed-factor-clock—xy„æ�usim_mux_fck@c40ìti,composite-mux-clock(—#yz{|}~€�ù“ @bæƒusim_fckìti,composite-clock—‚ƒusim_ick@c10ìti,omap3-interface-clock—S“ ù æ´dpll5_ck@d04ìti,omap3-dpll-clock—##“  $ L 4èúæ„dpll5_m2_ck@d50ìti,divider-clock—„W“ Pbæxsgx_gate_fck@b00ìti,composite-gate-clock—+ù“ æŒcore_d3_ckìfixed-factor-clock—+y„æ…core_d4_ckìfixed-factor-clock—+y„æ†core_d6_ckìfixed-factor-clock—+y„æ‡omap_192m_alwon_fckìfixed-factor-clock—'y„æˆcore_d2_ckìfixed-factor-clock—+y„æ‰sgx_mux_fck@b40ìti,composite-mux-clock —…†‡/ˆ‰Š‹“ @æ�sgx_fckìti,composite-clock—Œ�æsgx_ick@b10ìti,wait-gate-clock—C“ ùæäcpefuse_fck@a08ìti,gate-clock—#“ ùæØts_fck@a08ìti,gate-clock—E“ ùæÙusbtll_fck@a08ìti,wait-gate-clock—x“ ùæÚusbtll_ick@a18ìti,omap3-interface-clock—O“ ùæÛmmchs3_ick@a10ìti,omap3-interface-clock—O“ ùæÜmmchs3_fck@a00ìti,wait-gate-clock—“ ùæÝdss1_alwon_fck_3430es2@e00ìti,dss-gate-clock—Žù“¿æ¸dss_ick_3430es2@e10ìti,omap3-dss-interface-clock—D“ùæ¹usbhost_120m_fck@1400ìti,gate-clock—x“ùæåusbhost_48m_fck@1400ìti,dss-gate-clock—5“ùææusbhost_ick@1410ìti,omap3-dss-interface-clock—D“ùæçuart4_fck@1000ìti,wait-gate-clock—T“ùæ«clockdomainscore_l3_clkdmti,clockdomain—��dpll3_clkdmti,clockdomain—dpll1_clkdmti,clockdomain—per_clkdmti,clockdomainl—‘’“”•–—˜™š›œ�žŸ ¡¢£¤¥¦§¨©ª«emu_clkdmti,clockdomain—kdpll4_clkdmti,clockdomain—!wkup_clkdmti,clockdomain$—¬­®¯°±²³´dss_clkdmti,clockdomain—µ¶·¸¹core_l4_clkdmti,clockdomain”—º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖרÙÚÛÜÝcam_clkdmti,clockdomain—Þßiva2_clkdmti,clockdomain—àdpll2_clkdmti,clockdomain—rd2d_clkdmti,clockdomain —áâãdpll5_clkdmti,clockdomain—„sgx_clkdmti,clockdomain—äusbhost_clkdmti,clockdomain —åæçtarget-module@48320000ti,sysc-omap2ti,sysc“H2H2 revsysc—R±žfckick+ H2counter@0ti,omap-counter32k“ interrupt-controller@48200000ti,omap3-intc*“H ætarget-module@48056000ti,sysc-omap2ti,sysc“H`H`,H`(revsyscsyss# " +—Nžick+ H`dma-controller@0ti,omap3630-sdmati,omap-sdma“î 0; H`ægpio@48310000ti,omap3-gpio“H1îùgpio1Ugw*æùgpio@49050000ti,omap3-gpio“Iîùgpio2gw*gpio@49052000ti,omap3-gpio“I îùgpio3gw*gpio@49054000ti,omap3-gpio“I@î ùgpio4gw*gpio@49056000ti,omap3-gpio“I`î!ùgpio5gw*æ"gpio@49058000ti,omap3-gpio“I€î"ùgpio6gw*æserial@4806a000ti,omap3-uart“H  ƒH812=txrxùuart1GÜlzdefaultˆèserial@4806c000ti,omap3-uart“HÀƒI834=txrxùuart2GÜlzdefaultˆéserial@49020000ti,omap3-uart“IƒJ856=txrxùuart3GÜlzdefaultˆêi2c@48070000 ti,omap3-i2c“H€î88=txrx+ùi2c1zdefaultˆëG'¬@twl@48“Hî  ti,twl4030*zdefaultˆìíaudioti,twl4030-audiocodecrtcti,twl4030-rtcî bciti,twl4030-bciî —î¥ï ±vacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1¼ 'ÀÔ regulator-vdacti,twl4030-vdac¼w@Ôw@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1¼:�Ô0°æöregulator-vmmc2ti,twl4030-vmmc2¼:�Ô0°regulator-vusb1v5ti,twl4030-vusb1v5æðregulator-vusb1v8ti,twl4030-vusb1v8æñregulator-vusb3v1ti,twl4030-vusb3v1æîregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2¼w@Ôw@ ­vdds_dsiregulator-vsimti,twl4030-vsim¼w@Ô-ÆÀæ÷gpioti,twl4030-gpiogw*Âæøtwl4030-usbti,twl4030-usbî ÎðÜñêîøæpwmti,twl4030-pwm pwmledti,twl4030-pwmled pwrbuttonti,twl4030-pwrbuttonîkeypadti,twl4030-keypadî'madcti,twl4030-madcî:æïi2c@48072000 ti,omap3-i2c“H €î98=txrx+ùi2c2i2c@48060000 ti,omap3-i2c“H€î=8=txrx+ùi2c3zdefaultˆòG† æ eeprom@50 ti,eeprom“Pmailbox@48094000ti,omap3-mailboxùmailbox“H @îLXjdsp | ‡spi@48098000ti,omap2-mcspi“H €îA+ùmcspi1’@8#$%&'()* =tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspi“H  îB+ùmcspi2’ 8+,-.=tx0rx0tx1rx1spi@480b8000ti,omap2-mcspi“H €î[+ùmcspi3’ 8=tx0rx0tx1rx1spi@480ba000ti,omap2-mcspi“H  î0+ùmcspi4’8FG=tx0rx01w@480b2000 ti,omap3-1w“H î:ùhdq1wmmc@4809c000ti,omap3-hsmmc“H ÀîSùmmc1 8=>=txrx­ózdefaultˆôõºöÆ÷Ö àø éùmmc@480b4000ti,omap3-hsmmc“H @îVùmmc28/0=txrxzdefaultˆúûºüòýÖýmmc@480ad000ti,omap3-hsmmc“H Ðî^ùmmc38MN=txrx  disabledmmu@480bd400ti,omap2-iommu“H Ô€îùmmu_ispæmmu@5d000000ti,omap2-iommu“]€îùmmu_iva  disabledwdt@48314000 ti,omap3-wdt“H1@€ ùwd_timer2mcbsp@48074000ti,omap3-mcbsp“H@ÿmpu î;< /commontxrx?€ùmcbsp18 =txrx—þžfck  disabledtarget-module@480a0000ti,sysc-omap2ti,sysc“H <H @H Drevsyscsyss+—ÿžick+ H rng@0 ti,omap2-rng“ î4mcbsp@49022000ti,omap3-mcbsp“I ÿI€ÿ mpusidetoneî>?/commontxrxsidetone?ùmcbsp2mcbsp2_sidetone8!"=txrx—¨žfckick okayzdefaultˆæmcbsp@49024000ti,omap3-mcbsp“I@ÿI ÿ mpusidetoneîYZ/commontxrxsidetone?€ùmcbsp3mcbsp3_sidetone8=txrx—©žfckick  disabledmcbsp@49026000ti,omap3-mcbsp“I`ÿmpu î67 /commontxrx?€ùmcbsp48=txrx—žfckN  disabledmcbsp@48096000ti,omap3-mcbsp“H `ÿmpu îQR /commontxrx?€ùmcbsp58=txrx—žfck  disabledsham@480c3000ti,omap3-shamùsham“H 0dî18E=rxtarget-module@48318000ti,sysc-omap2-timerti,sysc“H1€H1€H1€revsyscsyss' +—³žfckick+ H1€_stimer@0ti,omap3430-timer“€—žfckî%~��Etarget-module@49032000ti,sysc-omap2-timerti,sysc“I I I revsyscsyss' +—§žfckick+ I timer@0ti,omap3430-timer“î&timer@49034000ti,omap3430-timer“I@î'ùtimer3timer@49036000ti,omap3430-timer“I`î(ùtimer4timer@49038000ti,omap3430-timer“I€î)ùtimer5´timer@4903a000ti,omap3430-timer“I î*ùtimer6´timer@4903c000ti,omap3430-timer“IÀî+ùtimer7´timer@4903e000ti,omap3430-timer“Iàî,ùtimer8Á´timer@49040000ti,omap3430-timer“Iî-ùtimer9Átimer@48086000ti,omap3430-timer“H`î.ùtimer10Átimer@48088000ti,omap3430-timer“H€î/ùtimer11Átarget-module@48304000ti,sysc-omap2-timerti,sysc“H0@H0@H0@revsyscsyss' +—²žfckick+ H0@timer@0ti,omap3430-timer“î_~Îusbhstll@48062000 ti,usbhs-tll“H îN ùusb_tll_hsusbhshost@48064000ti,usbhs-host“H@ ùusb_host_hs+ Þehci-phyohci@48064400ti,ohci-omap3“HDîLéehci@48064800 ti,ehci-omap“HHîMgpmc@6e000000ti,omap3430-gpmcùgpmc“nÐî8=rxtx+*gwzdefaultˆ  0,æ nand@0,0ti,omap2-nand “  î$micron,mt29c4g96maz3BTbch8duƒ,•,§¶"É,Ü(ë6ú@ RR+(=+ okayonenand@0,0ti,omap2-onenand “Udt†–¦B·uƒ`•`§¶ É Éë`×Ü` rrúZå ÿ0H=+Zd.à+  disabledethernet@gpmcsmsc,lan9221smsc,lan9115_·uƒ*•$§¶ É Éë*×Ü$ <6ú$åÿ=+*j„ž ® ¼Ézdefaultˆ  “ÿ îusb_otg_hs@480ab000ti,omap3-musb“H °î\]/mcdma ùusb_otg_hsßêò û  usb2-phyü 2dss@48050000 ti,omap3-dss“H okay ùdss_core—¸žfck+dispc@48050400ti,omap3-dispc“Hî ùdss_dispc—¸žfckencoder@4804fc00 ti,omap3-dsi“HüHþ@Hÿ protophypllî  disabled ùdss_dsi1—¸· žfcksys_clk+encoder@48050800ti,omap3-rfbi“H  disabled ùdss_rfbi—¸¹žfckickencoder@48050c00ti,omap3-venc“H   disabled ùdss_venc—µ¶žfcktv_dac_clkportendpoint " 2æssi-controller@48058000 ti,omap3-ssiùssi okay“H€H�sysgddîG/gdd_mpu+ —v žssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-port“H H¨txrxîCDssi-port@4805b000ti,omap3-ssi-port“H°H¸txrxîEFserial@49042000ti,omap3-uart“I îP8QR=txrxùuart4GÜlregulator-abb-mpu ti,abb-v1 ­abb_mpu_iva+“H0rðH0hbase-addressint-address =—# V g` wsO€7Èûæpinmux@480025a0 ti,omap3-padconfpinctrl-single“H% \+ *?]ÿzdefaultˆpinmux_hsusbb1_pins`’:8L N < > @ B D F H J æpinmux_leds_pins’TVXæpinmux_mmc1_cd_pins’Zæõisp@480bc000 ti,omap3-isp“H ÀüH Øî ƒ¦ð Šìports+bandgap@48002524“H%$ti,omap36xx-bandgap –ætarget-module@480cb000ti,sysc-omap3630-srti,syscùsmartreflex_core“H °8sysc —žfck+ H °smartreflex@0ti,omap3-smartreflex-core“îtarget-module@480c9000ti,sysc-omap3630-srti,syscùsmartreflex_mpu_iva“H �8sysc —žfck+ H �smartreflex@480c9000ti,omap3-smartreflex-mpu-iva“îtarget-module@50000000ti,sysc-omap4ti,sysc“PþPþ revsysc " —äžfckick+ Popp-tableoperating-points-v2-ti-cpu¦æopp50-300000000 ¬á£ ³ssssss Áÿÿÿÿ Òopp100-600000000 ¬#ÃF ³O€O€O€O€O€O€ Áÿÿÿÿopp130-800000000 ¬/¯ ³7È7È7È7È7È7È Áÿÿÿÿopp1g-1000000000 ¬;šÊ ³ûûûûûû Áÿÿÿÿ Þopp_supplyti,omap-opp-supply éûthermal-zonescpu_thermal ú è (N  5tripscpu_alert E8€ QÐŽpassiveæcpu_crit E_� QÐ Žcriticalcooling-mapsmap0 \ aÿÿÿÿÿÿÿÿmemory@80000000‡memory“€ soundti,omap-twl4030 pigep2 yregulator-vdd33regulator-fixed­vdd33 ‚regulator-vddvarioregulator-fixed ­vddvario ‚æ regulator-vdd33aregulator-fixed­vdd33a ‚æ ledszdefaultˆ gpio-ledsboot –omap3:green:boot ãù œonuser0 –omap3:red:user0 ãù œoffuser1 –omap3:red:user1 ãù œoffuser2 –omap3:green:user1 ãøhsusb1_power_regregulator-fixed ­hsusb1_vbus¼2Z Ô2Z  ªø ¯pæhsusb1_phyusb-nop-xceiv Àù Ìæencoder ti,tfp410 × ports+port@0“endpoint "æport@1“endpoint "æ!connectordvi-connector –dvi ç ï portendpoint "!æfixedregulator-mmcsdioregulator-fixed­vmmcsdio_fixed¼2Z Ô2Z æümmc2_pwrseqmmc-pwrseq-simple À" " æý compatibleinterrupt-parent#address-cells#size-cellsmodelstdout-pathi2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-points-v2vbb-supply#cooling-cellsphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-widthcd-gpioswp-gpiosmmc-pwrseqnon-removablestatus#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport1-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nsgpmc,sync-readgpmc,sync-writegpmc,burst-lengthgpmc,burst-wrapgpmc,burst-readgpmc,burst-writegpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsbank-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modeti,absolute-max-voltage-uvpolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-deviceti,modelti,mcbspregulator-always-onlabeldefault-stategpiostartup-delay-usreset-gpiosvcc-supplypowerdown-gpiosdigitalddc-i2c-bus