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#address-cells#size-cellsinterrupt-parentmodelcompatiblerangesregphandleclocksclock-names#clock-cells#reset-cells#power-domain-cellsamlogic,ao-sysctrlresetsreset-namesassigned-clocksassigned-clock-ratesinterruptsstatus#pwm-cellspinctrl-0pinctrl-names#io-channel-cellsamlogic,hhi-sysctrlnvmem-cellsnvmem-cell-namesvref-supply#phy-cellsbus-widthno-sdiocap-mmc-highspeedcap-sd-highspeeddisable-wpcd-gpiosvmmc-supplyvqmmc-supplymax-frequencymmc-hs200-1_8vmmc-pwrseqinterrupt-controller#interrupt-cellsamlogic,channel-interruptsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namesgroupsfunctionbias-disablebias-pull-upcache-unifiedcache-levelarm,data-latencyarm,tag-latencyarm,filter-rangesprefetch-dataprefetch-instrarm,shared-overridevdd-supplygpio-hogoutput-highline-namephysphy-namesg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-sizedr_modeinterrupt-namesrx-fifo-depthtx-fifo-depthpower-domainsphy-handlephy-modereset-assert-usreset-deassert-usreset-gpiosclock-frequencyclock-output-namesdevice_typenext-level-cacheenable-methodoperating-points-v2cpu-supplyopp-sharedopp-hzopp-microvoltturbo-modeinterrupt-affinityno-mapmali-supplyserial0mmc0mmc1stdout-pathlabellinux,default-triggerdefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltvin-supplygpioenable-active-highgpios-statesio-channelspwm-supplypwmspwm-dutycycle-rangeregulator-boot-onregulator-always-on