Ð þí ß8ô( ë¼2logicpd,dm3730-som-lv-devkitti,omap3630ti,omap3 ++7LogicPD Zoom DM3730 SOM-LV Development Kitchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000s/ocp@68000000/serial@49042000 {/displaycpus+cpu@0arm,cortex-a8„cpu�”›cpu§“àµÉÔãï pmu@54000000arm,cortex-a8-pmu�T€÷debugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus�h÷ + l3_mainl4@48000000ti,omap3-l4-coresimple-bus+  Hscm@2000ti,omap3-scmsimple-bus� +  pinmux@30 ti,omap3-padconfpinctrl-single�08+"3Hfÿƒdefault‘ïépinmux_mm3_pins0›468: ¢ïþpinmux_mcbsp2_pins › ïpinmux_uart2_pins(›DFHJhïêpinmux_mcspi1_pins ›˜šœžïùpinmux_hsusb2_pins0›¤ ¦ ¨ ª ¬ ® ïpinmux_hsusb_otg_pins`›rtvxz|~€‚„†ˆïpinmux_i2c1_pins›ŠŒŠïëpinmux_i2c2_pins›Ž�ïôpinmux_i2c3_pins›’”ïõpinmux_tsc2004_pins›Vï÷pinmux_twl4030_pins›°Aïípinmux_gpio_key_pins›þï"pinmux_led_pins›.ï$pinmux_lan9221_pins›Tïpinmux_mmc1_pins@›üïûpinmux_lcd_enable_pin›Zï&pinmux_dss_dpi_pins1 ›¤¦¨ª¬®°²´¶¸º¼¾ÀÂÄÆÈÊïscm_conf@270sysconsimple-bus�p0+  p0ïpbias_regulator@2b0ti,pbias-omap3ti,pbias-omap�°¯pbias_mmc_omap2430¶pbias_mmc_omap2430Åw@Ý-ÆÀïúclocks+mcbsp5_mux_fck@68õti,composite-mux-clock” �hï mcbsp5_fckõti,composite-clock” ïmcbsp1_mux_fck@4õti,composite-mux-clock” �ï mcbsp1_fckõti,composite-clock” ïmcbsp2_mux_fck@4õti,composite-mux-clock” �ïmcbsp2_fckõti,composite-clock”ïmcbsp3_mux_fck@68õti,composite-mux-clock” �hïmcbsp3_fckõti,composite-clock”ïmcbsp4_mux_fck@68õti,composite-mux-clock” �hïmcbsp4_fckõti,composite-clock”ïclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single� \+"3Hfÿƒdefault‘pinmux_hsusb1_reset_pin›ïpinmux_wl127x_gpio_pin›  ïÿpinmux_twl4030_vpins ›ïîpinmux_led_pins_wkup›$ï%pinmux_backlight_pins›ï)target-module@480a6000ti,sysc-omap2ti,sysc�H `DH `HH `Lrevsyscsyss &4”›ick+  H ` aes1@0 ti,omap3-aes�P÷A  Ftxrxtarget-module@480c5000ti,sysc-omap2ti,sysc�H PDH PHH PLrevsyscsyss &4”›ick+  H P aes2@0 ti,omap3-aes�P÷AABFtxrxprm@48306000 ti,omap3-prm�H0`@÷ clocks+virt_16_8m_ckõ fixed-clockPYïosc_sys_ck@d40õ ti,mux-clock”� @ïsys_ck@1270õti,divider-clock”`�pkï$sys_clkout1@d70õti,gate-clock”� pdpll3_x2_ckõfixed-factor-clock” ‚�dpll3_m2x2_ckõfixed-factor-clock”!‚�ï#dpll4_x2_ckõfixed-factor-clock”"‚�corex2_fckõfixed-factor-clock”#‚�ï%wkup_l4_ickõfixed-factor-clock”$‚�ïTcorex2_d3_fckõfixed-factor-clock”%‚�ï‹corex2_d5_fckõfixed-factor-clock”%‚�ïŒclockdomainscm@48004000 ti,omap3-cm�H@@clocks+dummy_apb_pclkõ fixed-clockPomap_32k_fckõ fixed-clockP€ïFvirt_12m_ckõ fixed-clockP·ïvirt_13m_ckõ fixed-clockPÆ]@ïvirt_19200000_ckõ fixed-clockP$øïvirt_26000000_ckõ fixed-clockPŒº€ïvirt_38_4m_ckõ fixed-clockPIðïdpll4_ck@d00õti,omap3-dpll-per-j-type-clock”$$� D 0ï"dpll4_m2_ck@d48õti,divider-clock”"`?� Hkï&dpll4_m2x2_mul_ckõfixed-factor-clock”&‚�ï'dpll4_m2x2_ck@d00õti,hsdiv-gate-clock”'� —ï(omap_96m_alwon_fckõfixed-factor-clock”(‚�ï/dpll3_ck@d00õti,omap3-dpll-core-clock”$$� @ 0ï dpll3_m3_ck@1140õti,divider-clock” `�@kï)dpll3_m3x2_mul_ckõfixed-factor-clock”)‚�ï*dpll3_m3x2_ck@d00õti,hsdiv-gate-clock”* � —ï+emu_core_alwon_ckõfixed-factor-clock”+‚�ïhsys_altclkõ fixed-clockPï4mcbsp_clksõ fixed-clockPï dpll3_m2_ck@d40õti,divider-clock” `� @kï!core_ckõfixed-factor-clock”!‚�ï,dpll1_fck@940õti,divider-clock”,`� @kï-dpll1_ck@904õti,omap3-dpll-clock”$-�  $ @ 4ïdpll1_x2_ckõfixed-factor-clock”‚�ï.dpll1_x2m2_ck@944õti,divider-clock”.`� DkïBcm_96m_fckõfixed-factor-clock”/‚�ï0omap_96m_fck@d40õ ti,mux-clock”0$� @ïKdpll4_m3_ck@e40õti,divider-clock”"` �@kï1dpll4_m3x2_mul_ckõfixed-factor-clock”1‚�ï2dpll4_m3x2_ck@d00õti,hsdiv-gate-clock”2� —ï3omap_54m_fck@d40õ ti,mux-clock”34� @ï>cm_96m_d2_fckõfixed-factor-clock”0‚�ï5omap_48m_fck@d40õ ti,mux-clock”54� @ï6omap_12m_fckõfixed-factor-clock”6‚�ïMdpll4_m4_ck@e40õti,divider-clock”"`�@kï7dpll4_m4x2_mul_ckõti,fixed-factor-clock”7­»Èï8dpll4_m4x2_ck@d00õti,gate-clock”8� —Èï�dpll4_m5_ck@f40õti,divider-clock”"`?�@kï9dpll4_m5x2_mul_ckõti,fixed-factor-clock”9­»Èï:dpll4_m5x2_ck@d00õti,hsdiv-gate-clock”:� —Èïpdpll4_m6_ck@1140õti,divider-clock”"`?�@kï;dpll4_m6x2_mul_ckõfixed-factor-clock”;‚�ï<dpll4_m6x2_ck@d00õti,hsdiv-gate-clock”<� —ï=emu_per_alwon_ckõfixed-factor-clock”=‚�ïiclkout2_src_gate_ck@d70õ ti,composite-no-wait-gate-clock”,� pï?clkout2_src_mux_ck@d70õti,composite-mux-clock”,$0>� pï@clkout2_src_ckõti,composite-clock”?@ïAsys_clkout2@d70õti,divider-clock”A`@� pÛmpu_ckõfixed-factor-clock”B‚�ïCarm_fck@924õti,divider-clock”C� $`emu_mpu_alwon_ckõfixed-factor-clock”C‚�ïjl3_ick@a40õti,divider-clock”,`� @kïDl4_ick@a40õti,divider-clock”D`� @kïErm_ick@c40õti,divider-clock”E`� @kgpt10_gate_fck@a00õti,composite-gate-clock”$ � ïGgpt10_mux_fck@a40õti,composite-mux-clock”F$� @ïHgpt10_fckõti,composite-clock”GHgpt11_gate_fck@a00õti,composite-gate-clock”$ � ïIgpt11_mux_fck@a40õti,composite-mux-clock”F$� @ïJgpt11_fckõti,composite-clock”IJcore_96m_fckõfixed-factor-clock”K‚�ïmmchs2_fck@a00õti,wait-gate-clock”� ï»mmchs1_fck@a00õti,wait-gate-clock”� ï¼i2c3_fck@a00õti,wait-gate-clock”� ï½i2c2_fck@a00õti,wait-gate-clock”� ï¾i2c1_fck@a00õti,wait-gate-clock”� ï¿mcbsp5_gate_fck@a00õti,composite-gate-clock”  � ï mcbsp1_gate_fck@a00õti,composite-gate-clock”  � ï core_48m_fckõfixed-factor-clock”6‚�ïLmcspi4_fck@a00õti,wait-gate-clock”L� ïÀmcspi3_fck@a00õti,wait-gate-clock”L� ïÁmcspi2_fck@a00õti,wait-gate-clock”L� ïÂmcspi1_fck@a00õti,wait-gate-clock”L� ïÃuart2_fck@a00õti,wait-gate-clock”L� ïÄuart1_fck@a00õti,wait-gate-clock”L�  ïÅcore_12m_fckõfixed-factor-clock”M‚�ïNhdq_fck@a00õti,wait-gate-clock”N� ïÆcore_l3_ickõfixed-factor-clock”D‚�ïOsdrc_ick@a10õti,wait-gate-clock”O� ï�gpmc_fckõfixed-factor-clock”O‚�core_l4_ickõfixed-factor-clock”E‚�ïPmmchs2_ick@a10õti,omap3-interface-clock”P� ïÇmmchs1_ick@a10õti,omap3-interface-clock”P� ïÈhdq_ick@a10õti,omap3-interface-clock”P� ïÉmcspi4_ick@a10õti,omap3-interface-clock”P� ïÊmcspi3_ick@a10õti,omap3-interface-clock”P� ïËmcspi2_ick@a10õti,omap3-interface-clock”P� ïÌmcspi1_ick@a10õti,omap3-interface-clock”P� ïÍi2c3_ick@a10õti,omap3-interface-clock”P� ïÎi2c2_ick@a10õti,omap3-interface-clock”P� ïÏi2c1_ick@a10õti,omap3-interface-clock”P� ïÐuart2_ick@a10õti,omap3-interface-clock”P� ïÑuart1_ick@a10õti,omap3-interface-clock”P�  ïÒgpt11_ick@a10õti,omap3-interface-clock”P�  ïÓgpt10_ick@a10õti,omap3-interface-clock”P�  ïÔmcbsp5_ick@a10õti,omap3-interface-clock”P�  ïÕmcbsp1_ick@a10õti,omap3-interface-clock”P�  ïÖomapctrl_ick@a10õti,omap3-interface-clock”P� ï×dss_tv_fck@e00õti,gate-clock”>�ï¶dss_96m_fck@e00õti,gate-clock”K�ï·dss2_alwon_fck@e00õti,gate-clock”$�ï¸dummy_ckõ fixed-clockPgpt1_gate_fck@c00õti,composite-gate-clock”$� ïQgpt1_mux_fck@c40õti,composite-mux-clock”F$� @ïRgpt1_fckõti,composite-clock”QRï aes2_ick@a10õti,omap3-interface-clock”P� ïwkup_32k_fckõfixed-factor-clock”F‚�ïSgpio1_dbck@c00õti,gate-clock”S� ï­sha12_ick@a10õti,omap3-interface-clock”P� ïØwdt2_fck@c00õti,wait-gate-clock”S� ï®wdt2_ick@c10õti,omap3-interface-clock”T� ï¯wdt1_ick@c10õti,omap3-interface-clock”T� ï°gpio1_ick@c10õti,omap3-interface-clock”T� ï±omap_32ksync_ick@c10õti,omap3-interface-clock”T� ï²gpt12_ick@c10õti,omap3-interface-clock”T� ï³gpt1_ick@c10õti,omap3-interface-clock”T� ï´per_96m_fckõfixed-factor-clock”/‚�ïper_48m_fckõfixed-factor-clock”6‚�ïUuart3_fck@1000õti,wait-gate-clock”U� ï’gpt2_gate_fck@1000õti,composite-gate-clock”$�ïVgpt2_mux_fck@1040õti,composite-mux-clock”F$�@ïWgpt2_fckõti,composite-clock”VWï gpt3_gate_fck@1000õti,composite-gate-clock”$�ïXgpt3_mux_fck@1040õti,composite-mux-clock”F$�@ïYgpt3_fckõti,composite-clock”XYgpt4_gate_fck@1000õti,composite-gate-clock”$�ïZgpt4_mux_fck@1040õti,composite-mux-clock”F$�@ï[gpt4_fckõti,composite-clock”Z[gpt5_gate_fck@1000õti,composite-gate-clock”$�ï\gpt5_mux_fck@1040õti,composite-mux-clock”F$�@ï]gpt5_fckõti,composite-clock”\]gpt6_gate_fck@1000õti,composite-gate-clock”$�ï^gpt6_mux_fck@1040õti,composite-mux-clock”F$�@ï_gpt6_fckõti,composite-clock”^_gpt7_gate_fck@1000õti,composite-gate-clock”$�ï`gpt7_mux_fck@1040õti,composite-mux-clock”F$�@ïagpt7_fckõti,composite-clock”`agpt8_gate_fck@1000õti,composite-gate-clock”$ �ïbgpt8_mux_fck@1040õti,composite-mux-clock”F$�@ïcgpt8_fckõti,composite-clock”bcgpt9_gate_fck@1000õti,composite-gate-clock”$ �ïdgpt9_mux_fck@1040õti,composite-mux-clock”F$�@ïegpt9_fckõti,composite-clock”deper_32k_alwon_fckõfixed-factor-clock”F‚�ïfgpio6_dbck@1000õti,gate-clock”f�ï“gpio5_dbck@1000õti,gate-clock”f�ï”gpio4_dbck@1000õti,gate-clock”f�ï•gpio3_dbck@1000õti,gate-clock”f�ï–gpio2_dbck@1000õti,gate-clock”f� ï—wdt3_fck@1000õti,wait-gate-clock”f� ï˜per_l4_ickõfixed-factor-clock”E‚�ïggpio6_ick@1010õti,omap3-interface-clock”g�ï™gpio5_ick@1010õti,omap3-interface-clock”g�ïšgpio4_ick@1010õti,omap3-interface-clock”g�ï›gpio3_ick@1010õti,omap3-interface-clock”g�ïœgpio2_ick@1010õti,omap3-interface-clock”g� ï�wdt3_ick@1010õti,omap3-interface-clock”g� ïžuart3_ick@1010õti,omap3-interface-clock”g� ïŸuart4_ick@1010õti,omap3-interface-clock”g�ï gpt9_ick@1010õti,omap3-interface-clock”g� ï¡gpt8_ick@1010õti,omap3-interface-clock”g� ï¢gpt7_ick@1010õti,omap3-interface-clock”g�ï£gpt6_ick@1010õti,omap3-interface-clock”g�ï¤gpt5_ick@1010õti,omap3-interface-clock”g�ï¥gpt4_ick@1010õti,omap3-interface-clock”g�ï¦gpt3_ick@1010õti,omap3-interface-clock”g�ï§gpt2_ick@1010õti,omap3-interface-clock”g�ï¨mcbsp2_ick@1010õti,omap3-interface-clock”g�ï©mcbsp3_ick@1010õti,omap3-interface-clock”g�ïªmcbsp4_ick@1010õti,omap3-interface-clock”g�ï«mcbsp2_gate_fck@1000õti,composite-gate-clock” �ïmcbsp3_gate_fck@1000õti,composite-gate-clock” �ïmcbsp4_gate_fck@1000õti,composite-gate-clock” �ïemu_src_mux_ck@1140õ ti,mux-clock”$hij�@ïkemu_src_ckõti,clkdm-gate-clock”kïlpclk_fck@1140õti,divider-clock”l`�@kpclkx2_fck@1140õti,divider-clock”l`�@katclk_fck@1140õti,divider-clock”l`�@ktraceclk_src_fck@1140õ ti,mux-clock”$hij�@ïmtraceclk_fck@1140õti,divider-clock”m `�@ksecure_32k_fckõ fixed-clockP€ïngpt12_fckõfixed-factor-clock”n‚�ï wdt1_fckõfixed-factor-clock”n‚�security_l4_ick2õfixed-factor-clock”E‚�ïoaes1_ick@a14õti,omap3-interface-clock”o� ïrng_ick@a14õti,omap3-interface-clock”o� ïsha11_ick@a14õti,omap3-interface-clock”o� des1_ick@a14õti,omap3-interface-clock”o� cam_mclk@f00õti,gate-clock”p�Ècam_ick@f10õ!ti,omap3-no-wait-interface-clock”E�ïßcsi2_96m_fck@f00õti,gate-clock”�ïàsecurity_l3_ickõfixed-factor-clock”D‚�ïqpka_ick@a14õti,omap3-interface-clock”q� icr_ick@a10õti,omap3-interface-clock”P� des2_ick@a10õti,omap3-interface-clock”P� mspro_ick@a10õti,omap3-interface-clock”P� mailboxes_ick@a10õti,omap3-interface-clock”P� ssi_l4_ickõfixed-factor-clock”E‚�ïxsr1_fck@c00õti,wait-gate-clock”$� ïsr2_fck@c00õti,wait-gate-clock”$� ïsr_l4_ickõfixed-factor-clock”E‚�dpll2_fck@40õti,divider-clock”,`�@kïrdpll2_ck@4õti,omap3-dpll-clock”$r�$@4ñ ïsdpll2_m2_ck@44õti,divider-clock”s`�Dkïtiva2_ck@0õti,wait-gate-clock”t�ïámodem_fck@a00õti,omap3-interface-clock”$� ïâsad2d_ick@a10õti,omap3-interface-clock”D� ïãmad2d_ick@a18õti,omap3-interface-clock”D� ïämspro_fck@a00õti,wait-gate-clock”� ssi_ssr_gate_fck_3430es2@a00õ ti,composite-no-wait-gate-clock”%� ïussi_ssr_div_fck_3430es2@a40õti,composite-divider-clock”%� @$ïvssi_ssr_fck_3430es2õti,composite-clock”uvïwssi_sst_fck_3430es2õfixed-factor-clock”w‚�ïhsotgusb_ick_3430es2@a10õ"ti,omap3-hsotgusb-interface-clock”O� ï‘ssi_ick_3430es2@a10õti,omap3-ssi-interface-clock”x� ïusim_gate_fck@c00õti,composite-gate-clock”K � ïƒsys_d2_ckõfixed-factor-clock”$‚�ïzomap_96m_d2_fckõfixed-factor-clock”K‚�ï{omap_96m_d4_fckõfixed-factor-clock”K‚�ï|omap_96m_d8_fckõfixed-factor-clock”K‚�ï}omap_96m_d10_fckõfixed-factor-clock”K‚� ï~dpll5_m2_d4_ckõfixed-factor-clock”y‚�ïdpll5_m2_d8_ckõfixed-factor-clock”y‚�ï€dpll5_m2_d16_ckõfixed-factor-clock”y‚�ï�dpll5_m2_d20_ckõfixed-factor-clock”y‚�ï‚usim_mux_fck@c40õti,composite-mux-clock(”$z{|}~€�‚� @kï„usim_fckõti,composite-clock”ƒ„usim_ick@c10õti,omap3-interface-clock”T�  ïµdpll5_ck@d04õti,omap3-dpll-clock”$$�  $ L 4ñï…dpll5_m2_ck@d50õti,divider-clock”…`� Pkïysgx_gate_fck@b00õti,composite-gate-clock”,� ï�core_d3_ckõfixed-factor-clock”,‚�ï†core_d4_ckõfixed-factor-clock”,‚�ï‡core_d6_ckõfixed-factor-clock”,‚�ïˆomap_192m_alwon_fckõfixed-factor-clock”(‚�ï‰core_d2_ckõfixed-factor-clock”,‚�ïŠsgx_mux_fck@b40õti,composite-mux-clock ”†‡ˆ0‰Š‹Œ� @ïŽsgx_fckõti,composite-clock”�Žïsgx_ick@b10õti,wait-gate-clock”D� ïåcpefuse_fck@a08õti,gate-clock”$� ïÙts_fck@a08õti,gate-clock”F� ïÚusbtll_fck@a08õti,wait-gate-clock”y� ïÛusbtll_ick@a18õti,omap3-interface-clock”P� ïÜmmchs3_ick@a10õti,omap3-interface-clock”P� ïÝmmchs3_fck@a00õti,wait-gate-clock”� ïÞdss1_alwon_fck_3430es2@e00õti,dss-gate-clock”��Èï¹dss_ick_3430es2@e10õti,omap3-dss-interface-clock”E�ïºusbhost_120m_fck@1400õti,gate-clock”y�ïæusbhost_48m_fck@1400õti,dss-gate-clock”6�ïçusbhost_ick@1410õti,omap3-dss-interface-clock”E�ïèuart4_fck@1000õti,wait-gate-clock”U�ï¬clockdomainscore_l3_clkdmti,clockdomain”�‘dpll3_clkdmti,clockdomain” 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2serial3display0device_typeregclocksclock-namesclock-latencyoperating-points-v2vbb-supply#cooling-cellscpu0-supplyphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedti,hs_extmute_gpiobci3v1-supplyio-channelsio-channel-namesti,bb-uvoltti,bb-uampregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsti,use_poweroffvio-supplytouchscreen-fuzz-xtouchscreen-fuzz-ytouchscreen-fuzz-pressuretouchscreen-size-xtouchscreen-size-ytouchscreen-max-pressureti,x-plate-ohmsti,esd-recovery-timeout-ms#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplywp-gpioscd-gpiosvmmc-supplybus-widthcap-power-off-cardnon-removableref-clock-frequency#iommu-cellsti,#tlb-entriesstatusinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthti,nand-ecc-optrb-gpiosgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nsgpmc,device-widthbank-widthgpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowervdds_dsi-supplyvdda_video-supplyremote-endpointdata-linesti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modeti,absolute-max-voltage-uvpolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicestartup-delay-usenable-active-highvin-supplyreset-gpioslabellinux,codewakeup-sourceti,modelti,mcbsplinux,default-triggerbacklightenable-gpiospwmsbrightness-levelsdefault-brightness-level