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#address-cells#size-cellsmodelcompatiblegpio0gpio1serial0serial1ethernet1ethernet2ethernet3i2c0i2c1interrupts-extendedcontrollerinterrupt-parentpcie-mem-aperturepcie-io-aperturerangesregclocksstatuscache-unifiedcache-levelarm,double-linefill-incrarm,double-linefill-wraparm,double-linefillprefetch-datainterrupts#interrupt-cellsinterrupt-controllerphandlepinctrl-0pinctrl-namesreg-shiftreg-io-widthmarvell,pinsmarvell,functionreg-namesngpiosgpio-controller#gpio-cells#pwm-cellsgpio-hogoutput-lowline-name#clock-cells#phy-cellsmsi-controllerclock-namestx-csum-limitphyphy-modebuffer-managerbm,pool-longbm,pool-shortphysspeedfull-duplexmanagedsfpdmacap,memcpydmacap,xordmacap,memsetmarvell,reg-initreset-gpioslabelphy-handleethernetmarvell,crypto-sramsmarvell,crypto-sram-sizeinternal-memclock-output-namesmrvl,clk-delay-cyclesbus-widthno-1-8-vnon-removablevmmcwp-invertedvbus-supplyno-memory-wccell-indexspi-max-frequencydevice_typemsi-parentbus-rangeassigned-addressesinterrupt-map-maskinterrupt-mapmarvell,pcie-portmarvell,pcie-laneclock-frequencyenable-methodstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-ongpiovin-supplyregulator-boot-oni2c-buslos-gpiomod-def0-gpiotx-disable-gpiolinux,can-disablelinux,codecolor