Ð þíàÕ8Û$(±Úì%teejet,mt_ventouxti,am3517ti,omap3 +7TeeJet Mt.Ventouxchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000cpus+cpu@0arm,cortex-a8scpuƒŠcpu–“सÇöpmu@54000000arm,cortex-a8-pmuT€ÏÚdebugsssocti,omap-inframpu ti,omap3-mpuÚmpuiva ti,iva2.2Úiva ädisableddsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bushÏ +ëÚl3_mainl4@48000000ti,omap3-l4-coresimple-bus+ ëHscm@2000ti,omap3-scmsimple-bus + ë pinmux@30 ti,omap3-padconfpinctrl-single08+ò'Eÿscm_conf@270sysconsimple-busp0+ ëp0Çpbias_regulator@2b0ti,pbias-omap3ti,pbias-omap°bpbias_mmc_omap2430ipbias_mmc_omap2430xw@�-ÆÀÇäclocks+mcbsp5_mux_fck@68¨ti,composite-mux-clockƒµhÇmcbsp5_fck¨ti,composite-clockƒÇêmcbsp1_mux_fck@4¨ti,composite-mux-clockƒµÇ mcbsp1_fck¨ti,composite-clockƒ Çåmcbsp2_mux_fck@4¨ti,composite-mux-clockƒ µÇ mcbsp2_fck¨ti,composite-clockƒ Ççmcbsp3_mux_fck@68¨ti,composite-mux-clockƒ hÇmcbsp3_fck¨ti,composite-clockƒÇèmcbsp4_mux_fck@68¨ti,composite-mux-clockƒ µhÇmcbsp4_fck¨ti,composite-clockƒÇéclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+ò'Eÿtarget-module@480a6000ti,sysc-omap2ti,syscH `DH `HH `LÂrevsyscsyssÌ Ù烊ick+ ëH ` aes1@0 ti,omap3-aesPÏô  ùtxrxtarget-module@480c5000ti,sysc-omap2ti,syscH PDH PHH PLÂrevsyscsyssÌ Ù烊ick+ ëH P aes2@0 ti,omap3-aesPÏôABùtxrxprm@48306000 ti,omap3-prmH0`@Ï clocks+virt_16_8m_ck¨ fixed-clockYÇosc_sys_ck@d40¨ ti,mux-clockƒ @Çsys_ck@1270¨ti,divider-clockƒµpÇ sys_clkout1@d70¨ti,gate-clockƒ pµdpll3_x2_ck¨fixed-factor-clockƒ5@dpll3_m2x2_ck¨fixed-factor-clockƒ5@Çdpll4_x2_ck¨fixed-factor-clockƒ5@corex2_fck¨fixed-factor-clockƒ5@Ç!wkup_l4_ick¨fixed-factor-clockƒ 5@ÇPcorex2_d3_fck¨fixed-factor-clockƒ!5@LJcorex2_d5_fck¨fixed-factor-clockƒ!5@Ljclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk¨ fixed-clockomap_32k_fck¨ fixed-clock€ÇBvirt_12m_ck¨ fixed-clock·Çvirt_13m_ck¨ fixed-clockÆ]@Çvirt_19200000_ck¨ fixed-clock$øÇvirt_26000000_ck¨ fixed-clockŒº€Çvirt_38_4m_ck¨ fixed-clockIðÇdpll4_ck@d00¨ti,omap3-dpll-per-clockƒ  D 0Çdpll4_m2_ck@d48¨ti,divider-clockƒ? HÇ"dpll4_m2x2_mul_ck¨fixed-factor-clockƒ"5@Ç#dpll4_m2x2_ck@d00¨ti,gate-clockƒ#µ JÇ$omap_96m_alwon_fck¨fixed-factor-clockƒ$5@Ç+dpll3_ck@d00¨ti,omap3-dpll-core-clockƒ  @ 0Çdpll3_m3_ck@1140¨ti,divider-clockƒµ@Ç%dpll3_m3x2_mul_ck¨fixed-factor-clockƒ%5@Ç&dpll3_m3x2_ck@d00¨ti,gate-clockƒ&µ  JÇ'emu_core_alwon_ck¨fixed-factor-clockƒ'5@Çdsys_altclk¨ fixed-clockÇ0mcbsp_clks¨ fixed-clockÇdpll3_m2_ck@d40¨ti,divider-clockƒµ @Çcore_ck¨fixed-factor-clockƒ5@Ç(dpll1_fck@940¨ti,divider-clockƒ(µ @Ç)dpll1_ck@904¨ti,omap3-dpll-clockƒ )  $ @ 4Çdpll1_x2_ck¨fixed-factor-clockƒ5@Ç*dpll1_x2m2_ck@944¨ti,divider-clockƒ* DÇ>cm_96m_fck¨fixed-factor-clockƒ+5@Ç,omap_96m_fck@d40¨ ti,mux-clockƒ, µ @ÇGdpll4_m3_ck@e40¨ti,divider-clockƒµ @Ç-dpll4_m3x2_mul_ck¨fixed-factor-clockƒ-5@Ç.dpll4_m3x2_ck@d00¨ti,gate-clockƒ.µ JÇ/omap_54m_fck@d40¨ ti,mux-clockƒ/0µ @Ç:cm_96m_d2_fck¨fixed-factor-clockƒ,5@Ç1omap_48m_fck@d40¨ ti,mux-clockƒ10µ @Ç2omap_12m_fck¨fixed-factor-clockƒ25@ÇIdpll4_m4_ck@e40¨ti,divider-clockƒ@Ç3dpll4_m4x2_mul_ck¨ti,fixed-factor-clockƒ3`n{Ç4dpll4_m4x2_ck@d00¨ti,gate-clockƒ4µ J{Ç‹dpll4_m5_ck@f40¨ti,divider-clockƒ?@Ç5dpll4_m5x2_mul_ck¨ti,fixed-factor-clockƒ5`n{Ç6dpll4_m5x2_ck@d00¨ti,gate-clockƒ6µ J{Çldpll4_m6_ck@1140¨ti,divider-clockƒµ?@Ç7dpll4_m6x2_mul_ck¨fixed-factor-clockƒ75@Ç8dpll4_m6x2_ck@d00¨ti,gate-clockƒ8µ JÇ9emu_per_alwon_ck¨fixed-factor-clockƒ95@Çeclkout2_src_gate_ck@d70¨ ti,composite-no-wait-gate-clockƒ(µ pÇ;clkout2_src_mux_ck@d70¨ti,composite-mux-clockƒ( ,: pÇ<clkout2_src_ck¨ti,composite-clockƒ;<Ç=sys_clkout2@d70¨ti,divider-clockƒ=µ@ pŽmpu_ck¨fixed-factor-clockƒ>5@Ç?arm_fck@924¨ti,divider-clockƒ? $emu_mpu_alwon_ck¨fixed-factor-clockƒ?5@Çfl3_ick@a40¨ti,divider-clockƒ( @Ç@l4_ick@a40¨ti,divider-clockƒ@µ @ÇArm_ick@c40¨ti,divider-clockƒAµ @gpt10_gate_fck@a00¨ti,composite-gate-clockƒ µ  ÇCgpt10_mux_fck@a40¨ti,composite-mux-clockƒB µ @ÇDgpt10_fck¨ti,composite-clockƒCDgpt11_gate_fck@a00¨ti,composite-gate-clockƒ µ  ÇEgpt11_mux_fck@a40¨ti,composite-mux-clockƒB µ @ÇFgpt11_fck¨ti,composite-clockƒEFcore_96m_fck¨fixed-factor-clockƒG5@Çmmchs2_fck@a00¨ti,wait-gate-clockƒ µǶmmchs1_fck@a00¨ti,wait-gate-clockƒ µÇ·i2c3_fck@a00¨ti,wait-gate-clockƒ µǸi2c2_fck@a00¨ti,wait-gate-clockƒ µǹi2c1_fck@a00¨ti,wait-gate-clockƒ µǺmcbsp5_gate_fck@a00¨ti,composite-gate-clockƒµ  Çmcbsp1_gate_fck@a00¨ti,composite-gate-clockƒµ  Ç core_48m_fck¨fixed-factor-clockƒ25@ÇHmcspi4_fck@a00¨ti,wait-gate-clockƒH µÇ»mcspi3_fck@a00¨ti,wait-gate-clockƒH µǼmcspi2_fck@a00¨ti,wait-gate-clockƒH µǽmcspi1_fck@a00¨ti,wait-gate-clockƒH µǾuart2_fck@a00¨ti,wait-gate-clockƒH µÇ¿uart1_fck@a00¨ti,wait-gate-clockƒH µ ÇÀcore_12m_fck¨fixed-factor-clockƒI5@ÇJhdq_fck@a00¨ti,wait-gate-clockƒJ µÇÁcore_l3_ick¨fixed-factor-clockƒ@5@ÇKsdrc_ick@a10¨ti,wait-gate-clockƒK µÇŒgpmc_fck¨fixed-factor-clockƒK5@core_l4_ick¨fixed-factor-clockƒA5@ÇLmmchs2_ick@a10¨ti,omap3-interface-clockƒL µÇÂmmchs1_ick@a10¨ti,omap3-interface-clockƒL µÇÃhdq_ick@a10¨ti,omap3-interface-clockƒL µÇÄmcspi4_ick@a10¨ti,omap3-interface-clockƒL µÇÅmcspi3_ick@a10¨ti,omap3-interface-clockƒL µÇÆmcspi2_ick@a10¨ti,omap3-interface-clockƒL µÇÇmcspi1_ick@a10¨ti,omap3-interface-clockƒL µÇÈi2c3_ick@a10¨ti,omap3-interface-clockƒL µÇÉi2c2_ick@a10¨ti,omap3-interface-clockƒL µÇÊi2c1_ick@a10¨ti,omap3-interface-clockƒL µÇËuart2_ick@a10¨ti,omap3-interface-clockƒL µÇÌuart1_ick@a10¨ti,omap3-interface-clockƒL µ ÇÍgpt11_ick@a10¨ti,omap3-interface-clockƒL µ ÇÎgpt10_ick@a10¨ti,omap3-interface-clockƒL µ ÇÏmcbsp5_ick@a10¨ti,omap3-interface-clockƒL µ ÇÐmcbsp1_ick@a10¨ti,omap3-interface-clockƒL µ ÇÑomapctrl_ick@a10¨ti,omap3-interface-clockƒL µÇÒdss_tv_fck@e00¨ti,gate-clockƒ:µDZdss_96m_fck@e00¨ti,gate-clockƒGµDzdss2_alwon_fck@e00¨ti,gate-clockƒ µdzdummy_ck¨ fixed-clockgpt1_gate_fck@c00¨ti,composite-gate-clockƒ µ ÇMgpt1_mux_fck@c40¨ti,composite-mux-clockƒB  @ÇNgpt1_fck¨ti,composite-clockƒMNÇëaes2_ick@a10¨ti,omap3-interface-clockƒLµ Çwkup_32k_fck¨fixed-factor-clockƒB5@ÇOgpio1_dbck@c00¨ti,gate-clockƒO µǨsha12_ick@a10¨ti,omap3-interface-clockƒL µÇÓwdt2_fck@c00¨ti,wait-gate-clockƒO µÇ©wdt2_ick@c10¨ti,omap3-interface-clockƒP µǪwdt1_ick@c10¨ti,omap3-interface-clockƒP µÇ«gpio1_ick@c10¨ti,omap3-interface-clockƒP µǬomap_32ksync_ick@c10¨ti,omap3-interface-clockƒP µÇ­gpt12_ick@c10¨ti,omap3-interface-clockƒP µÇ®gpt1_ick@c10¨ti,omap3-interface-clockƒP µǯper_96m_fck¨fixed-factor-clockƒ+5@Ç per_48m_fck¨fixed-factor-clockƒ25@ÇQuart3_fck@1000¨ti,wait-gate-clockƒQµ ÇŽgpt2_gate_fck@1000¨ti,composite-gate-clockƒ µÇRgpt2_mux_fck@1040¨ti,composite-mux-clockƒB @ÇSgpt2_fck¨ti,composite-clockƒRSÇìgpt3_gate_fck@1000¨ti,composite-gate-clockƒ µÇTgpt3_mux_fck@1040¨ti,composite-mux-clockƒB µ@ÇUgpt3_fck¨ti,composite-clockƒTUgpt4_gate_fck@1000¨ti,composite-gate-clockƒ µÇVgpt4_mux_fck@1040¨ti,composite-mux-clockƒB µ@ÇWgpt4_fck¨ti,composite-clockƒVWgpt5_gate_fck@1000¨ti,composite-gate-clockƒ µÇXgpt5_mux_fck@1040¨ti,composite-mux-clockƒB µ@ÇYgpt5_fck¨ti,composite-clockƒXYgpt6_gate_fck@1000¨ti,composite-gate-clockƒ µÇZgpt6_mux_fck@1040¨ti,composite-mux-clockƒB µ@Ç[gpt6_fck¨ti,composite-clockƒZ[gpt7_gate_fck@1000¨ti,composite-gate-clockƒ µÇ\gpt7_mux_fck@1040¨ti,composite-mux-clockƒB µ@Ç]gpt7_fck¨ti,composite-clockƒ\]gpt8_gate_fck@1000¨ti,composite-gate-clockƒ µ Ç^gpt8_mux_fck@1040¨ti,composite-mux-clockƒB µ@Ç_gpt8_fck¨ti,composite-clockƒ^_gpt9_gate_fck@1000¨ti,composite-gate-clockƒ µ Ç`gpt9_mux_fck@1040¨ti,composite-mux-clockƒB µ@Çagpt9_fck¨ti,composite-clockƒ`aper_32k_alwon_fck¨fixed-factor-clockƒB5@Çbgpio6_dbck@1000¨ti,gate-clockƒbµÇ�gpio5_dbck@1000¨ti,gate-clockƒbµÇ�gpio4_dbck@1000¨ti,gate-clockƒbµÇ‘gpio3_dbck@1000¨ti,gate-clockƒbµÇ’gpio2_dbck@1000¨ti,gate-clockƒbµ Ç“wdt3_fck@1000¨ti,wait-gate-clockƒbµ Ç”per_l4_ick¨fixed-factor-clockƒA5@Çcgpio6_ick@1010¨ti,omap3-interface-clockƒcµÇ•gpio5_ick@1010¨ti,omap3-interface-clockƒcµÇ–gpio4_ick@1010¨ti,omap3-interface-clockƒcµÇ—gpio3_ick@1010¨ti,omap3-interface-clockƒcµǘgpio2_ick@1010¨ti,omap3-interface-clockƒcµ Ç™wdt3_ick@1010¨ti,omap3-interface-clockƒcµ Çšuart3_ick@1010¨ti,omap3-interface-clockƒcµ Ç›uart4_ick@1010¨ti,omap3-interface-clockƒcµÇœgpt9_ick@1010¨ti,omap3-interface-clockƒcµ Ç�gpt8_ick@1010¨ti,omap3-interface-clockƒcµ Çžgpt7_ick@1010¨ti,omap3-interface-clockƒcµÇŸgpt6_ick@1010¨ti,omap3-interface-clockƒcµÇ gpt5_ick@1010¨ti,omap3-interface-clockƒcµÇ¡gpt4_ick@1010¨ti,omap3-interface-clockƒcµÇ¢gpt3_ick@1010¨ti,omap3-interface-clockƒcµÇ£gpt2_ick@1010¨ti,omap3-interface-clockƒcµǤmcbsp2_ick@1010¨ti,omap3-interface-clockƒcµÇ¥mcbsp3_ick@1010¨ti,omap3-interface-clockƒcµǦmcbsp4_ick@1010¨ti,omap3-interface-clockƒcµǧmcbsp2_gate_fck@1000¨ti,composite-gate-clockƒµÇ mcbsp3_gate_fck@1000¨ti,composite-gate-clockƒµÇmcbsp4_gate_fck@1000¨ti,composite-gate-clockƒµÇemu_src_mux_ck@1140¨ ti,mux-clockƒ def@Çgemu_src_ck¨ti,clkdm-gate-clockƒgÇhpclk_fck@1140¨ti,divider-clockƒhµ@pclkx2_fck@1140¨ti,divider-clockƒhµ@atclk_fck@1140¨ti,divider-clockƒhµ@traceclk_src_fck@1140¨ ti,mux-clockƒ defµ@Çitraceclk_fck@1140¨ti,divider-clockƒiµ @secure_32k_fck¨ fixed-clock€Çjgpt12_fck¨fixed-factor-clockƒj5@Çíwdt1_fck¨fixed-factor-clockƒj5@security_l4_ick2¨fixed-factor-clockƒA5@Çkaes1_ick@a14¨ti,omap3-interface-clockƒkµ Çrng_ick@a14¨ti,omap3-interface-clockƒk µÇæsha11_ick@a14¨ti,omap3-interface-clockƒk µdes1_ick@a14¨ti,omap3-interface-clockƒk µcam_mclk@f00¨ti,gate-clockƒlµ{cam_ick@f10¨!ti,omap3-no-wait-interface-clockƒAµÇÚcsi2_96m_fck@f00¨ti,gate-clockƒµÇÛsecurity_l3_ick¨fixed-factor-clockƒ@5@Çmpka_ick@a14¨ti,omap3-interface-clockƒm µicr_ick@a10¨ti,omap3-interface-clockƒL µdes2_ick@a10¨ti,omap3-interface-clockƒL µmspro_ick@a10¨ti,omap3-interface-clockƒL µmailboxes_ick@a10¨ti,omap3-interface-clockƒL µssi_l4_ick¨fixed-factor-clockƒA5@Çtsr1_fck@c00¨ti,wait-gate-clockƒ  µÇòsr2_fck@c00¨ti,wait-gate-clockƒ  µÇñsr_l4_ick¨fixed-factor-clockƒA5@dpll2_fck@40¨ti,divider-clockƒ(µ@Çndpll2_ck@4¨ti,omap3-dpll-clockƒ n$@4¤¶¾Çodpll2_m2_ck@44¨ti,divider-clockƒoDÇpiva2_ck@0¨ti,wait-gate-clockƒpµÇÜmodem_fck@a00¨ti,omap3-interface-clockƒ  µÇÝsad2d_ick@a10¨ti,omap3-interface-clockƒ@ µÇÞmad2d_ick@a18¨ti,omap3-interface-clockƒ@ µÇßmspro_fck@a00¨ti,wait-gate-clockƒ µssi_ssr_gate_fck_3430es2@a00¨ ti,composite-no-wait-gate-clockƒ!µ Çqssi_ssr_div_fck_3430es2@a40¨ti,composite-divider-clockƒ!µ @$ÒÇrssi_ssr_fck_3430es2¨ti,composite-clockƒqrÇsssi_sst_fck_3430es2¨fixed-factor-clockƒs5@Çîhsotgusb_ick_3430es2@a10¨"ti,omap3-hsotgusb-interface-clockƒK µÇ�ssi_ick_3430es2@a10¨ti,omap3-ssi-interface-clockƒt µÇïusim_gate_fck@c00¨ti,composite-gate-clockƒGµ  Çsys_d2_ck¨fixed-factor-clockƒ 5@Çvomap_96m_d2_fck¨fixed-factor-clockƒG5@Çwomap_96m_d4_fck¨fixed-factor-clockƒG5@Çxomap_96m_d8_fck¨fixed-factor-clockƒG5@Çyomap_96m_d10_fck¨fixed-factor-clockƒG5@ Çzdpll5_m2_d4_ck¨fixed-factor-clockƒu5@Ç{dpll5_m2_d8_ck¨fixed-factor-clockƒu5@Ç|dpll5_m2_d16_ck¨fixed-factor-clockƒu5@Ç}dpll5_m2_d20_ck¨fixed-factor-clockƒu5@Ç~usim_mux_fck@c40¨ti,composite-mux-clock(ƒ vwxyz{|}~µ @Ç€usim_fck¨ti,composite-clockƒ€usim_ick@c10¨ti,omap3-interface-clockƒP µ ǰdpll5_ck@d04¨ti,omap3-dpll-clockƒ   $ L 4¤¶Ç�dpll5_m2_ck@d50¨ti,divider-clockƒ� PÇusgx_gate_fck@b00¨ti,composite-gate-clockƒ(µ ljcore_d3_ck¨fixed-factor-clockƒ(5@Ç‚core_d4_ck¨fixed-factor-clockƒ(5@ǃcore_d6_ck¨fixed-factor-clockƒ(5@Ç„omap_192m_alwon_fck¨fixed-factor-clockƒ$5@Ç…core_d2_ck¨fixed-factor-clockƒ(5@džsgx_mux_fck@b40¨ti,composite-mux-clock ƒ‚ƒ„,…†‡ˆ @ÇŠsgx_fck¨ti,composite-clockƒ‰ŠÇósgx_ick@b10¨ti,wait-gate-clockƒ@ µÇàcpefuse_fck@a08¨ti,gate-clockƒ  µÇÔts_fck@a08¨ti,gate-clockƒB µÇÕusbtll_fck@a08¨ti,wait-gate-clockƒu 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2device_typeregclocksclock-namesclock-latencyoperating-points-v2#cooling-cellsphandleinterruptsti,hwmodsstatusranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-masksysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extended#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supply#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinsmultipointnum-epsram-bitsiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-device