Ð þí=¥8:Ì(Ù:”7xlnx,zynqmp-zc1275-revAxlnx,zynqmp-zc1275xlnx,zynqmp &ZynqMP ZC1275 RevAcpus cpu@0arm,cortex-a53,cpu8psciFZ^n cpu@1arm,cortex-a53,cpu8psciZF^cpu@2arm,cortex-a53,cpu8psciZF^cpu@3arm,cortex-a53,cpu8psciZF^idle-statesupscicpu-sleep-0arm,idle-state‚@™ª,»XË'Ücpu-opp-tableoperating-points-v2äÜopp00ïG†‹ôöB@¡ opp01ï#ÃEúöB@¡ opp02ï׃üöB@¡ opp03ïá¢ýöB@¡ dccarm,dccokaypmuarm,armv8-pmuv30-��‘’psci arm,psci-0.2?smcfirmwarezynqmp-firmwarexlnx,zynqmp-firmware8?smcÜ zynqmp-powerxlnx,zynqmp-power -#clock-controllerLxlnx,zynqmp-clkn AYpss_ref_clkvideo_clkpss_alt_ref_clkaux_ref_clkgt_crx_ref_clkÜnvmem_firmwarexlnx,zynqmp-nvmem-fw soc_revision@0Zpcapxlnx,zynqmp-pcap-fpgaÜ zynqmp-aesxlnx,zynqmp-aestimerarm,armv8-timer0-   fpga-full fpga-regione  naxi@0 simple-bus nÿÿÿÿinterrupt-controller@f9010000 arm,gic-400u0Zùùùù† - Üaxi simple-bus ncan@ff060000xlnx,zynq-can-1.0 disabled Ycan_clkpclkZÿ -›@©@· /n?can@ff070000xlnx,zynq-can-1.0 disabled Ycan_clkpclkZÿ -›@©@· 0n@cci@fd6e0000 arm,cci-400Zýn�nýn pmu@9000arm,cci-400-pmu,r1Z�P<-{{{{{dma@fd500000 disabledxlnx,zynqmp-dma-1.0ZýP -|Yclk_mainclk_apbÅ€· *ndma@fd510000 disabledxlnx,zynqmp-dma-1.0ZýQ -}Yclk_mainclk_apbÅ€· *ndma@fd520000 disabledxlnx,zynqmp-dma-1.0ZýR -~Yclk_mainclk_apbÅ€· *ndma@fd530000 disabledxlnx,zynqmp-dma-1.0ZýS -Yclk_mainclk_apbÅ€· *ndma@fd540000 disabledxlnx,zynqmp-dma-1.0ZýT -€Yclk_mainclk_apbÅ€· *ndma@fd550000 disabledxlnx,zynqmp-dma-1.0ZýU -�Yclk_mainclk_apbÅ€· *ndma@fd560000 disabledxlnx,zynqmp-dma-1.0ZýV -‚Yclk_mainclk_apbÅ€· *ndma@fd570000 disabledxlnx,zynqmp-dma-1.0ZýW -ƒYclk_mainclk_apbÅ€· *ndma@ffa80000 disabledxlnx,zynqmp-dma-1.0Zÿ¨ -MYclk_mainclk_apbÅ@· +nDdma@ffa90000 disabledxlnx,zynqmp-dma-1.0Zÿ© -NYclk_mainclk_apbÅ@· +nDdma@ffaa0000 disabledxlnx,zynqmp-dma-1.0Zÿª -OYclk_mainclk_apbÅ@· +nDdma@ffab0000 disabledxlnx,zynqmp-dma-1.0Zÿ« -PYclk_mainclk_apbÅ@· +nDdma@ffac0000 disabledxlnx,zynqmp-dma-1.0Zÿ¬ -QYclk_mainclk_apbÅ@· +nDdma@ffad0000 disabledxlnx,zynqmp-dma-1.0Zÿ­ -RYclk_mainclk_apbÅ@· +nDdma@ffae0000 disabledxlnx,zynqmp-dma-1.0Zÿ® -SYclk_mainclk_apbÅ@· +nDdma@ffaf0000 disabledxlnx,zynqmp-dma-1.0Zÿ¯ -TYclk_mainclk_apbÅ@· +nDmemory-controller@fd070000xlnx,zynqmp-ddrc-2.40aZý -pethernet@ff0b0000cdns,zynqmp-gemcdns,gem disabled-99Zÿ  Ypclkhclktx_clkrx_clktsu_clk · (nh-1,ethernet@ff0c0000cdns,zynqmp-gemcdns,gem disabled-;;Zÿ  Ypclkhclktx_clkrx_clktsu_clk · (ni.2,ethernet@ff0d0000cdns,zynqmp-gemcdns,gem disabled-==Zÿ  Ypclkhclktx_clkrx_clktsu_clk · (nj/3,ethernet@ff0e0000cdns,zynqmp-gemcdns,gem disabled-??Zÿ Ypclkhclktx_clkrx_clktsu_clk · (nk04,gpio@ff0a0000xlnx,zynqmp-gpio-1.0 disabledÔà -†uZÿ · .ni2c@ff020000cdns,i2c-r1p14 disabled -Zÿ · %n=i2c@ff030000cdns,i2c-r1p14 disabled -Zÿ · &n>pcie@fd0e0000xlnx,nwl-pcie-2.11 disabled uð,pci<-vutsrÿmiscdummyintxmsi1msi0 0ZýýH€bregpciregcfg8nààC$ÿ.`A    · ;nÜ legacy-interrupt-controller† uÜ phy@fd400000xlnx,zynqmp-psgtr-v1.1 disabled Zý@ý= serdessiouOrtc@ffa60000xlnx,zynqmp-rtc disabledZÿ¦- ÿalarmsecZ€ahci@fd0c0000ceva,ahci-1v84 disabledZý  -…· nmmc@ff160000#xlnx,zynqmp-8.9aarasan,sdhci-8.9a disabled -0ZÿYclk_xinclk_ahbLfclk_out_sd0clk_in_sd0· 'n6mmc@ff170000#xlnx,zynqmp-8.9aarasan,sdhci-8.9a disabled -1ZÿYclk_xinclk_ahbLfclk_out_sd1clk_in_sd1· (n7iommu@fd800000 arm,mmu-500Zý€ disabledyÌ-›››››››››››››››››spi@ff040000cdns,spi-r1p6 disabled -Zÿ Yref_clkpclk · #n:spi@ff050000cdns,spi-r1p6 disabled -Zÿ Yref_clkpclk · $n;timer@ff110000 cdns,ttc disabled$-$%&ZÿŒ · ntimer@ff120000 cdns,ttc disabled$-'()ZÿŒ · ntimer@ff130000 cdns,ttc disabled$-*+,ZÿŒ · ntimer@ff140000 cdns,ttc disabled$--./ZÿŒ · nserial@ff000000!xlnx,zynqmp-uartcdns,uart-r1p12okay -ZÿYuart_clkpclk· !n8serial@ff010000!xlnx,zynqmp-uartcdns,uart-r1p12 disabled -ZÿYuart_clkpclk· "n9usb@fe200000 snps,dwc3 disabled -AZþ Yclk_xinclk_ahb· n "usb@fe300000 snps,dwc3 disabled -FZþ0Yclk_xinclk_ahb· n!"watchdog@fd4d0000cdns,wdt-r1p2 disabled -qZýM˜ nKpss_ref_clk fixed-clockL¤ü UÜvideo_clk fixed-clockL¤›üÀÜpss_alt_ref_clk fixed-clockL¤Ügt_crx_ref_clk fixed-clockL¤oóÜ aux_ref_clk fixed-clockL¤›üÀÜaliases´/axi/serial@ff000000¼/dccchosen ÄearlyconÍserial0:115200n8memory@0,memoryZ€ compatible#address-cells#size-cellsmodeldevice_typeenable-methodoperating-points-v2regcpu-idle-statesclocksentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usphandleopp-sharedopp-hzopp-microvoltclock-latency-nsstatusinterrupt-parentinterrupts#power-domain-cells#clock-cellsclock-namesfpga-mgrranges#interrupt-cellsinterrupt-controllertx-fifo-depthrx-fifo-depthpower-domainsxlnx,bus-width#gpio-cellsgpio-controllermsi-controllerinterrupt-namesmsi-parentreg-namesbus-rangeinterrupt-map-maskinterrupt-map#phy-cellscalibrationclock-output-names#global-interruptstimer-widthtimeout-secclock-frequencyserial0serial1bootargsstdout-path