Ð þíi8b(aà'tsd,rk3368-lion-haikourockchip,rk3368 +'7Theobroma Systems RK3368-uQ7 Baseboardaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff660000Q/i2c@ff140000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/serial@ff180000m/serial@ff190000u/serial@ff690000}/serial@ff1b0000…/serial@ff1c0000�/spi@ff110000’/spi@ff120000—/spi@ff130000cpus+cpu-mapcluster0core0œcore1œcore2œcore3œcluster1core0œcore1œcore2œcore3œ cpu@0 cpuarm,cortex-a53¬°psci¾Í Øcpu@1 cpuarm,cortex-a53¬°psci¾Í Øcpu@2 cpuarm,cortex-a53¬°psci¾Í Øcpu@3 cpuarm,cortex-a53¬°psci¾Í Ø cpu@100 cpuarm,cortex-a53¬°psci¾Í Øcpu@101 cpuarm,cortex-a53¬°psci¾Í Øcpu@102 cpuarm,cortex-a53¬°psci¾Í Øcpu@103 cpuarm,cortex-a53¬°psci¾Í Øbus simple-bus+àdma-controller@ff250000arm,pl330arm,primecell¬ÿ%@çòý/ à 6apb_pclkdma-controller@ff600000arm,pl330arm,primecell¬ÿ`@çòý/  6apb_pclkØ=arm-pmuarm,armv8-pmuv3`çpqrstuvw B psci arm,psci-0.2·smctimerarm,armv8-timer0ç ÿÿ ÿ ÿoscillator fixed-clockUn6exin24mxmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc¬ÿ @…}x@ / È D r v6biuciuciu-driveciu-sample“ ç ž €¥reset±okay¸ÂÔ å îùdefault  Z/mmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc¬ÿ @…ðÑ€ / É E s w6biuciuciu-driveciu-sample“ ç!ž �¥reset ±disabledmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc¬ÿ@…ðÑ€ / Ë G u y6biuciuciu-driveciu-sample“ ç#ž ƒ¥reset±okay¸UðÑ€;J/Xùdefault saradc@ff100000rockchip,saradc¬ÿ ç$e/ I [6saradcapb_pclkž W ¥saradc-apb ±disabledspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spi¬ÿ/ A R6spiclkapb_pclk ç,ùdefault+ ±disabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spi¬ÿ/ B S6spiclkapb_pclk ç-ùdefault+±okayflash@0jedec,spi-nor¬wúð€spi@ff130000(rockchip,rk3368-spirockchip,rk3066-spi¬ÿ/ C T6spiclkapb_pclk ç)ùdefault !+±okay‰ i2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿ ç>+6i2c/ Nùdefault"±okayØGi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿ ç?+6i2c/ Oùdefault# ±disabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿ ç@+6i2c/ Pùdefault$ ±disabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿ çA+6i2c/ Qùdefault% ±disabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uart¬ÿUn6/ M U6baudclkapb_pclk ç7’œ±okayùdefault &'(serial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uart¬ÿUn6/ N V6baudclkapb_pclk ç8’œ ±disabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uart¬ÿUn6/ P X6baudclkapb_pclk ç:’œ±okayserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uart¬ÿUn6/ Q Y6baudclkapb_pclk ç;’œ ±disabledthermal-zonescpu©d¿ˆÍ)tripscpu_alert0Ý$øéЧpassiveØ*cpu_alert1Ý8€éЧpassiveØ+cpu_critÝséÐ §criticalcooling-mapsmap0ô*0ùÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1ô+0ùÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu©d¿ˆÍ)tripsgpu_alert0Ý8€éЧpassiveØ,gpu_critÝÁ8éÐ §criticalcooling-mapsmap0ô,0ùÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿtsadc@ff280000rockchip,rk3368-tsadc¬ÿ( ç%/ H Z6tsadcapb_pclkž Ÿ ¥tsadc-apbùinitdefaultsleep-.-2s ±disabledØ)ethernet@ff290000rockchip,rk3368-gmac¬ÿ) çImacirqY/8/  f g c € Å ]M6stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac±okayf v0�inputš¥rgmiiùdefault1® Ä'ÃP Ù2 éòusb@ff500000 generic-ehci¬ÿP ç/ ±okayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2¬ÿX ç/ Á6otgûotg$€€@@ ±okayi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿe/ L6i2c ç<ùdefault3+±okaypmic@1brockchip,rk808¬ 4çexin32krk808-clkout2xùdefault563T7`7l7x7„7�7œ7¨7´7Á7Î7regulatorsDCDC_REG1Ûvdd_cpuê ®`ã`.Ø DCDC_REG2Ûvdd_logê ®`ã`.DCDC_REG3Ûvcc_ddr.DCDC_REG4 Ûvcc33_ioê2Z 2Z .ØLDO_REG2 Ûvcc33_videoê2Z 2Z .LDO_REG3 Ûvdd10_pllêB@B@.LDO_REG4 Ûvcc18_ioêw@w@.ØLDO_REG6 Ûvdd10_videoêB@B@.LDO_REG8 Ûvcc18_videoêw@w@.i2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2c¬ÿf ç=+6i2c/ Mùdefault8±okayØEpwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwm¬ÿh@ùdefault9/ _6pwm ±disabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwm¬ÿh@ùdefault:/ _6pwm ±disabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwm¬ÿh @/ _6pwm ±disabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwm¬ÿh0@ùdefault;/ _6pwm ±disabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uart¬ÿi/ O W6baudclkapb_pclk ç9ùdefault<’œ ±disabledmbox@ff6b0000rockchip,rk3368-mailbox¬ÿk0ç’“”•/ E 6pclk_mailboxK ±disabledsyscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfd¬ÿs€Ø@io-domains&rockchip,rk3368-pmu-io-voltage-domain ±disabledreboot-modesyscon-reboot-modeW^RBÃjRBÃxRBà ˆRBÃclock-controller@ff760000rockchip,rk3368-cru¬ÿvY/x”Ø syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfd¬ÿwØ/io-domains"rockchip,rk3368-io-voltage-domain ±disabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdt¬ÿ€/ p çO±okaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timer¬ÿ�  çBspdif@ff880000rockchip,rk3368-spdif¬ÿˆ ç6/ S Ð 6mclkhclk¡=¦txùdefault>° ±disabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2s¬ÿ‰ ç(6i2s_clki2s_hclk/ T Ρ==¦txrx° ±disabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2s¬ÿ‰€ ç56i2s_clki2s_hclk/ R Ï¡==¦txrxùdefault?° ±disablediommu@ff900800rockchip,iommu¬ÿ� çIiep_mmu/ Ê Ô 6aclkifaceÁ ±disablediommu@ff914000rockchip,iommu ¬ÿ‘@ÿ‘P çIisp_mmu/ Í Õ 6aclkifaceÁÎ ±disablediommu@ff930300rockchip,iommu¬ÿ“ çIvop_mmu/ Æ Ñ 6aclkifaceÁ ±disablediommu@ff9a0440rockchip,iommu ¬ÿš@@ÿš€@ ç  Ihevc_mmu/ Ð Ü 6aclkifaceÁ ±disablediommu@ff9a0800rockchip,iommu¬ÿšç  Ivepu_mmuvdpu_mmu/ Ð Ü 6aclkifaceÁ ±disabledefuse@ffb00000rockchip,rk3368-efuse¬ÿ° +/ q 6pclk_efusecpu-leakage@17¬temp-adjust@1f¬interrupt-controller@ffb71000 arm,gic-400éþ@¬ÿ·ÿ· ÿ·@ ÿ·`  ç ÿØpinctrlrockchip,rk3368-pinctrlY/@+àùdefaultAgpio0@ff750000rockchip,gpio-bank¬ÿu/ @ çQ,éþØ4gpio1@ff780000rockchip,gpio-bank¬ÿx/ A çR,éþØFgpio2@ff790000rockchip,gpio-bank¬ÿy/ B çS,éþØ gpio3@ff7a0000rockchip,gpio-bank¬ÿz/ C çT,éþØ2pcfg-pull-up8ØCpcfg-pull-downEpcfg-pull-noneTØBpcfg-pull-none-12maTa ØDemmcemmc-clkpBØemmc-cmdpCØemmc-pwrpCemmc-bus1pCemmc-bus4@pCCCCemmc-bus8€pCCCCCCCCØgmacrgmii-pinsðpBBBD D DDD DBBBBBBØ1rmii-pins pBBBD D DBBBBi2c0i2c0-xfer pBBØ3i2c1i2c1-xfer pBBØ8i2c2i2c2-xfer p BBØ"i2c3i2c3-xfer pBBØ#i2c4i2c4-xfer pBBØ$i2c5i2c5-xfer pBBØ%i2si2s-8ch-bus�p B BBBBBBBBØ?pwm0pwm0-pinpBØ9pwm1pwm1-pinpBØ:pwm3pwm3-pinpBØ;sdio0sdio0-bus1pCsdio0-bus4@pCCCCsdio0-cmdpCsdio0-clkpBsdio0-cdpCsdio0-wppCsdio0-pwrpCsdio0-bkpwrpCsdio0-intpCsdmmcsdmmc-clkp BØ sdmmc-cmdp CØsdmmc-cdp Csdmmc-bus1pCsdmmc-bus4@pCCCCØsdmmc-cd-pinp Bspdifspdif-txpBØ>spi0spi0-clkpCØspi0-cs0pCØspi0-cs1pCspi0-txpCØspi0-rxpCØspi1spi1-clkpCØspi1-cs0pCØspi1-cs1pCspi1-rxpCØspi1-txpCØspi2spi2-clkp CØspi2-cs0p CØ!spi2-rxp CØ spi2-txp CØtsadcotp-pinpBØ-otp-outpBØ.uart0uart0-xfer pCBØ&uart0-ctspBØ'uart0-rtspBØ(uart1uart1-xfer pCBuart1-ctspBuart1-rtspBuart2uart2-xfer pCBØ<uart3uart3-xfer pCBuart3-ctspBuart3-rtspBuart4uart4-xfer pCBuart4-ctspBuart4-rtspBledsmodule-led-pins p BBØHsd-card-led-pinpBØIpmicpmic-int-lpCØ5pmic-sleeppBØ6hoghaikou-pin-hog@pCCCCØAusb_otgotg-vbus-drvpBØKchosen~serial0:115200n8gmac-clk fixed-clockUsY@ eext_gmacxØ0i2cmux1 i2c-mux-gpio+ŠE •Fi2c@0¬+i2c@1¬+i2cmux2 i2c-mux-gpio+ŠG •F i2c@0¬+fan@18 ti,amc6821¬¾rtc@6f isil,isl1208¬oeeprom@50 atmel,24c01Ÿ¬Pi2c@1¬+leds gpio-ledsùdefaultHIled-1 ¨module_led1 è  ®heartbeatÄled-2 ¨module_led2 è2Ôoffled-3 ¨sd_card_led è4®mmc0vcc-sys-regulatorregulator-fixedÛvcc_sysêLK@LK@.Ø7dc-12vregulator-fixedÛdc_12v.ê··ØJvcc3v3-baseboardregulator-fixedÛvcc3v3_baseboard.ê2Z 2Z âJØvcc5v0-otg-regulatorregulator-fixedí ä4ùdefaultK Ûvcc5v0_otg compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2cpudevice_typeregenable-method#cooling-cellscpu-supplyphandlerangesinterrupts#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclocksclock-namesinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyfifo-depthresetsreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcd-gpiosdisable-wppinctrl-namespinctrl-0rockchip,default-sample-phasevmmc-supplymmc-hs200-1_8vnon-removablevqmmc-supply#io-channel-cellsspi-max-frequencycs-gpiosreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-tempinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-on#pwm-cells#mbox-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-names#sound-dai-cells#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathi2c-parentmux-gpiospagesizelabellinux,default-triggerpanic-indicatordefault-statevin-supplyenable-active-high