bx8\<(<\#geekbuying,geekboxrockchip,rk3368 +7GeekBoxaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff660000Q/i2c@ff140000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/serial@ff180000m/serial@ff190000u/serial@ff690000}/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3 cpu@0cpuarm,cortex-a53pscicpu@1cpuarm,cortex-a53pscicpu@2cpuarm,cortex-a53pscicpu@3cpuarm,cortex-a53psci cpu@100cpuarm,cortex-a53pscicpu@101cpuarm,cortex-a53pscicpu@102cpuarm,cortex-a53pscicpu@103cpuarm,cortex-a53pscibus simple-bus+dma-controller@ff250000arm,pl330arm,primecell%@ $  +apb_pclkdma-controller@ff600000arm,pl330arm,primecell`@ $  +apb_pclk4arm-pmuarm,armv8-pmuv3`pqrstuvw 7 psci arm,psci-0.2smctimerarm,armv8-timer0   oscillator fixed-clockJn6Zxin24mmmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @zр $  D r v+biuciuciu-driveciu-sample  reset disabledmmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @zр $  E s w+biuciuciu-driveciu-sample ! reset disabledmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc@zр $  G u y+biuciuciu-driveciu-sample # resetokayJр  default  saradc@ff100000rockchip,saradc $$ I [+saradcapb_pclk W saradc-apb disabledspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spi$ A R+spiclkapb_pclk ,default+ disabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spi$ B S+spiclkapb_pclk -default+ disabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spi$ C T+spiclkapb_pclk )default+ disabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2c >++i2c$ Ndefault disabledi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2c ?++i2c$ Odefault disabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2c @++i2c$ Pdefault disabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2c A++i2c$ Qdefault disabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uartJn6$ M U+baudclkapb_pclk 7$ disabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uartJn6$ N V+baudclkapb_pclk 8$ disabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uartJn6$ P X+baudclkapb_pclk :$ disabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uartJn6$ Q Y+baudclkapb_pclk ;$ disabledthermal-zonescpu1dGU tripscpu_alert0e$qpassive!cpu_alert1e8qpassive"cpu_critesq criticalcooling-mapsmap0|!0map1|"0 gpu1dGU tripsgpu_alert0e8qpassive#gpu_crite8q criticalcooling-mapsmap0|#0tsadc@ff280000rockchip,rk3368-tsadc( %$ H Z+tsadcapb_pclk  tsadc-apbinitdefaultsleep$%$sokay ethernet@ff290000rockchip,rk3368-gmac) macirq&8$  f g c ]M+stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macokay '+rgmii4inputA Q(default)h0qusb@ff500000 generic-ehciP $ okayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2X $ +otgzotg@@ okayi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2ce$ L+i2c <default*+okaypmic@1brockchip,rk808default+, -...... '.3.@.M Zxin32krk808-clkout2mregulatorsDCDC_REG1Zn ``vdd_cpuDCDC_REG2Zn ``vdd_logDCDC_REG3Znvcc_ddrDCDC_REG4Zn2Z2Zvcc_io LDO_REG1Znw@w@ vcc18_flash LDO_REG2Zn2Z2Z vcc33_lcdLDO_REG3ZnB@B@vdd_10LDO_REG4nw@w@vcca_18LDO_REG5Znw@2Z vccio_sdLDO_REG6ZnB@B@ vdd10_lcdLDO_REG7Znw@w@vcc_18LDO_REG8Znw@w@ vcc18_lcdSWITCH_REG1vcc_sdSWITCH_REG2Znvcc_lan'i2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2cf =++i2c$ Mdefault/ disabledpwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault0$ _+pwm disabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault1$ _+pwm disabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwmh $ _+pwm disabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwmh0default2$ _+pwm disabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uarti$ O W+baudclkapb_pclk 9default3$okaymbox@ff6b0000rockchip,rk3368-mailboxk0$ E +pclk_mailbox disabledsyscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfds7io-domains&rockchip,rk3368-pmu-io-voltage-domain disabledreboot-modesyscon-reboot-modeRBRBRB RBclock-controller@ff760000rockchip,rk3368-cruv&m syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdw&io-domains"rockchip,rk3368-io-voltage-domain disabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdt$ p Ookaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timer  Bspdif@ff880000rockchip,rk3368-spdif 6$ S  +mclkhclk 4%txdefault5/ disabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2s (+i2s_clki2s_hclk$ T  44%txrx/ disabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2s 5+i2s_clki2s_hclk$ R  44%txrxdefault6/ disablediommu@ff900800rockchip,iommu iep_mmu$  +aclkiface@ disablediommu@ff914000rockchip,iommu @P isp_mmu$  +aclkiface@M disablediommu@ff930300rockchip,iommu vop_mmu$  +aclkiface@ disablediommu@ff9a0440rockchip,iommu @@@  hevc_mmu$  +aclkiface@ disablediommu@ff9a0800rockchip,iommu  vepu_mmuvdpu_mmu$  +aclkiface@ disabledefuse@ffb00000rockchip,rk3368-efuse +$ q +pclk_efusecpu-leakage@17temp-adjust@1finterrupt-controller@ffb71000 arm,gic-400h}@ @ `   pinctrlrockchip,rk3368-pinctrl&7+gpio0@ff750000rockchip,gpio-banku$ @ Qh}-gpio1@ff780000rockchip,gpio-bankx$ A Rh}gpio2@ff790000rockchip,gpio-banky$ B Sh}>gpio3@ff7a0000rockchip,gpio-bankz$ C Th};pcfg-pull-up9pcfg-pull-downpcfg-pull-none8pcfg-pull-none-12ma :emmcemmc-clk8 emmc-cmd9emmc-pwr9emmc-bus19emmc-bus4@9999emmc-bus899999999gmacrgmii-pins888: : ::: :888888)rmii-pins888: : :8888i2c0i2c0-xfer 88*i2c1i2c1-xfer 88/i2c2i2c2-xfer  88i2c3i2c3-xfer 88i2c4i2c4-xfer 88i2c5i2c5-xfer 88i2si2s-8ch-bus 8 888888886pwm0pwm0-pin80pwm1pwm1-pin81pwm3pwm3-pin82sdio0sdio0-bus19sdio0-bus4@9999sdio0-cmd9sdio0-clk8sdio0-cd9sdio0-wp9sdio0-pwr9sdio0-bkpwr9sdio0-int9sdmmcsdmmc-clk 8sdmmc-cmd 9sdmmc-cd 9sdmmc-bus19sdmmc-bus4@9999spdifspdif-tx85spi0spi0-clk9spi0-cs09spi0-cs19spi0-tx9spi0-rx9spi1spi1-clk9spi1-cs09spi1-cs19spi1-rx9spi1-tx9spi2spi2-clk 9spi2-cs0 9spi2-rx 9spi2-tx 9tsadcotp-pin8$otp-out8%uart0uart0-xfer 98uart0-cts8uart0-rts8uart1uart1-xfer 98uart1-cts8uart1-rts8uart2uart2-xfer 983uart3uart3-xfer 98uart3-cts8uart3-rts8uart4uart4-xfer 98uart4-cts8uart4-rts8irir-int8<keyspwr-key8=pmicpmic-sleep8,pmic-int9+chosenserial2:115200n8memory@0memorygmac-clk fixed-clockJsY@ Zext_gmacm(ir-receivergpio-ir-receiver  ;default<gpio-keys gpio-keysdefault=power  - GPIO Powert gpio-leds gpio-ledsled-0  >geekbox:blue:led.onled-1  >geekbox:red:led.offvcc-sys-regulatorregulator-fixedvcc_sysLK@LK@Zn. compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2cpudevice_typeregenable-method#cooling-cellsphandlerangesinterrupts#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclocksclock-namesinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyfifo-depthresetsreset-namesstatusbus-widthcap-mmc-highspeednon-removablevmmc-supplyvqmmc-supplypinctrl-namespinctrl-0#io-channel-cellsreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphy-supplyphy-modeclock_in_outassigned-clocksassigned-clock-parentstx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-name#pwm-cells#mbox-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-names#sound-dai-cells#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathgpioslabellinux,codewakeup-sourcedefault-state