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Adisabledsimple-audio-card,cpuHsimple-audio-card,codecHpsciarm,psci-1.0arm,psci-0.2Ôsmctimerarm,armv8-timer0¾   xin24m fixed-clockkxn6ˆxin24m Di2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s‰ÿ ¾�)7ài2s_clki2s_hclk›   txrxª Adisabled i2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s‰ÿ ¾�*8ài2s_clki2s_hclk› txrxª Adisabled i2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s‰ÿ ¾�+9ài2s_clki2s_hclk› txrxª Adisabledspdif@ff030000rockchip,rk3328-spdif‰ÿ ¾�.: àmclkhclk›  tx»defaultɪ Adisabledpdm@ff040000 rockchip,pdm‰ÿ�=Ràpdm_clkpdm_hclk› rx»defaultsleepÉÓ Adisabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd‰ÿ :io-domains"rockchip,rk3328-io-voltage-domainAokayÝëù#1grf-gpiorockchip,rk3328-grf-gpio>N dpower-controller!rockchip,rk3328-power-controllerZ+ <power-domain@6‰power-domain@5‰power-domain@8‰��Freboot-modesyscon-reboot-modenÈuRBÃ�RBÃ�RBà ŸRBÃserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart‰ÿ ¾7�&Òàbaudclkapb_pclk› txrx»default É !"«¸ Adisabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart‰ÿ ¾8�'Óàbaudclkapb_pclk› txrx»default É#$%«¸ Adisabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart‰ÿ ¾9�(Ôàbaudclkapb_pclk› txrx»defaultÉ&«¸Aokayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ ¾$+�7Í ài2cpclk»defaultÉ' Adisabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ ¾%+�8Î ài2cpclk»defaultÉ(Aokaypmic@18rockchip,rk805‰ )¾kˆxin32krk805-clkout2>N»defaultÉ*Âãñ+ý+ ++!- gregulatorsDCDC_REG1 9vdd_logicH ß4` xŒregulator-state-memž¶B@DCDC_REG29vdd_armH ß4` xŒ regulator-state-memž¶~ðDCDC_REG39vcc_ddrxŒregulator-state-memžDCDC_REG49vcc_ioH2Z `2Z xŒ regulator-state-memž¶2Z LDO_REG19vcc_18Hw@`w@xŒ regulator-state-memž¶w@LDO_REG2 9vcc18_emmcHw@`w@xŒ regulator-state-memž¶w@LDO_REG39vdd_10HB@`B@xŒregulator-state-memž¶B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ ¾&+�9Ï ài2cpclk»defaultÉ, Adisabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ ¾'+�:Ð ài2cpclk»defaultÉ- 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àbuscoreŠfiommu@ff330200rockchip,iommu‰ÿ3 ¾` h265e_mmu�“Ý àaclkiface Adisablediommu@ff340800rockchip,iommu‰ÿ4@ ¾b vepu_mmu��F àaclkiface Adisabledvideo-codec@ff350000rockchip,rk3328-vpu‰ÿ5 ¾ vdpu��F àaclkhclk;&<iommu@ff350800rockchip,iommu‰ÿ5@ ¾ vpu_mmu��F àaclkiface&< ;iommu@ff360480rockchip,iommu ‰ÿ6€@ÿ6À@ ¾J rkvdec_mmu�‹B àaclkiface Adisabledvop@ff370000rockchip,rk3328-vop‰ÿ7>ü ¾ �‘x;àaclk_vopdclk_vophclk_vopŠ…†‡ ‘axiahbdclk=Aokayport+ endpoint@0‰4> Ciommu@ff373f00rockchip,iommu‰ÿ7? ¾ vop_mmu�‘; àaclkifaceAokay =hdmi@ff3c0000rockchip,rk3328-dw-hdmi‰ÿ<«¾#G�çFàiahbisfrcecD?Ihdmi»default É@AB�:ªAokay ports+port@0‰endpoint4C >port@1‰codec@ff410000rockchip,rk3328-codec‰ÿA�ë* àpclkmclk�:ª Adisabled phy@ff430000rockchip,rk3328-hdmi-phy‰ÿC ¾S�äDyàsysclkrefoclkrefpclk ˆhdmi_phykSE _cpu-versionpAokay ?clock-controller@ff440000(rockchip,rk3328-crurockchip,crusyscon‰ÿD�:k{ø[x=&'(ˆ‰Ž…ƒŠŒ�ABDC"\5ˆH؉4æ$ˆzDDD|k©€n6n6n6äáÀäáÀõáõáõáõáúð€õáõáõáúð€úð€úð€úð€n6#ÃFLG†ŒðÑ€xhÀxhÀðÑ€xhÀxhÀ€ syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfd‰ÿE+usb2-phy@100rockchip,rk3328-usb2phy‰�Dàphyclk ˆusb480m_phyk[{ˆFAokay Fotg-portp$¾;<=otg-bvalidotg-idlinestateAokay Uhost-portp ¾> linestateAokay Vmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc‰ÿP@ ¾  �=!JNàbiuciuciu-driveciu-sampleŸªðÑ€Aokay¸ÂÔå»defaultÉGHIJðý %K1mmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc‰ÿQ@ ¾  �>"KOàbiuciuciu-driveciu-sampleŸªðÑ€ Adisabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc‰ÿR@ ¾ �?#LPàbiuciuciu-driveciu-sampleŸªðÑ€Aokay¸Â>KZ»default ÉLMN%1ethernet@ff540000rockchip,rk3328-gmac‰ÿT ¾macirq8�dWXZY–ßMàstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macŠc ‘stmmaceth�:hAokay[dfˆOOsinput€P‹rgmii»defaultÉQ” �)­ Ã'ÃPØã$ìethernet@ff550000rockchip,rk3328-gmac‰ÿU�: ¾macirq8�TSSU•ÞVIàstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyŠbd‘stmmacethmac-phy‹rmiiõRhsoutput Adisabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22‰�VŠd»defaultÉST Rusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2‰ÿX ¾�Màotghost,;€€@ DU Iusb2-phyAokayusb@ff5c0000 generic-ehci‰ÿ\ ¾ �NFDVIusbAokayusb@ff5d0000 generic-ohci‰ÿ] ¾ �NFDVIusbAokayusb@ff600000rockchip,rk3328-dwc3snps,dwc3‰ÿ` ¾C�`a„àref_clksuspend_clkbus_clkotg Jutmi_wideStŒ®Ïè Adisabledinterrupt-controller@ff811000 arm,gic-400  @‰ÿ�ÿ� ÿ�@ ÿ�`  ¾  pinctrlrockchip,rk3328-pinctrl�:+·gpio0@ff210000rockchip,gpio-bank‰ÿ! ¾3�È>N   bgpio1@ff220000rockchip,gpio-bank‰ÿ" ¾4�É>N   )gpio2@ff230000rockchip,gpio-bank‰ÿ# ¾5�Ê>N  gpio3@ff240000rockchip,gpio-bank‰ÿ$ ¾6�Ë>N  pcfg-pull-up ' Ypcfg-pull-down 4 apcfg-pull-none C Wpcfg-pull-none-2ma C P `pcfg-pull-up-2ma ' Ppcfg-pull-up-4ma ' P Zpcfg-pull-none-4ma C P ]pcfg-pull-down-4ma 4 Ppcfg-pull-none-8ma C P [pcfg-pull-up-8ma ' P \pcfg-pull-none-12ma C P  ^pcfg-pull-up-12ma ' P  _pcfg-output-high _pcfg-output-low kpcfg-input-high ' v Xpcfg-input vi2c0i2c0-xfer ƒWW 'i2c1i2c1-xfer ƒWW (i2c2i2c2-xfer ƒ WW ,i2c3i2c3-xfer ƒWW -i2c3-pins ƒWWhdmi_i2chdmii2c-xfer ƒWW Apdm-0pdmm0-clk ƒW pdmm0-fsync ƒWpdmm0-sdi0 ƒW pdmm0-sdi1 ƒW pdmm0-sdi2 ƒW pdmm0-sdi3 ƒW pdmm0-clk-sleep ƒX pdmm0-sdi0-sleep ƒX pdmm0-sdi1-sleep ƒX pdmm0-sdi2-sleep ƒX pdmm0-sdi3-sleep ƒX pdmm0-fsync-sleep ƒXtsadcotp-pin ƒ W 8otp-out ƒ W 9uart0uart0-xfer ƒ WY uart0-cts ƒ W !uart0-rts ƒ W "uart0-rts-pin ƒ Wuart1uart1-xfer ƒWY #uart1-cts ƒW $uart1-rts ƒW %uart1-rts-pin ƒWuart2-0uart2m0-xfer ƒWYuart2-1uart2m1-xfer ƒWY &spi0-0spi0m0-clk ƒYspi0m0-cs0 ƒ Yspi0m0-tx ƒ Yspi0m0-rx ƒ Yspi0m0-cs1 ƒ Yspi0-1spi0m1-clk ƒYspi0m1-cs0 ƒYspi0m1-tx ƒYspi0m1-rx ƒYspi0m1-cs1 ƒYspi0-2spi0m2-clk ƒY .spi0m2-cs0 ƒY 1spi0m2-tx ƒY /spi0m2-rx ƒY 0i2s1i2s1-mclk ƒWi2s1-sclk ƒWi2s1-lrckrx ƒWi2s1-lrcktx ƒWi2s1-sdi ƒWi2s1-sdo ƒWi2s1-sdio1 ƒWi2s1-sdio2 ƒWi2s1-sdio3 ƒWi2s1-sleep� ƒXXXXXXXXXi2s2-0i2s2m0-mclk ƒWi2s2m0-sclk ƒWi2s2m0-lrckrx ƒWi2s2m0-lrcktx ƒWi2s2m0-sdi ƒWi2s2m0-sdo ƒWi2s2m0-sleep` ƒXXXXXXi2s2-1i2s2m1-mclk ƒWi2s2m1-sclk ƒWi2sm1-lrckrx ƒWi2s2m1-lrcktx ƒWi2s2m1-sdi ƒWi2s2m1-sdo ƒWi2s2m1-sleepP ƒXXXXXspdif-0spdifm0-tx ƒWspdif-1spdifm1-tx ƒWspdif-2spdifm2-tx ƒW sdmmc0-0sdmmc0m0-pwren ƒZsdmmc0m0-pin ƒZsdmmc0-1sdmmc0m1-pwren ƒZsdmmc0m1-pin ƒZ csdmmc0sdmmc0-clk ƒ[ Gsdmmc0-cmd ƒ\ Hsdmmc0-dectn ƒZ Isdmmc0-wrprt ƒZsdmmc0-bus1 ƒ\sdmmc0-bus4@ ƒ\\\\ Jsdmmc0-pins€ ƒZZZZZZZZsdmmc0extsdmmc0ext-clk ƒ]sdmmc0ext-cmd ƒZsdmmc0ext-wrprt ƒZsdmmc0ext-dectn ƒZsdmmc0ext-bus1 ƒZsdmmc0ext-bus4@ ƒZZZZsdmmc0ext-pins€ ƒZZZZZZZZsdmmc1sdmmc1-clk ƒ [sdmmc1-cmd ƒ \sdmmc1-pwren ƒ\sdmmc1-wrprt ƒ\sdmmc1-dectn ƒ\sdmmc1-bus1 ƒ\sdmmc1-bus4@ ƒ\\\\sdmmc1-pins� ƒ Z ZZZZZZZZemmcemmc-clk ƒ^ Lemmc-cmd ƒ_ Memmc-pwren ƒWemmc-rstnout ƒWemmc-bus1 ƒ_emmc-bus4@ ƒ____emmc-bus8€ ƒ________ Npwm0pwm0-pin ƒW 2pwm1pwm1-pin ƒW 3pwm2pwm2-pin ƒW 4pwmirpwmir-pin ƒW 5gmac-1rgmiim1-pins` ƒ [ ]][]]] ] ][ []][[[ [][[[[ Qrmiim1-pins ƒ`^```` ` `^ ^ W WWWWWgmac2phyfephyled-speed10 ƒWfephyled-duplex ƒWfephyled-rxm1 ƒW Sfephyled-txm1 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compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterruptsarm,pl330-periph-burstclock-names#dma-cellssimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-ddr-1_8vmmc-hs200-1_8vnon-removablesnps,txpblclock_in_outphy-supplyphy-modesnps,aalsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ussnps,rxpbltx_delayrx_delayphy-handlephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathvin-supplygpiosregulator-typeenable-active-highlabellinux,default-triggerdefault-state