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5gmac-1rgmiim1-pins` v Y [[Y[[[ [ [Y Y[[YYY Y[YYYY Nrmiim1-pins v^\^^^^ ^ ^\ \ U UUUUUgmac2phyfephyled-speed10 vUfephyled-duplex vUfephyled-rxm1 vU Qfephyled-txm1 vUfephyled-linkm1 vU Rtsadc_pintsadc-int v Utsadc-pin v Uhdmi_pinhdmi-cec vU @hdmi-hpd v_ Bcif-0dvp-d2d9-m0À vUUUUU U U UUUUUcif-1dvp-d2d9-m1À vUUUUUUUUUUUUbuttonreset-button-pin vU `ethernet-phyeth-phy-reset-pin v_ Oledslan-led-pin vU bsys-led-pin vU cwan-led-pin vU dpmicpmic-int-l vW *sdsdio-vcc-pin vW fchosen „serial2:1500000n8gmac-clock fixed-clockxsY@ ˆgmac_clkink Lkeys gpio-keysÉ`»defaultreset �reset ía –˜ ¡2leds gpio-leds Ébcd»defaultled-0 íe �nanopi-r2s:green:lanled-1 ía �nanopi-r2s:red:sysled-2 íe �nanopi-r2s:green:wansdmmcio-regulatorregulator-gpio ³ í)Éf»default 9vcc_io_sdioHnw@†2Z  ƈ ávoltage ðЬw@2Z   sdmmc-regulatorregulator-fixed aÉg»default9vcc_sd\n2Z †2Z   Kvdd-5vregulator-fixed9vdd_5vH\nLK@†LK@ + compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterruptsarm,pl330-periph-burstclock-names#dma-cellssimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplysnps,txpblclock_in_outphy-handlephy-modephy-supplyrx_delaysnps,aaltx_delayreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathlabellinux,codedebounce-intervalenable-active-highregulator-settling-time-usregulator-typestartup-delay-usvin-supplygpio