Ð þ톷8}Ü(Û}¤$rockchip,rk3328-evbrockchip,rk3328 +7Rockchip RK3328 EVBaliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000cpus+cpu@0}cpuarm,cortex-a53‰�”£³xÍpsciÛì cpu@1}cpuarm,cortex-a53‰�”£³xÍpsciÛì cpu@2}cpuarm,cortex-a53‰�”£³xÍpsciÛì cpu@3}cpuarm,cortex-a53‰�”£³xÍpsciÛì idle-statespscicpu-sleeparm,idle-state 1HxYúi„ l2-cache0cache opp_table0operating-points-v2z opp-408000000…Q–Œ~ðšœ@«opp-600000000…#ÃFŒ~ðšœ@opp-816000000…0£,ŒB@šœ@opp-1008000000…<ÜŒÈàšœ@opp-1200000000…G†ŒŒ±(šœ@opp-1296000000…M?dŒÖ šœ@bus simple-bus+·dmac@ff1f0000arm,pl330arm,primecell‰ÿ@¾É�† àapb_pclkì analog-soundsimple-audio-card÷i2s*Analog Adisabledsimple-audio-card,cpuHsimple-audio-card,codecHarm-pmuarm,cortex-a53-pmu0¾defgR display-subsystemrockchip,display-subsysteme hdmi-soundsimple-audio-card÷i2s€*HDMI Adisabledsimple-audio-card,cpuHsimple-audio-card,codecHpsciarm,psci-1.0arm,psci-0.2Ôsmctimerarm,armv8-timer0¾   xin24m fixed-clockkxn6ˆxin24m Ai2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s‰ÿ ¾�)7ài2s_clki2s_hclk›   txrxª Adisabled i2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s‰ÿ ¾�*8ài2s_clki2s_hclk› txrxª Adisabled i2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s‰ÿ ¾�+9ài2s_clki2s_hclk› txrxª Adisabledspdif@ff030000rockchip,rk3328-spdif‰ÿ ¾�.: àmclkhclk›  tx»defaultɪ Adisabledpdm@ff040000 rockchip,pdm‰ÿ�=Ràpdm_clkpdm_hclk› rx»defaultsleepÉÓ Adisabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd‰ÿ 7io-domains"rockchip,rk3328-io-voltage-domain Adisabledgrf-gpiorockchip,rk3328-grf-gpioÝípower-controller!rockchip,rk3328-power-controllerù+ 9power-domain@6‰power-domain@5‰power-domain@8‰��Freboot-modesyscon-reboot-mode ÈRBà RBÃ.RBà >RBÃserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart‰ÿ ¾7�&Òàbaudclkapb_pclk› txrx»default ÉJW Adisabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart‰ÿ ¾8�'Óàbaudclkapb_pclk› txrx»default É !JW Adisabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart‰ÿ ¾9�(Ôàbaudclkapb_pclk› txrx»defaultÉ"JWAokayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ ¾$+�7Í ài2cpclk»defaultÉ# Adisabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ ¾%+�8Î ài2cpclk»defaultÉ$Aokaypmic@18rockchip,rk805‰ %¾kˆxin32krk805-clkout2Ýí»defaultÉ&a‚�'œ'¨'´'À(Ì(regulatorsDCDC_REG1 Øvdd_logicç ß4ÿ +regulator-state-mem=UB@DCDC_REG2Øvdd_armç ß4ÿ + regulator-state-mem=U~ðDCDC_REG3Øvcc_ddr+regulator-state-mem=DCDC_REG4Øvcc_ioç2Z ÿ2Z + (regulator-state-mem=U2Z LDO_REG1Øvcc_18çw@ÿw@+regulator-state-mem=Uw@LDO_REG2 Øvcc18_emmcçw@ÿw@+regulator-state-mem=Uw@LDO_REG3Øvdd_10çB@ÿB@+regulator-state-mem=UB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ ¾&+�9Ï ài2cpclk»defaultÉ) Adisabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c‰ÿ ¾'+�:Ð ài2cpclk»defaultÉ* Adisabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi‰ÿ ¾1+� Ñàspiclkapb_pclk›  txrx»defaultÉ+,-. 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¾3�ÈÝí4# cgpio1@ff220000rockchip,gpio-bank‰ÿ" ¾4�ÉÝí4# bgpio2@ff230000rockchip,gpio-bank‰ÿ# ¾5�ÊÝí4# %gpio3@ff240000rockchip,gpio-bank‰ÿ$ ¾6�ËÝí4#pcfg-pull-upI Xpcfg-pull-downV `pcfg-pull-nonee Vpcfg-pull-none-2maer _pcfg-pull-up-2maIrpcfg-pull-up-4maIr Ypcfg-pull-none-4maer \pcfg-pull-down-4maVrpcfg-pull-none-8maer Zpcfg-pull-up-8maIr [pcfg-pull-none-12maer  ]pcfg-pull-up-12maIr  ^pcfg-output-high�pcfg-output-low�pcfg-input-highI˜ Wpcfg-input˜i2c0i2c0-xfer ¥VV #i2c1i2c1-xfer ¥VV $i2c2i2c2-xfer ¥ VV )i2c3i2c3-xfer ¥VV *i2c3-pins ¥VVhdmi_i2chdmii2c-xfer ¥VV >pdm-0pdmm0-clk¥V pdmm0-fsync¥Vpdmm0-sdi0¥V pdmm0-sdi1¥V pdmm0-sdi2¥V pdmm0-sdi3¥V pdmm0-clk-sleep¥W pdmm0-sdi0-sleep¥W pdmm0-sdi1-sleep¥W pdmm0-sdi2-sleep¥W pdmm0-sdi3-sleep¥W pdmm0-fsync-sleep¥Wtsadcotp-pin¥ V 5otp-out¥ V 6uart0uart0-xfer ¥ VX uart0-cts¥ V uart0-rts¥ V uart0-rts-pin¥ Vuart1uart1-xfer ¥VX uart1-cts¥V uart1-rts¥V !uart1-rts-pin¥Vuart2-0uart2m0-xfer ¥VXuart2-1uart2m1-xfer ¥VX "spi0-0spi0m0-clk¥Xspi0m0-cs0¥ Xspi0m0-tx¥ Xspi0m0-rx¥ Xspi0m0-cs1¥ Xspi0-1spi0m1-clk¥Xspi0m1-cs0¥Xspi0m1-tx¥Xspi0m1-rx¥Xspi0m1-cs1¥Xspi0-2spi0m2-clk¥X +spi0m2-cs0¥X .spi0m2-tx¥X ,spi0m2-rx¥X -i2s1i2s1-mclk¥Vi2s1-sclk¥Vi2s1-lrckrx¥Vi2s1-lrcktx¥Vi2s1-sdi¥Vi2s1-sdo¥Vi2s1-sdio1¥Vi2s1-sdio2¥Vi2s1-sdio3¥Vi2s1-sleep�¥WWWWWWWWWi2s2-0i2s2m0-mclk¥Vi2s2m0-sclk¥Vi2s2m0-lrckrx¥Vi2s2m0-lrcktx¥Vi2s2m0-sdi¥Vi2s2m0-sdo¥Vi2s2m0-sleep`¥WWWWWWi2s2-1i2s2m1-mclk¥Vi2s2m1-sclk¥Vi2sm1-lrckrx¥Vi2s2m1-lrcktx¥Vi2s2m1-sdi¥Vi2s2m1-sdo¥Vi2s2m1-sleepP¥WWWWWspdif-0spdifm0-tx¥Vspdif-1spdifm1-tx¥Vspdif-2spdifm2-tx¥V sdmmc0-0sdmmc0m0-pwren¥Ysdmmc0m0-pin¥Ysdmmc0-1sdmmc0m1-pwren¥Ysdmmc0m1-pin¥Y dsdmmc0sdmmc0-clk¥Z Dsdmmc0-cmd¥[ Esdmmc0-dectn¥Y Fsdmmc0-wrprt¥Ysdmmc0-bus1¥[sdmmc0-bus4@¥[[[[ Gsdmmc0-pins€¥YYYYYYYYsdmmc0extsdmmc0ext-clk¥\sdmmc0ext-cmd¥Ysdmmc0ext-wrprt¥Ysdmmc0ext-dectn¥Ysdmmc0ext-bus1¥Ysdmmc0ext-bus4@¥YYYYsdmmc0ext-pins€¥YYYYYYYYsdmmc1sdmmc1-clk¥ Z Lsdmmc1-cmd¥ [ Ksdmmc1-pwren¥[sdmmc1-wrprt¥[sdmmc1-dectn¥[sdmmc1-bus1¥[sdmmc1-bus4@¥[[[[ Jsdmmc1-pins�¥ Y YYYYYYYYemmcemmc-clk¥] Memmc-cmd¥^ Nemmc-pwren¥Vemmc-rstnout¥Vemmc-bus1¥^emmc-bus4@¥^^^^emmc-bus8€¥^^^^^^^^ Opwm0pwm0-pin¥V /pwm1pwm1-pin¥V 0pwm2pwm2-pin¥V 1pwmirpwmir-pin¥V 2gmac-1rgmiim1-pins`¥ Z \\Z\\\ \ \Z Z\\ZZZ Z\ZZZZrmiim1-pins¥_]____ _ _] ] V VVVVVgmac2phyfephyled-speed10¥Vfephyled-duplex¥Vfephyled-rxm1¥V Rfephyled-txm1¥Vfephyled-linkm1¥V Stsadc_pintsadc-int¥ Vtsadc-pin¥ Vhdmi_pinhdmi-cec¥V =hdmi-hpd¥` ?cif-0dvp-d2d9-m0À¥VVVVV V V VVVVVcif-1dvp-d2d9-m1À¥VVVVVVVVVVVVpmicpmic-int-l¥X &sdio-pwrseqwifi-enable-h¥V achosen³serial2:1500000n8dc-12vregulator-fixedØdc_12v+ç·ÿ· esdio-pwrseqmmc-pwrseq-simple»defaultÉa ¿b Isdmmc-regulatorregulator-fixed Ëc»defaultÉdØvcc_sdç2Z ÿ2Z Ð( Hvcc-sysregulator-fixedØvcc_sys+çLK@ÿLK@Ðe 'vcc-phy-regulatorregulator-fixedØvcc_phy+ Q compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterruptsarm,pl330-periph-burstclock-names#dma-cellssimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1gpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesnps,txpblphy-modephy-handleclock_in_outphy-supplyassigned-clock-ratephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathreset-gpiosgpiovin-supply