Ð þíp·8k(³jÌ&firefly,roc-rk3308-ccrockchip,rk3308 +7Firefly ROC-RK3308-CC boardaliases=/i2c@ff040000B/i2c@ff050000G/i2c@ff060000L/i2c@ff070000Q/serial@ff0a0000Y/serial@ff0b0000a/serial@ff0c0000i/serial@ff0d0000q/serial@ff0e0000y/spi@ff120000~/spi@ff130000ƒ/spi@ff140000cpus+cpu@0ˆcpuarm,cortex-a35”˜psci¦­¼ZÖêú cpu@1ˆcpuarm,cortex-a35”˜psciÖêúcpu@2ˆcpuarm,cortex-a35”˜psciÖêú cpu@3ˆcpuarm,cortex-a35”˜psciÖêú idle-statespscicpu-sleeparm,idle-state+<Sxdút„l2-cachecachecpu0-opp-tableoperating-points-v2…opp-408000000�Q– —~ð~ðr`¥œ@¶opp-600000000�#ÃF —~ð~ðr`¥œ@opp-816000000�0£, —£è£èr`¥œ@opp-1008000000�<Ü —*ˆ*ˆr`¥œ@arm-pmuarm,cortex-a35-pmu0ÂSTUVÍ external-mac-clock fixed-clockàúð€ ðmac_clkinpsci arm,psci-1.0Ÿsmctimerarm,armv8-timer0   xin24m fixed-clockàn6ðxin24mgrf@ff000000&rockchip,rk3308-grfsysconsimple-mfd”ÿBreboot-modesyscon-reboot-modeRBÃ'RBÃ3RBÃ?RBÃMRBà syscon@ff00b000-rockchip,rk3308-detect-grfsysconsimple-mfd”ÿ°+syscon@ff00c000+rockchip,rk3308-core-grfsysconsimple-mfd”ÿÀ+i2c@ff040000(rockchip,rk3308-i2crockchip,rk3399-i2c”ÿ¦Ê [i2cpclk  gdefaultu + disabledi2c@ff050000(rockchip,rk3308-i2crockchip,rk3399-i2c”ÿ¦Ë [i2cpclk  gdefaultu +okayà€rtc@51 nxp,pcf8563”Qi2c@ff060000(rockchip,rk3308-i2crockchip,rk3399-i2c”ÿ¦Ì [i2cpclk  gdefaultu + disabledi2c@ff070000(rockchip,rk3308-i2crockchip,rk3399-i2c”ÿ¦Í [i2cpclk Âgdefaultu+ disabledwatchdog@ff080000 snps,dw-wdt”ÿ¦Ö   disabledserial@ff0a0000&rockchip,rk3308-uartsnps,dw-apb-uart”ÿ  ¦Å[baudclkapb_pclk†�gdefault u disabledserial@ff0b0000&rockchip,rk3308-uartsnps,dw-apb-uart”ÿ  ¦Æ[baudclkapb_pclk†�gdefault u disabledserial@ff0c0000&rockchip,rk3308-uartsnps,dw-apb-uart”ÿ  ¦Ç[baudclkapb_pclk†�gdefaultuokayserial@ff0d0000&rockchip,rk3308-uartsnps,dw-apb-uart”ÿ  ¦È[baudclkapb_pclk†�gdefaultu disabledserial@ff0e0000&rockchip,rk3308-uartsnps,dw-apb-uart”ÿ ¦É[baudclkapb_pclk†�gdefault u disabledspi@ff120000(rockchip,rk3308-spirockchip,rk3066-spi”ÿ Â+¦Ï[spiclkapb_pclk�¢txrxgdefaultu disabledspi@ff130000(rockchip,rk3308-spirockchip,rk3066-spi”ÿ Â+¦Ð[spiclkapb_pclk�¢txrxgdefaultu !" disabledspi@ff140000(rockchip,rk3308-spirockchip,rk3066-spi”ÿ Â+¦Ñ[spiclkapb_pclk�##¢txrxgdefaultu$%&' disabledpwm@ff160000(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ¦yè [pwmpclkgdefaultu(¬ disabledpwm@ff160010(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ¦yè [pwmpclkgdefaultu)¬ disabledpwm@ff160020(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ ¦yè [pwmpclkgdefaultu*¬ disabledpwm@ff160030(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ0¦yè [pwmpclkgdefaultu+¬ disabledpwm@ff170000(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ¦xç [pwmpclkgdefaultu,¬ disabledpwm@ff170010(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ¦xç [pwmpclkgactiveu-¬okayPpwm@ff170020(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ ¦xç [pwmpclkgdefaultu.¬ disabledpwm@ff170030(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ0¦xç [pwmpclkgdefaultu/¬ disabledpwm@ff180000(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ¦Î [pwmpclkgdefaultu0¬okayUpwm@ff180010(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ¦Î [pwmpclkgdefaultu1¬ disabledpwm@ff180020(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ ¦Î [pwmpclkgdefaultu2¬ disabledpwm@ff180030(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ0¦Î [pwmpclkgdefaultu3¬ disabledrktimer@ff1a0000rockchip,rk3288-timer”ÿ  Â¦Ô [pclktimersaradc@ff1e0000.rockchip,rk3308-saradcrockchip,rk3399-saradc”ÿ Â%¦%Ò[saradcapb_pclk·ÉF Ðsaradc-apb disabledbus simple-bus+Üdma-controller@ff2c0000arm,pl330arm,primecell”ÿ,@Â㦊 [apb_pclkúdma-controller@ff2d0000arm,pl330arm,primecell”ÿ-@Â㦋 [apb_pclkú#i2s@ff350000(rockchip,rk3308-i2srockchip,rk3066-i2s”ÿ5 Â4¦\¨[i2s_clki2s_hclk�## ¢txrxÉ•”Ðreset-mreset-hgdefaultu4567 disabledi2s@ff360000(rockchip,rk3308-i2srockchip,rk3066-i2s”ÿ6 Â5¦^©[i2s_clki2s_hclk�# ¢rxÉ—–Ðreset-mreset-h disabledspdif-tx@ff3a0000,rockchip,rk3308-spdifrockchip,rk3066-spdif”ÿ: Â7¦b¢ [mclkhclk�# ¢txgdefaultu8 disabledmmc@ff4800000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshc”ÿH@ ÂL ¦š012[biuciuciu-driveciu-sampleðÑ€gdefaultu9:;<okay(:K,]jw…=‘>mmc@ff4900000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshc”ÿI@ ÂM ¦œ:;<[biuciuciu-driveciu-sampleðÑ€okay(ž­mmc@ff4a00000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshc”ÿJ@ ÂN ¦›567[biuciuciu-driveciu-sampleðÑ€gdefault u?@A disabledclock-controller@ff500000rockchip,rk3308-cru”ÿP»ÈBÕå€interrupt-controller@ff580000 arm,gic-400@”ÿXÿX ÿX@ ÿX`   ú sram@fff80000 mmio-sram”ÿøÜÿø+ddr-sram@0”€vad-sram@8000”€€pinctrlrockchip,rk3308-pinctrlÈB+ÜgdefaultuCgpio0@ff220000rockchip,gpio-bank”ÿ" Â(¦× 0 úNgpio1@ff230000rockchip,gpio-bank”ÿ# Â)¦Ø 0 úgpio2@ff240000rockchip,gpio-bank”ÿ$ Â*¦Ù 0 úgpio3@ff250000rockchip,gpio-bank”ÿ% Â+¦Ú 0 úgpio4@ff260000rockchip,gpio-bank”ÿ& Â,¦Û 0 úSpcfg-pull-up<Mpcfg-pull-downIJpcfg-pull-noneXFpcfg-pull-none-2maXepcfg-pull-up-2ma<epcfg-pull-up-4ma<eLpcfg-pull-none-4maXeKpcfg-pull-down-4maIepcfg-pull-none-8maXeDpcfg-pull-up-8ma<eEpcfg-pull-none-12maXe Hpcfg-pull-up-12ma<e Gpcfg-pull-none-smtXtIpcfg-output-high‰pcfg-output-low•pcfg-input-high< pcfg-input emmcemmc-clk­ Demmc-cmd­Eemmc-pwren­ Femmc-rstn­ Femmc-bus1­Eemmc-bus4@­EEEEemmc-bus8€­EEEEEEEEflashflash-csn0­ Fflash-rdy­ Fflash-ale­ Fflash-cle­ Fflash-wrn­Fflash-rdn­ Fflash-bus8€­GGGGGGGGgmacrmii-pins�­HHHFFFFF Fmac-refclk-12ma­ Hmac-refclk­ Fgmac-m1rmiim1-pins�­HHHFFFFF Fmacm1-refclk-12ma­ Hmacm1-refclk­ Fi2c0i2c0-xfer ­II i2c1i2c1-xfer ­ I I i2c2i2c2-xfer ­II i2c3-m0i2c3m0-xfer ­IIi2c3-m1i2c3m1-xfer ­ I Ii2c3-m2i2c3m2-xfer ­IIi2s_2ch_0i2s-2ch-0-mclk­ Fi2s-2ch-0-sclk­ F4i2s-2ch-0-lrck­F5i2s-2ch-0-sdo­F7i2s-2ch-0-sdi­F6i2s_8ch_0i2s-8ch-0-mclk­Fi2s-8ch-0-sclktx­Fi2s-8ch-0-sclkrx­Fi2s-8ch-0-lrcktx­Fi2s-8ch-0-lrckrx­Fi2s-8ch-0-sdo0­ Fi2s-8ch-0-sdo1­ Fi2s-8ch-0-sdo2­ Fi2s-8ch-0-sdo3­ Fi2s-8ch-0-sdi0­ Fi2s-8ch-0-sdi1­Fi2s-8ch-0-sdi2­Fi2s-8ch-0-sdi3­Fi2s_8ch_1_m0i2s-8ch-1-m0-mclk­Fi2s-8ch-1-m0-sclktx­Fi2s-8ch-1-m0-sclkrx­Fi2s-8ch-1-m0-lrcktx­Fi2s-8ch-1-m0-lrckrx­Fi2s-8ch-1-m0-sdo0­Fi2s-8ch-1-m0-sdo1-sdi3­Fi2s-8ch-1-m0-sdo2-sdi2­ Fi2s-8ch-1-m0-sdo3_sdi1­ Fi2s-8ch-1-m0-sdi0­ Fi2s_8ch_1_m1i2s-8ch-1-m1-mclk­ Fi2s-8ch-1-m1-sclktx­ Fi2s-8ch-1-m1-sclkrx­Fi2s-8ch-1-m1-lrcktx­Fi2s-8ch-1-m1-lrckrx­Fi2s-8ch-1-m1-sdo0­Fi2s-8ch-1-m1-sdo1-sdi3­Fi2s-8ch-1-m1-sdo2-sdi2­Fi2s-8ch-1-m1-sdo3_sdi1­Fi2s-8ch-1-m1-sdi0­Fpdm_m0pdm-m0-clk­Fpdm-m0-sdi0­ Fpdm-m0-sdi1­ Fpdm-m0-sdi2­ Fpdm-m0-sdi3­Fpdm_m1pdm-m1-clk­Fpdm-m1-sdi0­Fpdm-m1-sdi1­Fpdm-m1-sdi2­Fpdm-m1-sdi3­Fpdm_m2pdm-m2-clkm­Fpdm-m2-clk­Fpdm-m2-sdi0­ Fpdm-m2-sdi1­Fpdm-m2-sdi2­Fpdm-m2-sdi3­Fpwm0pwm0-pin­ Fpwm0-pin-pull-down­ J0pwm1pwm1-pin­F1pwm1-pin-pull-down­Jpwm2pwm2-pin­F2pwm2-pin-pull-down­Jpwm3pwm3-pin­F3pwm3-pin-pull-down­Jpwm4pwm4-pin­F,pwm4-pin-pull-down­Jpwm5pwm5-pin­Fpwm5-pin-pull-down­J-pwm6pwm6-pin­F.pwm6-pin-pull-down­Jpwm7pwm7-pin­F/pwm7-pin-pull-down­Jpwm8pwm8-pin­ F(pwm8-pin-pull-down­ Jpwm9pwm9-pin­ F)pwm9-pin-pull-down­ Jpwm10pwm10-pin­ F*pwm10-pin-pull-down­ Jpwm11pwm11-pin­F+pwm11-pin-pull-down­Jrtcrtc-32k­FCsdmmcsdmmc-clk­K9sdmmc-cmd­L:sdmmc-det­L;sdmmc-pwren­Ksdmmc-bus1­Lsdmmc-bus4@­LLLL<sdiosdio-clk­DAsdio-cmd­E@sdio-pwren­Dsdio-wrpt­Dsdio-intn­Dsdio-bus1­Esdio-bus4@­EEEE?spdif_inspdif-in­Fspdif_outspdif-out­F8spi0spi0-clk­Lspi0-csn0­Lspi0-miso­Lspi0-mosi­Lspi1spi1-clk­ Lspi1-csn0­ L spi1-miso­ L!spi1-mosi­ L"spi1-m1spi1m1-miso­Lspi1m1-mosi­Lspi1m1-clk­Lspi1m1-csn0­ Lspi2spi2-clk­L$spi2-csn0­L%spi2-miso­L&spi2-mosi­L'tsadctsadc-otp-pin­ Ftsadc-otp-out­ Fuart0uart0-xfer ­MMuart0-cts­Fuart0-rts­Fuart0-rts-pin­Fuart1uart1-xfer ­MMuart1-cts­Fuart1-rts­Fuart2-m0uart2m0-xfer ­MMuart2-m1uart2m1-xfer ­MMuart3uart3-xfer ­ M Muart3-m1uart3m1-xfer ­MMuart4uart4-xfer ­ MMuart4-cts­Fuart4-rts­Fuart4-rts-pin­Fir-receiverir-recv-pin­FObuttonspwr-key­Mchosen»serial2:1500000n8ir-receivergpio-ir-receiver ÇNgdefaultuOir_tx pwm-ir-txÍPa¨leds gpio-ledsled-0Òfirefly:red:powerØir-power-clickîon ÇNled-1Òfirefly:blue:userØir-user-clickîoff ÇN typec-vcc5vregulator-fixed ütypec_vcc5v LK@#LK@;OQvcc5v0-sysregulator-fixed üvcc5v0_sys LK@#LK@;OaQRvcc-ioregulator-fixedüvcc_io 2Z #2Z ;OaRTvcc-sdmmcregulator-gpio üvcc_sdmmc w@#2Z  ÇNów@2Z aR>vcc-sdregulator-fixed lSüvcc_sd 2Z #2Z ;OaT=vdd-corepwm-regulatorÍUˆ üvdd_core žx#r`q|ØŠú;O¨Rvdd-logregulator-fixedüvdd_log �#�;OaR compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootclock-namespinctrl-namespinctrl-0statusreg-shiftreg-io-widthdmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesrangesarm,pl330-periph-burst#dma-cellsbus-widthfifo-depthmax-frequencycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-hs200-1_8vnon-removable#reset-cellsrockchip,grfassigned-clocksassigned-clock-rates#interrupt-cellsinterrupt-controllergpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathgpiospwmslabellinux,default-triggerdefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onvin-supplygpioregulator-init-microvoltregulator-settling-time-up-uspwm-supply