Ð þírß8mH(—m$rockchip,rk3308-evbrockchip,rk3308 +7Rockchip RK3308 EVBaliases=/i2c@ff040000B/i2c@ff050000G/i2c@ff060000L/i2c@ff070000Q/serial@ff0a0000Y/serial@ff0b0000a/serial@ff0c0000i/serial@ff0d0000q/serial@ff0e0000y/spi@ff120000~/spi@ff130000ƒ/spi@ff140000cpus+cpu@0ˆcpuarm,cortex-a35”˜psci¦­¼ZÖêú cpu@1ˆcpuarm,cortex-a35”˜psciÖêúcpu@2ˆcpuarm,cortex-a35”˜psciÖêú cpu@3ˆcpuarm,cortex-a35”˜psciÖêú idle-statespscicpu-sleeparm,idle-state+<Sxdút„l2-cachecachecpu0-opp-tableoperating-points-v2…opp-408000000�Q– —~ð~ðr`¥œ@¶opp-600000000�#ÃF —~ð~ðr`¥œ@opp-816000000�0£, —£è£èr`¥œ@opp-1008000000�<Ü —*ˆ*ˆr`¥œ@arm-pmuarm,cortex-a35-pmu0ÂSTUVÍ external-mac-clock fixed-clockàúð€ ðmac_clkinpsci arm,psci-1.0Ÿsmctimerarm,armv8-timer0   xin24m fixed-clockàn6ðxin24mgrf@ff000000&rockchip,rk3308-grfsysconsimple-mfd”ÿ?reboot-modesyscon-reboot-modeRBÃ'RBÃ3RBÃ?RBÃMRBà syscon@ff00b000-rockchip,rk3308-detect-grfsysconsimple-mfd”ÿ°+syscon@ff00c000+rockchip,rk3308-core-grfsysconsimple-mfd”ÿÀ+i2c@ff040000(rockchip,rk3308-i2crockchip,rk3399-i2c”ÿ¦Ê [i2cpclk  gdefaultu + disabledi2c@ff050000(rockchip,rk3308-i2crockchip,rk3399-i2c”ÿ¦Ë [i2cpclk  gdefaultu + disabledi2c@ff060000(rockchip,rk3308-i2crockchip,rk3399-i2c”ÿ¦Ì [i2cpclk  gdefaultu + disabledi2c@ff070000(rockchip,rk3308-i2crockchip,rk3399-i2c”ÿ¦Í [i2cpclk Âgdefaultu+ disabledwatchdog@ff080000 snps,dw-wdt”ÿ¦Ö   disabledserial@ff0a0000&rockchip,rk3308-uartsnps,dw-apb-uart”ÿ  ¦Å[baudclkapb_pclk†�gdefault u disabledserial@ff0b0000&rockchip,rk3308-uartsnps,dw-apb-uart”ÿ  ¦Æ[baudclkapb_pclk†�gdefault u disabledserial@ff0c0000&rockchip,rk3308-uartsnps,dw-apb-uart”ÿ  ¦Ç[baudclkapb_pclk†�gdefaultu disabledserial@ff0d0000&rockchip,rk3308-uartsnps,dw-apb-uart”ÿ  ¦È[baudclkapb_pclk†�gdefaultu disabledserial@ff0e0000&rockchip,rk3308-uartsnps,dw-apb-uart”ÿ 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[pwmpclkgdefaultu-¬ disabledpwm@ff180000(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ¦Î [pwmpclkgdefaultu.¬okayRpwm@ff180010(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ¦Î [pwmpclkgdefaultu/¬ disabledpwm@ff180020(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ ¦Î [pwmpclkgdefaultu0¬ disabledpwm@ff180030(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ0¦Î [pwmpclkgdefaultu1¬ disabledrktimer@ff1a0000rockchip,rk3288-timer”ÿ  Â¦Ô [pclktimersaradc@ff1e0000.rockchip,rk3308-saradcrockchip,rk3399-saradc”ÿ Â%¦%Ò[saradcapb_pclk·ÉF Ðsaradc-apbokayÜ2Kbus simple-bus+èdma-controller@ff2c0000arm,pl330arm,primecell”ÿ,@Â力 [apb_pclkdma-controller@ff2d0000arm,pl330arm,primecell”ÿ-@Â曆 [apb_pclk!i2s@ff350000(rockchip,rk3308-i2srockchip,rk3066-i2s”ÿ5 Â4¦\¨[i2s_clki2s_hclk�!! ¢txrxÉ•”Ðreset-mreset-hgdefaultu3456 disabledi2s@ff360000(rockchip,rk3308-i2srockchip,rk3066-i2s”ÿ6 Â5¦^©[i2s_clki2s_hclk�! ¢rxÉ—–Ðreset-mreset-h disabledspdif-tx@ff3a0000,rockchip,rk3308-spdifrockchip,rk3066-spdif”ÿ: Â7¦b¢ [mclkhclk�! ¢txgdefaultu7 disabledmmc@ff4800000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshc”ÿH@ ÂL ¦š012[biuciuciu-driveciu-sample&ðÑ€gdefaultu89:; disabledmmc@ff4900000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshc”ÿI@ ÂM ¦œ:;<[biuciuciu-driveciu-sample&ðÑ€ disabledmmc@ff4a00000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshc”ÿJ@ ÂN ¦›567[biuciuciu-driveciu-sample&ðÑ€gdefault u<=> disabledclock-controller@ff500000rockchip,rk3308-cru”ÿP4A?N^€interrupt-controller@ff580000 arm,gic-400@”ÿXÿX ÿX@ ÿX`   s„sram@fff80000 mmio-sram”ÿøèÿø+ddr-sram@0”€vad-sram@8000”€€pinctrlrockchip,rk3308-pinctrlA?+ègdefaultu@gpio0@ff220000rockchip,gpio-bank”ÿ" Â(¦×™©„sMgpio1@ff230000rockchip,gpio-bank”ÿ# Â)¦Ø™©„sgpio2@ff240000rockchip,gpio-bank”ÿ$ Â*¦Ù™©„sgpio3@ff250000rockchip,gpio-bank”ÿ% Â+¦Ú™©„sgpio4@ff260000rockchip,gpio-bank”ÿ& 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Ci2s-8ch-0-sdo3& Ci2s-8ch-0-sdi0& Ci2s-8ch-0-sdi1&Ci2s-8ch-0-sdi2&Ci2s-8ch-0-sdi3&Ci2s_8ch_1_m0i2s-8ch-1-m0-mclk&Ci2s-8ch-1-m0-sclktx&Ci2s-8ch-1-m0-sclkrx&Ci2s-8ch-1-m0-lrcktx&Ci2s-8ch-1-m0-lrckrx&Ci2s-8ch-1-m0-sdo0&Ci2s-8ch-1-m0-sdo1-sdi3&Ci2s-8ch-1-m0-sdo2-sdi2& Ci2s-8ch-1-m0-sdo3_sdi1& Ci2s-8ch-1-m0-sdi0& Ci2s_8ch_1_m1i2s-8ch-1-m1-mclk& Ci2s-8ch-1-m1-sclktx& Ci2s-8ch-1-m1-sclkrx&Ci2s-8ch-1-m1-lrcktx&Ci2s-8ch-1-m1-lrckrx&Ci2s-8ch-1-m1-sdo0&Ci2s-8ch-1-m1-sdo1-sdi3&Ci2s-8ch-1-m1-sdo2-sdi2&Ci2s-8ch-1-m1-sdo3_sdi1&Ci2s-8ch-1-m1-sdi0&Cpdm_m0pdm-m0-clk&Cpdm-m0-sdi0& Cpdm-m0-sdi1& Cpdm-m0-sdi2& Cpdm-m0-sdi3&Cpdm_m1pdm-m1-clk&Cpdm-m1-sdi0&Cpdm-m1-sdi1&Cpdm-m1-sdi2&Cpdm-m1-sdi3&Cpdm_m2pdm-m2-clkm&Cpdm-m2-clk&Cpdm-m2-sdi0& Cpdm-m2-sdi1&Cpdm-m2-sdi2&Cpdm-m2-sdi3&Cpwm0pwm0-pin& Cpwm0-pin-pull-down& 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&JJuart2-m1uart2m1-xfer &JJuart3uart3-xfer & J Juart3-m1uart3m1-xfer &JJuart4uart4-xfer & JJuart4-cts&Cuart4-rts&Cuart4-rts-pin&Cbuttonspwr-key&JLusbusb-drv&CQsdio-pwrseqwifi-enable-h&Cchosen4serial4:1500000n8adc-keys0 adc-keys@KLbuttons]dkw@func-key…Ð �function–FPadc-keys1 adc-keys@KLbuttons]dkw@esc-key…ø�micmute–>home-key…u�mode– ¿ˆmenu-key…Ï�play– …€vol-down-key…r �volume down–“àvol-up-key…s �volume up–FPgpio-keys gpio-keys°gdefaultuLpower »M…t�GPIO Key PowerÁdÓvcc12v-dcinregulator-fixed ávcc12v_dcinð·· 4Nvcc5v0-sysregulator-fixed ávcc5v0_sysðLK@LK@ 4FNPvcc-1v8regulator-fixedávcc_1v8ðw@w@ 4FO2vcc-ddrregulator-fixedávcc_ddrðã`ã` 4FPvcc-ioregulator-fixedávcc_ioð2Z 2Z  4FPOvccio-flashregulator-fixed ávccio_flashð2Z 2Z  4FOvcc5v0-hostregulator-fixed QMVgdefaultuQ ávbus_hostFPvdd-corepwm-regulatoriRˆ ávdd_coreð žxr` 4núŒPvdd-logregulator-fixedávdd_logð�� 4FPvdd-1v0regulator-fixedávdd_1v0ðB@B@ 4FP compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootclock-namespinctrl-namespinctrl-0statusreg-shiftreg-io-widthdmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesvref-supplyrangesarm,pl330-periph-burst#dma-cellsbus-widthfifo-depthmax-frequency#reset-cellsrockchip,grfassigned-clocksassigned-clock-rates#interrupt-cellsinterrupt-controllergpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathio-channelsio-channel-namespoll-intervalkeyup-threshold-microvoltlinux,codelabelpress-threshold-microvoltautorepeatgpiosdebounce-intervalwakeup-sourceregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onvin-supplygpioenable-active-highpwmsregulator-settling-time-up-uspwm-supply