Ð þíŸ8—0(O–ø(hisilicon,hi6220-hikeyhisilicon,hi6220 +7HiKey Development Boardpsci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D idle-statesHpscicpu-sleeparm,idle-stateUf}¼Žúžè¯ cluster-sleeparm,idle-stateUf}莼ž Œ·Ü¯cpu@0arm,cortex-a53ÉcpuÕÙpsciç ø ÿ  #27¯cpu@1arm,cortex-a53ÉcpuÕÙpsciç ø ÿ  #27¯cpu@2arm,cortex-a53ÉcpuÕÙpsciç ø ÿ  #27¯cpu@3arm,cortex-a53ÉcpuÕÙpsciç ø ÿ  #27¯cpu@100arm,cortex-a53ÉcpuÕÙpsciçø ÿ  #27¯cpu@101arm,cortex-a53ÉcpuÕÙpsciçø ÿ  #27¯cpu@102arm,cortex-a53ÉcpuÕÙpsciçø ÿ  #27¯cpu@103arm,cortex-a53ÉcpuÕÙpsciçø ÿ  #27¯ l2-cache0cache¯ l2-cache1cache¯cpu_opp_tableoperating-points-v2L¯ opp00W eÔ^Þ€l¡ opp01W¿Ì^Þ€l¡ opp02W+s¨@^¡Ðl¡ opp03W98p^`l¡ opp04WG†Œ^KPl¡ interrupt-controller@f6801000 arm,gic-400@Õö€ö€ ö€@ ö€` }Ž £ ÿ¯timerarm,armv8-timer 0£ ÿÿ ÿ ÿsoc simple-bus+®sram@fff80000!hisilicon,hi6220-sramctrlsysconÕÿø ¯ao_ctrl@f7800000hisilicon,hi6220-aoctrlsysconÕ÷€ µÂ¯sys_ctrl@f7030000 hisilicon,hi6220-sysctrlsysconÕ÷ µÂ¯media_ctrl@f4410000"hisilicon,hi6220-mediactrlsysconÕôAµÂ¯Tpm_ctrl@f7032000hisilicon,hi6220-pmctrlsysconÕ÷ µacpu_sctrl@f6504000#hisilicon,hi6220-acpu-sctrlsysconÕöP@µ¯Xmedianoc_ade@f4520000sysconÕôR@¯Sstub_clockhisilicon,hi6220-stub-clkϵémbox-txô ¯ serial@f8015000arm,pl011arm,primecellÕøP £$ø$$ûuartclkapb_pclkserial@f7111000arm,pl011arm,primecellÕ÷ £%øûuartclkapb_pclkdefault  $rxtx.okay5)EðÑ€bluetooth ti,wl1835-st Zø ûext_clockserial@f7112000arm,pl011arm,primecellÕ÷  £&øûuartclkapb_pclkdefault.okay gLS-UART0serial@f7113000arm,pl011arm,primecellÕ÷0 £'øûuartclkapb_pclkdefault.okay gLS-UART1serial@f7114000arm,pl011arm,primecellÕ÷@ £(øûuartclkapb_pclkdefault .disableddma@f7370000hisilicon,k3-dma-1.0Õ÷7mx…  £Tø ’ �hi6220_dma.okay¯timer@f8008000arm,sp804arm,primecellÕø€£øûtimer1timer2apb_pclkrtc@f8003000arm,pl031arm,primecellÕø0 £ ø% ûapb_pclkrtc@f8004000arm,pl031arm,primecellÕø@ £ø& ûapb_pclkpinmux@f7010000pinctrl-singleÕ÷|+¦µÇ åp P X ` h p x       ! + 0 8 J z ~  ‡ � —default!"#$%¯,gpio-range¯ boot_sel_pmx_func=¯!emmc_pmx_funcP=  $¯;sd_pmx_func0=  ¯@sd_pmx_idle0=  ¯Csdio_pmx_func0=(,048<¯Hsdio_pmx_idle0=(,048<¯Kisp_pmx_func€=$(,048<@DHLPTX\`hkadc_ssi_pmx_func=h¯"codec_clk_pmx_func=l¯#codec_pmx_func =ptx|fm_pmx_func =€„ˆŒbt_pmx_func =�”˜œpwm_in_pmx_func=¸¯$bl_pwm_pmx_func=¼¯%uart0_pmx_func=ÀÄuart1_pmx_func =ÈÌÐÔ¯uart2_pmx_func =ØÜàä¯uart3_pmx_func =€„ˆŒ¯uart4_pmx_func =ÐÔØÜ¯uart5_pmx_func=ÈÌi2c0_pmx_func=èì¯0i2c1_pmx_func=ðô¯2i2c2_pmx_func=øü¯4spi0_pmx_func = ¤¨¬¯-pinmux@f7010800pinconf-singleÕ÷Œ+¦Ç default&'()*boot_sel_cfg_func=Qn‰p¯&hkadc_ssi_cfg_func=lQn‰p¯'emmc_clk_cfg_func=Qn‰ p¯<emmc_cfg_funcH=  $(Qn‰p¯=emmc_rst_cfg_func=,Qn‰p¯>sd_clk_cfg_func= Qn‰0p¯Asd_clk_cfg_idle= Qn‰p¯Dsd_cfg_func(= Qn‰ p¯Bsd_cfg_idle(= Qn‰p¯Esdio_clk_cfg_func=4Qn‰ p¯Isdio_clk_cfg_idle=4Qn‰p¯Lsdio_cfg_func(=8<@DHQn‰p¯Jsdio_cfg_idle(=8<@DHQn‰p¯Misp_cfg_func1x=(,048<@DHLPX\`dQn‰pisp_cfg_idle1=48Qn‰pisp_cfg_func2=TQn‰pcodec_clk_cfg_func=pQn‰p¯(codec_clk_cfg_idle=pQn‰pcodec_cfg_func1=tQn‰pcodec_cfg_func2=x|€Qn‰pcodec_cfg_idle2=x|€Qn‰pfm_cfg_func =„ˆŒ�Qn‰pbt_cfg_func =”˜œ Qn‰pbt_cfg_idle =”˜œ Qn‰ppwm_in_cfg_func=¼Qn‰p¯)bl_pwm_cfg_func=ÀQn‰p¯*uart0_cfg_func1=ÄQn‰puart0_cfg_func2=ÈQn‰puart1_cfg_func1=ÌÔQn‰p¯uart1_cfg_func2=ÐØQn‰p¯uart2_cfg_func =ÜàäèQn‰p¯uart3_cfg_func =�”˜œQn‰p¯uart4_cfg_func =àäèìQn‰p¯uart5_cfg_func=ØÜQn‰pi2c0_cfg_func=ìðQn‰p¯1i2c1_cfg_func=ôøQn‰p¯3i2c2_cfg_func=üQn‰p¯5spi0_cfg_func =°´¸¼Qn‰p¯.pinmux@f8001800pinconf-singleÕøx+¦Ç default+rstout_n_cfg_func=Qn‰p¯+pmu_peri_en_cfg_func=Qn‰psysclk0_en_cfg_func=Qn‰pjtag_tdo_cfg_func= Qn‰ prf_reset_cfg_func=ptQn‰pgpio@f8011000arm,pl061arm,primecellÕø £4§·Ž}ø ûapb_pclkOÃPWR_HOLDDSI_SELUSB_HUB_RESET_NUSB_SELHDMI_PDWL_REG_ONPWRON_DET5V_HUB_EN¯6gpio@f8012000arm,pl061arm,primecellÕø  £5§·Ž}ø ûapb_pclk:ÃSD_DETHDMI_INTPMU_IRQ_NWL_HOST_WAKENCNCNCBT_REG_ON¯gpio@f8013000arm,pl061arm,primecellÕø0 £6§·Ž}ø ûapb_pclkBÃGPIO-AGPIO-BGPIO-CGPIO-DGPIO-EUSB_ID_DETUSB_VBUS_DETGPIO-Hgpio@f8014000arm,pl061arm,primecellÕø@ £7§·Ó,PŽ}ø ûapb_pclk%ÃGPIO3_0NCNCNCWLAN_ACTIVENCNC¯}gpio@f7020000arm,pl061arm,primecellÕ÷ £8§·Ó,XŽ}ø ûapb_pclk?ÃUSER_LED1USER_LED2USER_LED3USER_LED4SD_SELNCNCBT_ACTIVE¯|gpio@f7021000arm,pl061arm,primecellÕ÷ £9§·Ó,`Ž}ø ûapb_pclk?ÃNCNC[UART1_RxD][UART1_TxD][AUX_SSI1]NC[PCM_CLK][PCM_FS]gpio@f7022000arm,pl061arm,primecellÕ÷  £:§·Ó,hŽ}ø ûapb_pclk=Ã[SPI0_DIN][SPI0_DOUT][SPI0_CS][SPI0_SCLK]NCNCNCGPIO-G¯/gpio@f7023000arm,pl061arm,primecellÕ÷0 £;§·Ó,pŽ}ø ûapb_pclk$ÃNCNCNCNC[PCM_DI][PCM_DO]NCNCgpio@f7024000arm,pl061arm,primecellÕ÷@ £<§· Ó,x,Ž}ø ûapb_pclkÃNC[CEC_CLK_19_2MHZ]NCgpio@f7025000arm,pl061arm,primecellÕ÷P £=§·Ó,Ž}ø ûapb_pclk'ÃGPIO-JGPIO-LNCNCNCNC[ISP_CCLK0]gpio@f7026000arm,pl061arm,primecellÕ÷` £>§· Ó,,Ž}ø ûapb_pclk?ÃBOOT_SEL[ISP_CCLK1]GPIO-IGPIO-KNCNC[I2C2_SDA][I2C2_SCL]gpio@f7027000arm,pl061arm,primecellÕ÷p £?§· Ó,,Ž}ø ûapb_pclk"Ã[I2C3_SDA][I2C3_SCL]NCNCNCgpio@f7028000arm,pl061arm,primecellÕ÷€ £@§· Ó,!,+Ž}ø ûapb_pclk8Ã[BT_PCM_XFS][BT_PCM_DI][BT_PCM_DO]NCNCNCNCGPIO-Fgpio@f7029000arm,pl061arm,primecellÕ÷� £A§·Ó,0Ž}ø ûapb_pclkhÃ[UART0_RX][UART0_TX][BT_UART1_CTS][BT_UART1_RTS][BT_UART1_RX][BT_UART1_TX][UART0_CTS][UART0_RTS]gpio@f702a000arm,pl061arm,primecellÕ÷  £B§·Ó,8Ž}ø ûapb_pclkZÃ[UART0_RxD][UART0_TxD][I2C0_SCL][I2C0_SDA][I2C1_SCL][I2C1_SDA][I2C2_SCL][I2C2_SDA]gpio@f702b000arm,pl061arm,primecellÕ÷° £C§·0Ó,J,z,~Ž}ø ûapb_pclk ÃNCgpio@f702c000arm,pl061arm,primecellÕ÷À £D§·Ó,Ž}ø ûapb_pclkgpio@f702d000arm,pl061arm,primecellÕ÷Ð £E§·Ó,‡Ž}ø ûapb_pclkgpio@f702e000arm,pl061arm,primecellÕ÷à £F§·Ó,�Ž}ø ûapb_pclkgpio@f702f000arm,pl061arm,primecellÕ÷ð £G§·Ó,—Ž}ø ûapb_pclkspi@f7106000arm,pl022arm,primecellÕ÷` £2ßæø ûapb_pclkdefault-.ñ ø/.okayi2c@f7100000snps,designware-i2cÕ÷ £,ø ,default01.okayi2c@f7101000snps,designware-i2cÕ÷ø £-,default23.okayi2c@f7102000snps,designware-i2cÕ÷ ø £.,default45.okay+adv7533@39 adi,adv7533Õ9 £ 6-ports+port@0endpoint>7¯Wport@2Õendpoint>8¯Pusbphyhisilicon,hi6220-usb-phyNY9d¯:usb@f72c0000hisilicon,hi6220-usbÕ÷,€: …usb2-phyøûotg�otg—¦€<¸€€€€€€€€ £Mmailbox@f7510000hisilicon,hi6220-mbox Õ÷Qßø £^ǯdwmmc0@f723d000hisilicon,hi6220-dw-mshcÕ÷#Ð £HøûciubiuÓÚresetdefault;<=>æø?dwmmc1@f723e000hisilicon,hi6220-dw-mshcdÕ÷#à £I+øûciubiuÓÚreset defaultidle @AB CDE&È8IVcpFG} ˆdwmmc2@f723f000hisilicon,hi6220-dw-mshcÕ÷#ð £JøûciubiuÓÚreset defaultidle HIJ KLMø‘N¤O+wlcore@2 ti,wl1835Õ £watchdog@f8005000arm,sp805arm,primecellÕøP £ øûwdog_clkapb_pclktsensor@0,f7030700hisilicon,tsensorÕ÷ £ø ûthermal_clk¯¯Qi2s@f7118000hisilicon,hi6210-i2sÕ÷€€ £{ø 8ûdacodeci2s-base$rxtxÅ-portsport@0¯~endpoint>PÞi2s¯8thermal-zonescls0éè÷d þQtripstrip-point@0/ýè;Ðpassivetrip-point@1/$ø;Ðpassive¯Rcooling-mapsmap0FR`Kÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿade@f4100000hisilicon,hi6220-adeÕôx Zade_basedSÓT £søTTT(ûclk_ade_coreclk_codec_jpegclk_ade_pix5TTEu**ˆy.okayportendpoint>U¯Vdsi@f4107800hisilicon,hi6220-dsiÕôxøTûpclk.okayports+port@0Õendpoint>V¯Uport@1Õendpoint@0>W¯7debug@f6590000&arm,coresight-cpu-debugarm,primecellÕöYø; ûapb_pclkDdebug@f6592000&arm,coresight-cpu-debugarm,primecellÕöY ø; ûapb_pclkDdebug@f6594000&arm,coresight-cpu-debugarm,primecellÕöY@ø; ûapb_pclkDdebug@f6596000&arm,coresight-cpu-debugarm,primecellÕöY`ø; ûapb_pclkDdebug@f65d0000&arm,coresight-cpu-debugarm,primecellÕö]ø; ûapb_pclkDdebug@f65d2000&arm,coresight-cpu-debugarm,primecellÕö] ø; ûapb_pclkDdebug@f65d4000&arm,coresight-cpu-debugarm,primecellÕö]@ø; ûapb_pclkDdebug@f65d6000&arm,coresight-cpu-debugarm,primecellÕö]`ø; ûapb_pclkD gpu@f4080000#hisilicon,hi6220-maliarm,mali-450Õô „£~~~~~~~~~~~8†gpgpmmupppp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3øTT ûcorebus5TTEÍe•DÚao_g3dmedia_g3dÓTfunnel@f6401000+arm,coresight-dynamic-funnelarm,primecellÕö@øX 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ûapb_pclkD¯uout-portsportendpoint>m¯eetm@f659f000"arm,coresight-etm4xarm,primecellÕöYðøX ûapb_pclkD¯vout-portsportendpoint>n¯fetm@f65dc000"arm,coresight-etm4xarm,primecellÕö]ÀøX ûapb_pclkD¯wout-portsportendpoint>o¯getm@f65dd000"arm,coresight-etm4xarm,primecellÕö]ÐøX ûapb_pclkD¯xout-portsportendpoint>p¯hetm@f65de000"arm,coresight-etm4xarm,primecellÕö]àøX ûapb_pclkD¯yout-portsportendpoint>q¯ietm@f65df000"arm,coresight-etm4xarm,primecellÕö]ðøX ûapb_pclkD ¯zout-portsportendpoint>r¯jcti@f6403000 arm,coresight-ctiarm,primecellÕö@0øX ûapb_pclkcti@f6598000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellÕöY€øX ûapb_pclkD–scti@f6599000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellÕöY�øX ûapb_pclkD–tcti@f659a000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellÕöY øX ûapb_pclkD–ucti@f659b000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellÕöY°øX ûapb_pclkD–vcti@f65d8000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellÕö]€øX ûapb_pclkD–wcti@f65d9000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellÕö]�øX ûapb_pclkD–xcti@f65da000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellÕö] øX ûapb_pclkD–ycti@f65db000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellÕö]°øX ûapb_pclkD –zaliases§/soc/serial@f8015000¯/soc/serial@f7111000·/soc/serial@f7112000¿/soc/serial@f7113000chosenÇserial3:115200n8memory@0Émemory`Õàðð ïÐà`ðA¯"reserved-memory+®ramoops@21f00000ramoopsÕ!ðÓßìlinux,cmashared-dma-poolø¡reboot-mode-syscon@5f01000sysconsimple-mfdÕðreboot-modesyscon-reboot-modewfU&wfU6wfUregulator@0regulator-fixedDSYS_5VSLK@kLK@ƒ•¯{regulator@1regulator-fixedDVDD_3V3S2Z k2Z ƒ•©{¯Nregulator@2regulator-fixedD5V_HUBSLK@kLK@ƒ ´6•©{¯9wl1835-pwrseqmmc-pwrseq-simple ¹6ø ûext_clockÅ Ü ¯Oleds gpio-ledsuser_led1 ggreen:user1 a| ïheartbeatuser_led2 ggreen:user2 a|ïmmc0user_led3 ggreen:user3 a|ïmmc1user_led4 ggreen:user4 a|ïnonewlan_active_led gyellow:wlan a}ïphy0txoffbt_active_ledgblue:bt a| ïhci0-poweroffpmic@f8000000hisilicon,hi655x-pmicÕøµŽ} #¯regulatorsLDO2 DLDO2_2V8S&% k0Ô.xLDO7 DLDO7_SDIOSw@k2Z .x¯FLDO10 DLDO10_2V85Sw@k-ÆÀ.h¯GLDO13 DLDO13_1V8SjkÁ0.xLDO14 DLDO14_2V8S&% k0Ô.xLDO15 DLDO15_1V8SjkÁ0ƒ•.xLDO17 DLDO17_2V5S&% k0Ô.xLDO19 DLDO19_3V0Sw@k-ÆÀ.h¯?LDO21 DLDO21_1V8S-Pk„€•.xLDO22 DLDO22_1V2S » kO€ƒ•.xfirmwareopteelinaro,optee-tz=smcsound_cardaudio-graph-cardJ~ compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpuentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usphandlewakeup-latency-usdevice_typeregenable-methodnext-level-cacheclocksoperating-points-v2cpu-idle-states#cooling-cellsdynamic-power-coefficientopp-sharedopp-hzopp-microvoltclock-latency-ns#interrupt-cellsinterrupt-controllerinterruptsranges#clock-cells#reset-cellshisilicon,hi6220-clk-srammbox-namesmboxesclock-namespinctrl-namespinctrl-0dmasdma-namesstatusassigned-clocksassigned-clock-ratesenable-gpioslabel#dma-cellsdma-channelsdma-requestsdma-no-ccidma-type#pinctrl-cells#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-range#pinctrl-single,gpio-range-cellspinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthgpio-controller#gpio-cellsgpio-line-namesgpio-rangesbus-idenable-dmanum-cscs-gpiosi2c-sda-hold-time-nspd-gpiosadi,dsi-lanes#sound-dai-cellsremote-endpoint#phy-cellsphy-supplyhisilicon,peripheral-sysconphysphy-namesdr_modeg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-size#mbox-cellsresetsreset-namescap-mmc-highspeednon-removablebus-widthvmmc-supplypinctrl-1card-detect-delaycap-sd-highspeedsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50vqmmc-supplydisable-wpcd-gpioscap-power-off-cardmmc-pwrseq#thermal-sensor-cellshisilicon,sysctrl-syscondai-formatpolling-delaypolling-delay-passivesustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicereg-nameshisilicon,noc-syscondma-coherentinterrupt-namesarm,cs-dev-assocserial0serial1serial2serial3stdout-pathrecord-sizeconsole-sizeftrace-sizereusablelinux,cma-defaultoffsetmode-normalmode-bootloadermode-recoveryregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-onvin-supplygpioreset-gpiospost-power-on-delay-mspower-off-delay-uslinux,default-triggerpanic-indicatordefault-statepmic-gpiosregulator-enable-ramp-delaydais