Ð þí¨‚8žü( †žÄ+hisilicon,hi3660-hikey960hisilicon,hi3660 + 7HiKey960psci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D cpu@0arm,cortex-a53HcpuTXpscif w ‡Pš ¡µÄnÞcpu@1arm,cortex-a53HcpuTXpscif w ‡Pš ¡µÞcpu@2arm,cortex-a53HcpuTXpscif w ‡Pš ¡µÞcpu@3arm,cortex-a53HcpuTXpscif w ‡Pš ¡µÞcpu@100arm,cortex-a73HcpuTXpscifw‡š ¡µÄ&Þcpu@101arm,cortex-a73HcpuTXpscifw‡š ¡µÞcpu@102arm,cortex-a73HcpuTXpscifw‡š ¡µÞcpu@103arm,cortex-a73HcpuTXpscifw‡š ¡µÞ idle-statesæpscicpu-sleep-0arm,idle-stateó�,Š<ÜÞ cluster-sleep-0arm,idle-stateóô,@< ¬Þ cpu-sleep-1arm,idle-stateó�,&<ÜÞcluster-sleep-1arm,idle-stateó , T< ¬Þl2-cache0cacheÞ l2-cache1cacheÞopp_table0operating-points-v2MÞopp00XÄï@_ ®`m“àopp01X;‹‡À_ 5m“àopp02XS�Ò€_ » m“àopp03XeÝE@_B@m“àopp04Xmé5_Èàm“àopp_table1operating-points-v2MÞopp10X5Ò¯À_ ®`m“àopp11XT²½@_ 5m“àopp12Xk–@_ » m“àopp13X}â�_B@m“àopp14XŒÉB€_Èàm“àinterrupt-controller@e82b0000 arm,gic-400@Tè+è+ è+@ è+` ~� ¤ ÿÞa53-pmuarm,cortex-a53-pmu0¤¯a73-pmuarm,cortex-a73-pmu0¤¯ timerarm,armv8-timer 0¤ ÿÿ ÿ ÿsoc simple-bus+Âcrg_ctrl@fff35000 hisilicon,hi3660-crgctrlsysconTÿóPÉÞcrg_rst_controllerhisilicon,hi3660-resetÖãÞpctrl@e8a09000hisilicon,hi3660-pctrlsysconTè � ÉÞMcrg_ctrl@fff34000 hisilicon,hi3660-pmuctrlsysconTÿó@Ésctrl@fff0a000hisilicon,hi3660-sctrlsysconTÿð ÉÞ9iomcu@ffd7e000hisilicon,hi3660-iomcusysconTÿ×àÉÞresethisilicon,hi3660-resetãÖÞmailbox@e896b000hisilicon,hi3660-mboxTè–°¤ÀÁóÞstub_clock@e896b500hisilicon,hi3660-stub-clkTè–µÉÿ Þ timer@fff14000arm,sp804arm,primecellTÿñ@¤01š   timer1timer2apb_pclki2c@ffd71000snps,designware-i2cTÿ× ¤v+€š " )default7AokayHLS-I2C0i2c@ffd72000snps,designware-i2cTÿ×  ¤w+€š " )default7Aokayrt1711h@4erichtek,rt1711hTNAokay ¤)default7connectorusb-c-connectorHUSB-CNdualXdualcsinkr�2~�2†A�dˆ˜–€ports+port@1TendpointšÞPport+endpoint@0TšÞOadv7533@39Aokay adi,adv7533T9ªports+port@0Tport@1Ti2c@fdf0c000snps,designware-i2cTýðÀ ¤Q+€š7 "x)default7 ! Adisabledi2c@fdf0b000snps,designware-i2cTýð° ¤:+€š6 "`)default7"#AokayHLS-I2C1serial@fdf02000arm,pl011arm,primecellTýð  ¤Jšhuartclkapb_pclk)default7$% Adisabledserial@fdf00000arm,pl011arm,primecellTýð ¤K¸rxtxÂ&&š99uartclkapb_pclk)default7'( Adisabledserial@fdf03000arm,pl011arm,primecellTýð0 ¤L¸rxtxÂ&&š:uartclkapb_pclk)default7)* Adisabledserial@ffd74000arm,pl011arm,primecellTÿ×@ ¤ršuartclkapb_pclk)default7+,Aokay HLS-UART0serial@fdf01000arm,pl011arm,primecellTýð ¤M¸rxtxÂ&&š;;uartclkapb_pclk)default7-.Aokaybluetooth ti,wl1837-st Ç/Ô-ÆÀserial@fdf05000arm,pl011arm,primecellTýðP ¤N¸rxtxÂ&& š<<uartclkapb_pclk)default701 Adisabledserial@fff32000arm,pl011arm,primecellTÿó  ¤Oš uartclkapb_pclk)default723Aokay HLS-UART1dma@fdf30000hisilicon,k3-dma-1.0TýóÞéö ÿþ ¤�š> hi3660_dmaÞ&dma-controller@e804b000hisilicon,hisi-pcm-asp-dma-1.0Tè°Þéö  ¤Ø (asp_dma_irqrtc@fff04000arm,pl031arm,primecellTÿð@ ¤.š apb_pclkgpio@e8a0b000arm,pl061arm,primecellTè ° ¤T8HT4�~š apb_pclkL`TP901[PMU0_SSI][PMU1_SSI][PMU2_SSI][PMU0_CLKOUT][JTAG_TCK][JTAG_TMS]gpio@e8a0c000arm,pl061arm,primecellTè À ¤U8HT4�~š  apb_pclkC`[JTAG_TRST_N][JTAG_TDI][JTAG_TDO]NCNC[I2C3_SCL][I2C3_SDA]NCgpio@e8a0d000arm,pl061arm,primecellTè Ð ¤V8HT4�~š! apb_pclkG`NCNCNCGPIO-JGPIO_020_HDMI_SELGPIO-LGPIO_022_UFSBUCK_INT_NGPIO-Ggpio@e8a0e000arm,pl061arm,primecellTè à ¤W8HT4�~š" apb_pclkJ`[CSI0_MCLK][CSI1_MCLK]NC[I2C2_SCL][I2C2_SDA][I2C3_SCL][I2C3_SDA]NCgpio@e8a0f000arm,pl061arm,primecellTè ð ¤X8HT4�~š# apb_pclkA`NCNCPWR_BTN_NGPIO_035_PMU2_ENGPIO_036_USB_HUB_RESETNCNCNCÞvgpio@e8a10000arm,pl061arm,primecellTè¡ ¤Y8HT4&�~š$ apb_pclkQ`GPIO-HGPIO_041_HDMI_PDTP904TP905NCNCGPIO_046_HUB_VDD33_ENGPIO_047_PMU1_ENgpio@e8a11000arm,pl061arm,primecellTè¡ ¤Z8HT4.�~š% apb_pclkA`NCNCNCGPIO_051_WIFI_ENGPIO-I[SD_DAT1][SD_DAT2][UART1_RXD]Þxgpio@e8a12000arm,pl061arm,primecellTè¡  ¤[8HT46�~š& apb_pclky`[UART1_TXD][UART0_CTS][UART0_RTS][UART0_RXD][UART0_TXD][SOC_BT_UART4_CTS_N][SOC_BT_UART4_RTS_N][SOC_BT_UART4_RXD]gpio@e8a13000arm,pl061arm,primecellTè¡0 ¤\8HT4>�~š' apb_pclk?`[SOC_BT_UART4_TXD]NC[PMU_HKADC_SSI]NCGPIO_068_SELNCNCNCgpio@e8a14000arm,pl061arm,primecellTè¡@ ¤]8HT4F�~š( apb_pclk`NCNCNCGPIO-KNCNCNCNCgpio@e8a15000arm,pl061arm,primecellTè¡P ¤^8HT4N�~š) apb_pclk`NCNCNCNCNCNCNCNCgpio@e8a16000arm,pl061arm,primecellTè¡` ¤_8HT4V�~š* apb_pclk$`NC[PCIE_PERST_N]NCNCNCNCNCNCÞ?gpio@e8a17000arm,pl061arm,primecellTè¡p ¤`8H T4^4e�~š+ apb_pclk`NCNCNCNCgpio@e8a18000arm,pl061arm,primecellTè¡€ ¤a8HT4f�~š, apb_pclk`NCNCNCNCNCNCNCNCgpio@e8a19000arm,pl061arm,primecellTè¡� ¤b8HT4n�~š- apb_pclk`NCNCNCNCNCNCNCNCgpio@e8a1a000arm,pl061arm,primecellTè¡  ¤c8HT4v�~š. apb_pclk'`NCNCNCNCNCNCGPIO_126_BT_ENTP902Þ/gpio@e8a1b000arm,pl061arm,primecellTè¡° ¤d8H�~š/ apb_pclk`gpio@e8a1c000arm,pl061arm,primecellTè¡À ¤e8H�~š0 apb_pclk`gpio@ff3b4000arm,pl061arm,primecellTÿ;@ ¤f8HT5�~š1 apb_pclkm`[UFS_REF_CLK][UFS_RST_N][SPI1_SCLK][SPI1_DIN][SPI1_DOUT][SPI1_CS]GPIO_150_USER_LED1GPIO_151_USER_LED2Þ>gpio@ff3b5000arm,pl061arm,primecellTÿ;P ¤g8HT5�~š2 apb_pclk`NCNCNCNCgpio@e8a1f000arm,pl061arm,primecellTè¡ð ¤h8HT6�~š3 apb_pclk@`[SD_CLK][SD_CMD][SD_DATA0][SD_DATA1][SD_DATA2][SD_DATA3]gpio@e8a20000arm,pl061arm,primecellTè¢ ¤i8H�~T7š4 apb_pclk^`[WL_SDIO_CLK][WL_SDIO_CMD][WL_SDIO_DATA0][WL_SDIO_DATA1][WL_SDIO_DATA2][WL_SDIO_DATA3]gpio@fff0b000arm,pl061arm,primecellTÿð° ¤j8HT8�~š9 apb_pclkd`[GPIO_176_PMU_PWR_HOLD]NA[SYSCLK_EN]GPIO_179_WL_WAKEUP_APGPIO_180_HDMI_INTNAGPIO-F[I2C0_SCL]ÞJgpio@fff0c000arm,pl061arm,primecellTÿðÀ ¤k8HT8�~š9 apb_pclk^`[I2C0_SDA][I2C1_SCL][I2C1_SDA][I2C1_SCL][I2C1_SDA]GPIO_189_USER_LED3GPIO_190_USER_LED4Þwgpio@fff0d000arm,pl061arm,primecellTÿðÐ ¤l8HT8 �~š9 apb_pclkt`[PCM_DI][PCM_DO][PCM_CLK][PCM_FS][GPIO_196_I2S2_DI][GPIO_197_I2S2_DO][GPIO_198_I2S2_XCLK][GPIO_199_I2S2_XFS]gpio@fff0e000arm,pl061arm,primecellTÿðà ¤m8H T88�~š9 apb_pclkz`NCNCGPIO_202_VBUS_TYPECGPIO_203_SD_DETGPIO_204_PMU12_IRQ_NGPIO_205_WIFI_ACTIVEGPIO_206_USBSW_SELGPIO_207_BT_ACTIVEÞ@gpio@fff0f000arm,pl061arm,primecellTÿðð ¤n8HT8�~š9 apb_pclkL`GPIO-AGPIO-BGPIO-CGPIO-DGPIO-E[PCIE_CLKREQ_N][PCIE_WAKE_N][SPI0_CLK]gpio@fff10000arm,pl061arm,primecellTÿñ ¤o8HT8$�~š9 apb_pclkB`[SPI0_DIN][SPI0_DOUT][SPI0_CS]GPIO_219_CC_INTNCNC[PMU_INT]Þgpio@fff1d000arm,pl061arm,primecellTÿñÐ ¤�8H�~š9 apb_pclk`spi@ffd68000arm,pl022arm,primecellTÿÖ€+ ¤tš apb_pclk)default7:;p wAokayHLS-SPI0spi@ff3b3000arm,pl022arm,primecellTÿ;0+ ¤8š5 apb_pclk)default7<=p w>AokayHHS-SPI1pcie@f4000000hisilicon,kirin960-pcie@Tôÿ?àóòõ €dbiapbphyconfigŠ+HpciÂö”~ ¤(msižø€±(šRSQP:pcie_phy_refpcie_auxpcie_apb_phypcie_apb_syspcie_aclk ¿?ufs@ff3b0000#hisilicon,hi3660-ufsjedec,ufs-1.1 Tÿ;ÿ;  ¤šferef_clkphy_clkË "„ Ùrstdwmmc1@ff37f000hisilicon,hi3660-dw-mshcTÿ7ð+ ¤‹šKciubiu0Ô "”Ùresetå9ÈAokay.;HUc n@)default 7ABCwDƒEdwmmc2@ff3ff000hisilicon,hi3660-dw-mshcTÿ?ð+ ¤ŒšLciubiu "”ÙresetÈAokay�ž¨)default 7FGHwIwlcore@2 ti,wl1837T J¤watchdog@e8a06000arm,sp805arm,primecellTè ` ¤,š  wdog_clkapb_pclkwatchdog@e8a07000arm,sp805arm,primecellTè p ¤-š  wdog_clkapb_pclktsensor@fff30000hisilicon,hi3660-tsensorTÿó ¤‘»ÞKthermal-zonescls0Ñèßdõ”Ktripstrip-point@0ýè#èOpassivetrip-point@1$ø#èOpassiveÞLcooling-mapsmap0.L30@ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1.L30@ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿusb3_otg_bc@ff200000sysconsimple-mfdTÿ usb-phyhisilicon,hi3660-usb-phyOZsMŠ$fäÞNdwc3@ff100000 snps,dwc3TÿšIrefbus_early¦I¶ ¦C@0"����¤Ÿ¡ËN Ðusb3-phyÚotg âsuper-speedðutmiù1Jc}‘©¿Ïhostport+endpoint@0TšOÞendpoint@1TšPÞetm@ecc40000"arm,coresight-etm4xarm,primecellTìÄš apb_pclkDout-portsportendpointšQÞVetm@ecd40000"arm,coresight-etm4xarm,primecellTìÔš apb_pclkDout-portsportendpointšRÞWetm@ece40000"arm,coresight-etm4xarm,primecellTìäš apb_pclkDout-portsportendpointšSÞXetm@ecf40000"arm,coresight-etm4xarm,primecellTìôš apb_pclkDout-portsportendpointšTÞYfunnel@ec801000+arm,coresight-dynamic-funnelarm,primecellT쀚 apb_pclkout-portsportendpointšUÞZin-ports+port@0TendpointšVÞQport@1TendpointšWÞRport@2TendpointšXÞSport@3TendpointšYÞTetf@ec802000 arm,coresight-tmcarm,primecellTì€ š apb_pclkin-portsportendpointšZÞUout-portsportendpointš[Þhetm@ed440000"arm,coresight-etm4xarm,primecellTíDš apb_pclkDout-portsportendpointš\Þaetm@ed540000"arm,coresight-etm4xarm,primecellTíTš apb_pclkDout-portsportendpointš]Þbetm@ed640000"arm,coresight-etm4xarm,primecellTídš apb_pclkDout-portsportendpointš^Þcetm@ed740000"arm,coresight-etm4xarm,primecellTítš apb_pclkD out-portsportendpointš_Þdfunnel@ed001000+arm,coresight-dynamic-funnelarm,primecellTíš apb_pclkout-portsportendpointš`Þein-ports+port@0TendpointšaÞ\port@1TendpointšbÞ]port@2TendpointšcÞ^port@3TendpointšdÞ_etf@ed002000 arm,coresight-tmcarm,primecellTí š apb_pclkin-portsportendpointšeÞ`out-portsportendpointšfÞifunnelarm,coresight-static-funnelš apb_pclkout-portsportendpointšgÞkin-ports+port@0TendpointšhÞ[port@1TendpointšiÞffunnel@ec031000+arm,coresight-dynamic-funnelarm,primecellTìš apb_pclkout-portsportendpointšjÞlin-ports+port@0TendpointškÞgetf@ec036000 arm,coresight-tmcarm,primecellTì`š apb_pclkin-portsportendpointšlÞjout-portsportendpointšmÞnreplicator arm,coresight-static-replicatorš apb_pclkin-portsportendpointšnÞmout-ports+port@0TendpointšoÞqport@1TendpointšpÞretr@ec033000 arm,coresight-tmcarm,primecellTì0š apb_pclkin-portsportendpointšqÞotpiu@ec032000!arm,coresight-tpiuarm,primecellTì š apb_pclkin-portsportendpointšrÞpgpio-rangeèÞspinmux@e896c000pinctrl-singleTè–Àð * H esstÞ4pmu_pmx_func  csi0_pwd_n_pmx_funcDcsi1_pwd_n_pmx_funcLisp0_pmx_funcXdhisp1_pmx_func\lppwr_key_pmx_func€Þti2c3_pmx_func,0Þ i2c4_pmx_func�”pcie_perstn_pmx_func\usbhub5734_pmx_func uart0_pmx_funcÌÐÞ$uart1_pmx_func °´¨¬Þ'uart2_pmx_func ¼ÀÈÄÞ)uart3_pmx_func ÜàäèÞ+uart4_pmx_func ìðôøÞ-uart5_pmx_func ÄȼÀÞ0uart6_pmx_func ÌÐÔØÞ2cam0_rst_pmx_funcÈcam1_rst_pmx_func$pinmux@ff37e000pinctrl-singleTÿ7à * HesÞ6sd_pmx_func0 ÞApinmux@ff3b6000pinctrl-singleTÿ;`0 * Hes Þ5ufs_pmx_funcspi3_pmx_func  Þ<pinmux@ff3fd000pinctrl-singleTÿ?Ð * HesÞ7sdio_pmx_func0 ÞFpinmux@fff11000pinctrl-singleTÿñ¨ * Hes*Þ8i2s2_pmx_func DHLPslimbus_pmx_func,0i2c0_pmx_funcÞi2c1_pmx_func Þi2c7_pmx_func$(Þ"pcie_pmx_func„ˆspi2_pmx_func Œ�”˜Þ:i2s0_pmx_func 48<@pinmux@e896c800pinconf-singleTè–È * pmu_cfg_func  “°Ë ði2c3_cfg_func8<“°ËðÞ!csi0_pwd_n_cfg_funcP“°Ëðcsi1_pwd_n_cfg_funcX“°Ëðisp0_cfg_funcdpt“°Ëðisp1_cfg_funchx|“°Ëðpwr_key_cfg_funcŒ“°ËðÞuuart1_cfg_func ´¸¼À“°ËðÞ(uart2_cfg_func ÈÌÐÔ“°ËðÞ*uart5_cfg_func ÈÌÐÔ“°ËðÞ1cam0_rst_cfg_funcÔ“°Ëðuart0_cfg_funcØÜ“°ËðÞ%uart6_cfg_func ØÜàä“°ËðÞ3uart3_cfg_func èìðô“°ËðÞ,uart4_cfg_func øü“°ËðÞ.cam1_rst_cfg_func0“°Ëðpinmux@ff3b6800pinconf-singleTÿ;h * ufs_cfg_func“°Ë0ðspi3_cfg_func  “°Ë ðÞ=pinmux@ff3fd800pinconf-singleTÿ?Ø * sdio_clk_cfg_func“°ËððÞGsdio_cfg_func( “°Ë€ðÞHpinmux@ff37e800pinconf-singleTÿ7è * sd_clk_cfg_func“°ËððÞBsd_cfg_func( “°Ë€ðÞCpinmux@fff11800pinconf-singleTÿñ¼ * i2c0_cfg_func “°ËðÞi2c1_cfg_func$(“°ËðÞi2c7_cfg_func,0“°ËðÞ#slimbus_cfg_func48“°Ëði2s0_cfg_func @DHL“°Ëði2s2_cfg_func PTX\“°Ëðpcie_cfg_func”˜“°Ëðspi2_cfg_func œ ¤¨“°Ë ðÞ;usb_cfg_func¬“°ËðÞaliasesé/soc/dwmmc1@ff37f000ï/soc/dwmmc2@ff3ff000õ/soc/serial@fdf02000ý/soc/serial@fdf00000/soc/serial@fdf03000 /soc/serial@ffd74000/soc/serial@fdf01000/soc/serial@fdf05000%/soc/serial@fff32000chosen-serial6:115200n8memory@0HmemoryTreserved-memory+Âramoops@32000000ramoopsT29ERreboot-mode-syscon@32100000sysconsimple-mfdT2reboot-modesyscon-reboot-mode^ewfUqwfU�wfUkeys gpio-keys)default7tupower� Îv HGPIO Power�tleds gpio-ledsuser_led1 Hgreen:user1 Î> ¨heartbeatuser_led2 Hgreen:user2 Î>¨noneuser_led3 Hgreen:user3 Îw¨mmc0user_led4 Hgreen:user4 Îw¾¨nonewlan_active_led Hyellow:wlan Î@¨phy0txÎoffbt_active_ledHblue:bt Î@ ¨hci0-powerÎoffpmic@fff34000hisilicon,hi6421v530-pmicTÿó@�~regulatorsLDO3 ÜVOUT3_1V85ëw@ !‘À xLDO9ÜVOUT9_1V8_2V95ë³ð 2Z  ðÞELDO11ÜVOUT11_1V8_2V95ë³ð 2Z  ðLDO15 ÜVOUT15_3V0ë³ð -ÆÀ 7 I xLDO16 ÜVOUT16_2V95ë³ð -ÆÀ hÞDwlan-en-1-8vregulator-fixedÜwlan-en-regulatorëw@ w@ ]x bp sÞIfirmwareopteelinaro,optee-tz=smc compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpudevice_typeregenable-methodnext-level-cachecpu-idle-statescapacity-dmips-mhzclocksoperating-points-v2#cooling-cellsdynamic-power-coefficientphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-ns#interrupt-cellsinterrupt-controllerinterruptsinterrupt-affinityranges#clock-cells#reset-cellshisi,rst-syscon#mbox-cellsmboxesclock-namesclock-frequencyresetspinctrl-namespinctrl-0statuslabeldata-rolepower-roletry-power-rolesource-pdossink-pdosop-sink-microwattremote-endpointadi,dsi-lanesdma-namesdmasenable-gpiosmax-speed#dma-cellsdma-channelsdma-requestsdma-channel-maskdma-no-ccidma-typeinterrupt-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namesnum-cscs-gpiosreg-namesbus-rangenum-lanesinterrupt-map-maskinterrupt-mapreset-gpiosfreq-table-hzreset-nameshisilicon,peripheral-sysconcard-detect-delaybus-widthcap-sd-highspeedsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104disable-wpcd-gpiosvmmc-supplyvqmmc-supplynon-removablebroken-cdcap-power-off-card#thermal-sensor-cellspolling-delaypolling-delay-passivesustainable-powerthermal-sensorstemperaturehysteresistripcontributioncooling-device#phy-cellshisilicon,pericrg-sysconhisilicon,pctrl-sysconhisilicon,eye-diagram-paramassigned-clocksassigned-clock-ratesphysphy-namesdr_modemaximum-speedphy_typesnps,dis-del-phy-power-chg-quirksnps,lfps_filter_quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirksnps,tx_de_emphasis_quirksnps,tx_de_emphasissnps,dis_enblslpm_quirksnps,gctl-reset-quirkusb-role-switchrole-switch-default-mode#pinctrl-single,gpio-range-cells#pinctrl-cells#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-rangepinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthmshc1mshc2serial0serial1serial2serial3serial4serial5serial6stdout-pathrecord-sizeconsole-sizeftrace-sizeoffsetmode-normalmode-bootloadermode-recoverywakeup-sourcelinux,codelinux,default-triggerpanic-indicatordefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-boot-onregulator-always-ongpiostartup-delay-usenable-active-high