Ð þí>8:( 9Ì)STMicroelectronics STM32H743i-EVAL board !st,stm32h743i-evalst,stm32h743interrupt-controller@e000e100!arm,armv7m-nvic,ARàá Vtimer@e000e010!arm,armv7m-systickRàà^okayeæ²€soc !simple-busu†timer@40000c00!st,stm32-timerR@ �2˜_timer@40002400!st,stm32-lptimerR@$˜�Ÿmux ^disabledpwm!st,stm32-pwm-lp« ^disabledtrigger@0!st,stm32-lptimer-triggerR ^disabledcounter!st,stm32-lptimer-counter ^disabledspi@40003800!st,stm32h7-spiR@8�$¶Ž˜� ^disabledspi@40003c00!st,stm32h7-spiR@<�3¶�˜Ž ^disabledserial@40004400!st,stm32h7-uartR@D�& ^disabled˜Œserial@40004800!st,stm32h7-uartR@H�' ^disabled˜‹serial@40004c00!st,stm32h7-uartR@L�4 ^disabled˜Ši2c@40005400!st,stm32f7-i2cR@T� ¶•˜ˆ^okay½ÇdefaultÕ¹ìi2c@40005800!st,stm32f7-i2cR@X�!"¶–˜‡ ^disabledi2c@40005c00!st,stm32f7-i2cR@\�HI¶—˜† ^disableddac@40007400!st,stm32h7-dac-coreR@t˜XŸpclk ^disableddac@1 !st,stm32-dacR ^disableddac@2 !st,stm32-dacR ^disabledserial@40011000!st,stm32h7-uartR@�%^okay˜œ½Çdefaultspi@40013000!st,stm32h7-spiR@0�#¶Ì˜š ^disabledspi@40013400!st,stm32h7-spiR@4�T¶Í˜™ ^disabledspi@40015000!st,stm32h7-spiR@P�U¶Ô˜˜ ^disableddma-controller@40020000 !st,stm32-dmaR@ � /˜A!, ^disabledVdma-controller@40020400 !st,stm32-dmaR@ �89:;<DEF˜@!, ^disabledVdma-router@40020800!st,stm32h7-dmamuxR@@9,€F˜Aadc@40022000!st,stm32h7-adc-coreR@ �˜}Ÿbus,A^okayR^Vadc@0!st,stm32h7-adcRu�^okayjadc@100!st,stm32h7-adcRu� ^disabledusb@40040000!st,stm32f7-hsotgR@�M˜|Ÿotgz‰  ›€€@@@@ ^okay½ Çdefaultª  ¯usb2-phy¹otgusb@40080000!st,stm32f4x9-fsotgR@�e˜{Ÿotg ^disableddisplay-controller@50001000!st,stm32-ltdcRP�XY¶c˜‚Ÿlcd ^disableddma-controller@52000000!st,stm32h7-mdmaRR�z˜99, mmc@52007000!arm,pl18xarm,primecellÁ1€RRp�1Øcmd_irq˜x Ÿapb_pclk¶ðèù 'Çdefaultopendrainsleep½  #-7BNZd^okaymmc@48022400!arm,pl18xarm,primecellÁ1€RH$�|Øcmd_irq˜~ Ÿapb_pclk¶)èù ' ^disabledinterrupt-controller@58000000!st,stm32h7-exti,ARX4� ()>LVsyscon@58000400!st,stm32-syscfgsysconRXVspi@58001400!st,stm32h7-spiRX�V¶å˜¤ ^disabledi2c@58001c00!st,stm32f7-i2cRX�_`¶ç˜£ ^disabledtimer@58002400!st,stm32-lptimerRX$˜¢Ÿmux ^disabledpwm!st,stm32-pwm-lp« ^disabledtrigger@1!st,stm32-lptimer-triggerR ^disabledcounter!st,stm32-lptimer-counter ^disabledtimer@58002800!st,stm32-lptimerRX(˜¡Ÿmux ^disabledpwm!st,stm32-pwm-lp« ^disabledtrigger@2!st,stm32-lptimer-triggerR ^disabledtimer@58002c00!st,stm32-lptimerRX,˜ Ÿmux ^disabledpwm!st,stm32-pwm-lp« ^disabledtimer@58003000!st,stm32-lptimerRX0˜ŸŸmux ^disabledpwm!st,stm32-pwm-lp« ^disabledregulator@58003c00!st,stm32-vrefbufRX<˜mpã`ˆ&%  ^disabledrtc@58004000!st,stm32h7-rtcRX@˜l  Ÿpclkrtc_ck  ° u� Ç^okayreset-clock-controller@58024400!st,stm32h743-rccst,stm32-rccRXDÑÞ ˜ÇVpower-config@58024800!st,stm32-power-configsysconRXHVadc@58026000!st,stm32h7-adc-coreRX`�˜€Ÿbus,A ^disabledVadc@0!st,stm32h7-adcRu� ^disabledethernet@40028000 !st,stm32-dwmacsnps,dwmac-4.10aR@€€ ëstmmaceth�=Ømacirq Ÿstmmacethmac-clk-txmac-clk-rx˜>=<õÿ ^disabled½Çdefaultrmiimdio0!snps,dwmac-mdioethernet-phy@0RVpinctrl@58020000!st,stm32h743-pinctrl †X0uÇVgpio@58020000.>R˜VJGPIOA,AW^gpio@58020400.>R˜UJGPIOB,AW^gpio@58020800.>R˜TJGPIOC,AW^ gpio@58020c00.>R ˜SJGPIOD,AW^0gpio@58021000.>R˜RJGPIOE,AW^@gpio@58021400.>R˜QJGPIOF,AW^Pgpio@58021800.>R˜PJGPIOG,AW^`gpio@58021c00.>R˜OJGPIOH,AW^pgpio@58022000.>R ˜NJGPIOI,AW^€gpio@58022400.>R$˜MJGPIOJ,AW^�gpio@58022800.>R(˜LJGPIOK,AW^ i2c1-0Vpinsjq~�rmii-0Vpins$jk m l $ %  !   �sdmmc1-b4-0V pinsj( ) * + , 2 �™qsdmmc1-b4-od-0V pins1j( ) * + , �™qpins2j2 �~qsdmmc1-b4-sleep-0Vpinsj()*+,2sdmmc1-dir-0V pins1 j& ' �™©pins2j©sdmmc1-dir-sleep-0Vpinsj&'sdmmc2-b4-0pinsj    6 7 �™qsdmmc2-b4-od-0pins1j    6 �™qpins2j7 �~qsdmmc2-b4-sleep-0pinsj67spi1-0pins1jq™�pins2jiquart4-0pins1j q™�pins2j‰ qusart1-0Vpins1jq™�pins2jqusart2-0pins1j5q™�pins2j6qusart3-0pins1j<q™�pins2j;qusbotg-hs-0V pins0jt ‹          q™�clocksclk-hseÑ !fixed-clocke}x@Vclk-lseÑ !fixed-clocke€Vi2s_ckinÑ !fixed-clockeVchosen¶root=/dev/ram¿serial0:115200n8memory@d0000000ËmemoryRÐaliases×/soc/serial@40011000regulator-vdda!regulator-fixedßvddap2Z ˆ2Z îVregulator-v2v9_sd!regulator-fixedßv2v9_sdp,@ ˆ,@ îVusb-phy!usb-nop-xceiv˜; Ÿmain_clkV  #address-cells#size-cellsmodelcompatibleinterrupt-controller#interrupt-cellsregphandlestatusclock-frequencyinterrupt-parentrangesinterruptsclocksclock-names#pwm-cellsresetspinctrl-0pinctrl-namesi2c-scl-rising-time-nsi2c-scl-falling-time-ns#io-channel-cells#dma-cellsst,mem2memdma-requestsdma-channelsdma-mastersvdda-supplyvref-supplyst,adc-channelsg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-sizephysphy-namesdr_modearm,primecell-periphidinterrupt-namescap-sd-highspeedcap-mmc-highspeedmax-frequencypinctrl-1pinctrl-2broken-cdst,sig-dirst,neg-edgest,use-ckinbus-widthvmmc-supplyregulator-min-microvoltregulator-max-microvoltassigned-clocksassigned-clock-parentsst,syscfg#clock-cells#reset-cellsreg-namesst,sysconsnps,pblphy-modephy-handlepins-are-numberedgpio-controller#gpio-cellsst,bank-namengpiosgpio-rangespinmuxbias-disabledrive-open-drainslew-ratedrive-push-pullbias-pull-upbootargsstdout-pathdevice_typeserial0regulator-nameregulator-always-on#phy-cells