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Ph pwm@ff680000rockchip,rk3288-pwmÿÿhCÿdefault Q;_9okayh§pwm@ff680010rockchip,rk3288-pwmÿÿhCÿdefault R;_9okayhœpwm@ff680020rockchip,rk3288-pwmÿÿh Cÿdefault S;_ 9disabledpwm@ff680030rockchip,rk3288-pwmÿÿh0Cÿdefault T;_ 9disabledsram@ff700000 mmio-sramÿÿp€�ÿp€smp-sram@0rockchip,rk3066-smp-sramÿsram@ff720000#rockchip,rk3288-pmu-srammmio-sramÿÿrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdÿÿshpower-controller!rockchip,rk3288-power-controllerN–h¦ hhpower-domain@9ÿ È;ÊÍÈÌÅÆ¾¿ÔÕÖÙÑÒchgfdehilkj$bUVWXYZ[\]Npower-domain@11ÿ ;Ïopb^_Npower-domain@12ÿ ;ÐÜb`Npower-domain@13ÿ ;ÀbabNreboot-modesyscon-reboot-modei”pRBÃ|RBÊRBà šRBÃsyscon@ff740000rockchip,rk3288-sgrfsysconÿÿtclock-controller@ff760000rockchip,rk3288-cruÿÿv; xin24m¥Eº¦H–ÑÝjÒÞk$³#g¸€ׄÍeá£ðÑ€xhÀá£ðÑ€xhÀhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdÿÿwhEedp-phyrockchip,rk3288-dp-phy;h24mÈ9okayhxio-domains"rockchip,rk3288-io-voltage-domain9okayÓ5Ýèö5 5 c  ,d 9usbphyrockchip,rk3288-usb-phy9okayusb-phy@320Èÿ ;]phyclkº… -phy-resethHusb-phy@334Èÿ4;^phyclkºˆ -phy-resethFusb-phy@348ÈÿH;_phyclkº‹ -phy-resethGwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdtÿÿ€;p ºO9okaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdifÿÿ‹ G;TÐ mclkhclk‡eŒtx º6ÿdefault f¥E 9disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2sÿÿ‰ G º5;RÎi2s_clki2s_hclk‡eeŒtxrxÿdefault g X s9okayhŸcrypto@ff8a0000rockchip,rk3288-cryptoÿÿŠ@ º0 ;ÇÍ}Áaclkhclksclkapb_pclk® -crypto-rstiommu@ff900800rockchip,iommuÿÿ�@ º;ÊÔ aclkiface � 9disablediommu@ff914000rockchip,iommu ÿÿ‘@ÿ‘P º;ÍÕ aclkiface � š 9disabledrga@ff920000rockchip,rk3288-rgaÿÿ’€ º;ÈÖjaclkhclksclk µh ilm -coreaxiahbvop@ff930000rockchip,rk3288-vop ÿÿ“œÿ“ º;žÑaclk_vopdclk_vophclk_vop µh def -axiahbdclk Ãi9okayporth endpoint@0ÿ Êjhendpoint@1ÿ Êkhzendpoint@2ÿ Êlhsendpoint@3ÿ Êmhviommu@ff930300rockchip,iommuÿÿ“ º;ÅÑ aclkiface µh  �9okayhivop@ff940000rockchip,rk3288-vop ÿÿ”œÿ” º;Æ¿Òaclk_vopdclk_vophclk_vop µh °±² -axiahbdclk Ãn9okayporth endpoint@0ÿ Êoh€endpoint@1ÿ Êph{endpoint@2ÿ Êqhtendpoint@3ÿ Êrhwiommu@ff940300rockchip,iommuÿÿ” º;ÆÒ aclkiface µh  �9okayhnmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsiÿÿ–@ º;~d refpclk µh ¥E 9disabledportsportendpoint@0ÿ Êshlendpoint@1ÿ Êthqlvds@ff96c000rockchip,rk3288-lvdsÿÿ–À@;g pclk_lvdsÿlcdc u µh ¥E 9disabledportsport@0ÿendpoint@0ÿ Êvhmendpoint@1ÿ Êwhrdp@ff970000rockchip,rk3288-dpÿÿ—@ ºb;icdppclk xdp µh o-dp¥E9okayÿdefault yportsport@0ÿendpoint@0ÿ Êzhkendpoint@1ÿ Ê{hpport@1ÿendpoint@0ÿ Ê|h«hdmi@ff980000rockchip,rk3288-dw-hdmiÿÿ˜Ò G¥E ºg;hmniahbisfrcec µh 9okayÿdefaultunwedge }{~h¢portsportendpoint@0ÿ Êhjendpoint@1ÿ Ê€hovideo-codec@ff9a0000rockchip,rk3288-vpuÿÿšº   ûvepuvdpu;ÐÜ aclkhclk Ã� µh iommu@ff9a0800rockchip,iommuÿÿš º ;ÐÜ aclkiface � µh h�iommu@ff9c0440rockchip,iommu ÿÿœ@@ÿœ€@ ºo;ÏÛ aclkiface � 9disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760ÿÿ£$º ûjobmmugpu;À ‚ µh 9okay ÚƒhBopp-table-1operating-points-v2h‚opp-100000000{õá‚~ðopp-200000000{ ë‚~ðopp-300000000{ᣂB@opp-400000000{ׄ‚Èàopp-600000000{#ÃF‚Ðqos@ffaa0000rockchip,rk3288-qossysconÿÿª haqos@ffaa0080rockchip,rk3288-qossysconÿÿª€ hbqos@ffad0000rockchip,rk3288-qossysconÿÿ­ hVqos@ffad0100rockchip,rk3288-qossysconÿÿ­ hWqos@ffad0180rockchip,rk3288-qossysconÿÿ­€ hXqos@ffad0400rockchip,rk3288-qossysconÿÿ­ hYqos@ffad0480rockchip,rk3288-qossysconÿÿ­€ hZqos@ffad0500rockchip,rk3288-qossysconÿÿ­ hUqos@ffad0800rockchip,rk3288-qossysconÿÿ­ h[qos@ffad0880rockchip,rk3288-qossysconÿÿ­€ h\qos@ffad0900rockchip,rk3288-qossysconÿÿ­ h]qos@ffae0000rockchip,rk3288-qossysconÿÿ® h`qos@ffaf0000rockchip,rk3288-qossysconÿÿ¯ h^qos@ffaf0080rockchip,rk3288-qossysconÿÿ¯€ h_dma-controller@ffb20000arm,pl330arm,primecellÿÿ²@ºßê;Á apb_pclkheefuse@ffb40000rockchip,rk3288-efuseÿÿ´ ;q pclk_efusecpu-id@7ÿcpu_leakage@17ÿinterrupt-controller@ffc01000 arm,gic-400 æ û@ÿÿÀÿÀ ÿÀ@ ÿÀ`  º hpinctrlrockchip,rk3288-pinctrl¥Eæ�ÿdefaultsleep „…†‡ˆ{„…†‰Šgpio@ff750000rockchip,gpio-bankÿÿu ºQ;@   æ ûç (PMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LAP_LID_INT_LEC_IN_RWAC_PRESENT_APRECOVERY_SW_LOTP_OUTHOST1_PWR_ENUSBOTG_PWREN_HAP_WARM_RESET_HnFALUT2I2C0_SDA_PMICI2C0_SCL_PMICSUSPEND_LUSB_INTh2gpio@ff780000rockchip,gpio-bankÿÿx ºR;A   æ ûgpio@ff790000rockchip,gpio-bankÿÿy ºS;B   æ ûM (CONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_LBL_PWR_ENAVDD_1V8_DISP_ENh•gpio@ff7a0000rockchip,gpio-bankÿÿz ºT;C   æ û‚ (FLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio@ff7b0000rockchip,gpio-bankÿÿ{ ºU;D   æ û³ (UART0_RXDUART0_TXDUART0_CTSUART0_RTSSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEhgpio@ff7c0000rockchip,gpio-bankÿÿ| ºV;E   æ ûA (SPI0_CLKSPI0_CS0SPI0_TXDSPI0_RXDVCC50_HDMI_ENhšgpio@ff7d0000rockchip,gpio-bankÿÿ} ºW;F   æ û° (I2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HALS_INTINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETSDMMC_D0SDMMC_D1SDMMC_D2SDMMC_D3SDMMC_CLKSDMMC_CMDhOgpio@ff7e0000rockchip,gpio-bankÿÿ~ ºX;G   æ ûâ (LCDC_BLPWM_LOGBL_ENTRACKPAD_INTTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LEC_INTCPU_NMIDVSOKSDMMC_WPEDP_HPDDVS1nFALUT1LCD_ENDVS2VCC5V_GOOD_HI2C4_SDA_TPI2C4_SCL_TPI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDh gpio@ff7f0000rockchip,gpio-bankÿÿ ºY;H   æ û^ (RAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 8‹hdmi-cec-c7 8‹hdmi-ddc 8‹‹h}hdmi-ddc-unwedge 8Œ‹h~vcc50-hdmi-en 8‹h›pcfg-output-low FhŒpcfg-pull-up Qh�pcfg-pull-down ^h�pcfg-pull-none mh‹pcfg-pull-none-12ma m z h‘suspendglobal-pwroff 8‹h†ddrio-pwroff 8‹h…ddr0-retention 8�h„ddr1-retention 8�suspend-l-wake 8Œh‡suspend-l-sleep 8Žh‰edpedp-hpd 8 �hyi2c0i2c0-xfer 8‹‹hIi2c1i2c1-xfer 8‹‹h/i2c2i2c2-xfer 8 ‹ ‹hNi2c3i2c3-xfer 8‹‹h0i2c4i2c4-xfer 8‹‹h1i2c5i2c5-xfer 8‹‹h6i2s0i2s0-bus` 8‹‹‹‹‹‹hglcdclcdc-ctl@ 8‹‹‹‹husdmmcsdmmc-clk 8�hsdmmc-cmd 8�hsdmmc-cd 8�sdmmc-bus1 8�sdmmc-bus4@ 8����hsdmmc-cd-disabled 8‹hsdmmc-cd-pin 8‹hsdio0sdio0-bus1 8�sdio0-bus4@ 8����hsdio0-cmd 8�hsdio0-clk 8�hsdio0-cd 8�sdio0-wp 8�sdio0-pwr 8�sdio0-bkpwr 8�sdio0-int 8�wifienable-h 8‹h—bt-enable-l 8‹bt-host-wake 8�bt-host-wake-l 8‹hbt-dev-wake-sleep 8ŒhŠbt-dev-wake-awake 8Žhˆbt-dev-wake 8‹sdio1sdio1-bus1 8�sdio1-bus4@ 8����sdio1-cd 8�sdio1-wp 8�sdio1-bkpwr 8�sdio1-int 8�sdio1-cmd 8�sdio1-clk 8‹sdio1-pwr 8 �emmcemmc-clk 8�hemmc-cmd 8�hemmc-pwr 8 �emmc-bus1 8�emmc-bus4@ 8����emmc-bus8€ 8��������h emmc-reset 8 ‹h”spi0spi0-clk 8 �h"spi0-cs0 8 �h%spi0-tx 8�h#spi0-rx 8�h$spi0-cs1 8�spi1spi1-clk 8 �h'spi1-cs0 8 �h*spi1-rx 8�h)spi1-tx 8�h(spi2spi2-cs1 8�spi2-clk 8�h+spi2-cs0 8�h.spi2-rx 8�h-spi2-tx 8 �h,uart0uart0-xfer 8�‹h7uart0-cts 8�h8uart0-rts 8‹h9uart1uart1-xfer 8� ‹h:uart1-cts 8 �uart1-rts 8 ‹uart2uart2-xfer 8�‹h;uart3uart3-xfer 8�‹h<uart3-cts 8 �uart3-rts 8 ‹uart4uart4-xfer 8�‹h=uart4-cts 8 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™hMvcc33-sysregulator-fixed |vcc33_sys‹Ÿ±2Z É2Z  Ù˜hvcc50-hdmiregulator-fixed |vcc50_hdmi‹Ÿ ÙM ä ÷šÿdefault ›vdd-logicpwm-regulator |vdd_logic üœÊ  { ”‹Ÿ±~ðÉ™pá sound!rockchip,rockchip-audio-max98090ÿdefault �ž 3VEYRON-I2S BŸ Z  oO …O  œ¡ ³¢backlight-regulatorregulator-fixed ä ÷• ÿdefault £|backlight_regulator Ù Ç:˜h¨panel-regulatorregulator-fixed ä ÷ ÿdefault ¤|panel_regulator Ùh©vcc18-lcdregulator-fixed ä ÷• ÿdefault ¥ |vcc18_lcd‹Ÿ Ùbacklightpwm-backlight Øÿ ê÷ €  ÿdefault ¦ ü§B@ '  <  M¨hªpanelinnolux,n116bge9okay M© Zªpanel-timing—l÷ dV lˆ y< … � œ ¤ ±  ½  Çportsportendpoint Ê«h|gpio-charger gpio-charger Ômains ‚2ÿdefault ¬lid-switch gpio-keysÿdefault ­switch-lid ¡Lid ‚2º § á ²vccsysregulator-fixed|vccsysŸ‹h˜vcc5-host1-regulatorregulator-fixed ä ÷2 ÿdefault ® |vcc5_host1‹Ÿvcc5v-otg-regulatorregulator-fixed ä ÷2 ÿdefault ¯ |vcc5_host2‹Ÿ #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2i2c20interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplydisable-wppinctrl-namespinctrl-0cap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablemarvell,wakeup-pinmmc-hs200-1_8v#io-channel-cellsdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasvcc-supplywakeup-sourcereg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplydvs-gpiosregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codecstartup-delay-usbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplybacklighthactivehfront-porchhback-porchhsync-lenhsync-activevactivevfront-porchvback-porchvsync-lenvsync-activecharger-typelinux,input-type