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Db„regulatorsDCDC_REG1´vdd_armÃ×é q° qb regulator-state-mem.DCDC_REG2´vdd_gpuÃ×é 5Ðqburegulator-state-mem.DCDC_REG3 ´vcc135_ddrÃ×regulator-state-memGDCDC_REG4´vcc_18Ã×éw@w@bregulator-state-memG_w@LDO_REG3´vdd_10Ã×éB@B@regulator-state-memG_B@LDO_REG7 ´vdd10_lcdÃ×éB@B@{regulator-state-mem.SWITCH_REG1 ´vcc33_lcdÃ×bXregulator-state-mem.SWITCH_REG2Ã× ´vcc18_hdmi{i2c@ff660000rockchip,rk3288-i2cùÿf ´=üi2c5N‘defaultŸE3okay‘† ‡2Ÿ pwm@ff680000rockchip,rk3288-pwmùÿhš‘defaultŸF5_ 3disabledpwm@ff680010rockchip,rk3288-pwmùÿhš‘defaultŸG5_3okaybˆpwm@ff680020rockchip,rk3288-pwmùÿh š‘defaultŸH5_ 3disabledpwm@ff680030rockchip,rk3288-pwmùÿh0š‘defaultŸI5_ 3disabledsram@ff700000 mmio-sramùÿp€Šÿp€smp-sram@0rockchip,rk3066-smp-sramùsram@ff720000#rockchip,rk3288-pmu-srammmio-sramùÿrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdùÿsbpower-controller!rockchip,rk3288-power-controller¥òh b\power-domain@9ù È5ÊÍÈÌÅÆ¾¿ÔÕÖÙÑÒchgfdehilkj$¹JKLMNOPQR¥power-domain@11ù 5Ïop¹ST¥power-domain@12ù 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Ót Þd:gpio-restart gpio-restart ñ? ‘defaultŸ� ðÈemmc-pwrseqmmc-pwrseq-emmcŸ‚‘default ùƒ bsdio-pwrseqmmc-pwrseq-simple5„ üext_clock‘defaultŸ… ù.b vcc-5vregulator-fixed´vcc_5vÃ×éLK@LK@b†vcc33-sysregulator-fixed ´vcc33_sysÃ×é2Z 2Z  †bvcc50-hdmiregulator-fixed ´vcc50_hdmiÃ× †  #D‘defaultŸ‡vdd-logicpwm-regulator ´vdd_logic (ˆÊ - 8{ L”Ã×é~ð™p vcc33_ioregulator-fixed ´vcc33_ioÃ× bCvcc5-host2-regulatorregulator-fixed  #? ‘defaultŸ‰ ´vcc5_host2Ã× #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedrockchip,default-sample-phasedisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesrx-sample-delay-nsspi-max-frequencyi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreg-shiftreg-io-widthhost-wakeup-gpiosshutdown-gpiosdevice-wakeup-gpiosmax-speedbrcm,bt-pcm-int-params#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplydvs-gpiosregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltregulator-suspend-mem-disabled#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unit