Ð þíb 8[à()[¨,radxa,rockrockchip,rk3188 7Radxa Rockaliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/serial@10124000h/serial@10126000p/serial@20064000x/serial@20068000€/spi@20070000…/spi@20074000Š/mmc@10214000oscillator ,fixed-clock�n6Ÿ¬xin24m¿<gpu@10090000",rockchip,rk3188-maliarm,mali-400Ç ËÅÅ ÒbuscoreÞÅîõáx okayx 5gpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3,video-codec@10104000(,rockchip,rk3188-vpurockchip,rk3066-vpuÇ@   vepuvdpu ËÎØÍ×(Òaclk_vdpuhclk_vdpuaclk_vepuhclk_vepu,cache-controller@10138000,arm,pl310-cacheÇ€:H¿4scu@1013c000,arm,cortex-a9-scuÇÀglobal-timer@1013c200,arm,cortex-a9-global-timerÇ   Ë  disabledlocal-timer@1013c600,arm,cortex-a9-twd-timerÇÆ   Ëinterrupt-controller@1013d000,arm,cortex-a9-gicTiÇÐÁ¿serial@10124000&,rockchip,rk3188-uartsnps,dw-apb-uartÇ@ "z„Òbaudclkapb_pclkË@L okay‘defaultŸserial@10126000&,rockchip,rk3188-uartsnps,dw-apb-uartÇ` #z„Òbaudclkapb_pclkËAM okay‘defaultŸqos@1012d000,rockchip,rk3066-qossysconÇÐ ¿qos@1012e000,rockchip,rk3066-qossysconÇà ¿qos@1012f000,rockchip,rk3066-qossysconÇð ¿qos@1012f080,rockchip,rk3066-qossysconÇð€ ¿qos@1012f100,rockchip,rk3066-qossysconÇñ ¿qos@1012f180,rockchip,rk3066-qossysconÇñ€ ¿qos@1012f200,rockchip,rk3066-qossysconÇò qos@1012f280,rockchip,rk3066-qossysconÇò€ ¿usb@10180000,rockchip,rk3066-usbsnps,dwc2Ç ËÃÒotg©otg±ÃÒ€€@@ á æusb2-phy okayusb@101c0000 ,snps,dwc2Ç ËÉÒotg©hostá æusb2-phy okayethernet@10204000,rockchip,rk3188-emacÇ @< ðËÄD Òhclkmacrefýdrmii okay  ‘default Ÿ mdioethernet-phy@0Ç¿ mmc@10214000,rockchip,rk2928-dw-mshcÇ!@ ËÀHÒbiuciu$rx-tx.Q9reset okay‘defaultŸEQ[m~mmc@10218000,rockchip,rk2928-dw-mshcÇ!€ ËÁIÒbiuciu$rx-tx.R9reset  disabledmmc@1021c000,rockchip,rk2928-dw-mshcÇ!À ËÂJÒbiuciu$rx-tx.S9reset  disablednand-controller@10500000,rockchip,rk2928-nfcÇP@ ËÓÒahb  disabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfdÇ @¿=reboot-mode,syscon-reboot-mode‰@�RBÜRBêRBà ºRBÃpower-controller!,rockchip,rk3188-power-controllerÆ¿power-domain@7ÇhËÃľ¿ÍÎOÊÐÈÑÉÒÚÆpower-domain@6Ç ËÎÍØ×ÚÆpower-domain@8ÇËÅÚÆgrf@20008000&,rockchip,rk3188-grfsysconsimple-mfdÇ €¿io-domains",rockchip,rk3188-io-voltage-domain  disabledusbphy,rockchip,rk3188-usb-phy okayusb-phy@10cÇ ËQÒphyclkŸá¿usb-phy@11cÇËRÒphyclkŸá¿dma-controller@20018000,arm,pl330arm,primecellÇ €@ì÷ËÀ Òapb_pclk¿:dma-controller@2001c000,arm,pl330arm,primecellÇ À@ì÷ËÀ Òapb_pclk  disabledi2c@2002d000,rockchip,rk3188-i2cÇ Ð (ðÒi2cËP  disabled‘defaultŸi2c@2002f000,rockchip,rk3188-i2cÇ ð )ðËQÒi2c okay‘defaultŸ�€rtc@51,haoyu,hym8563ÇQ ‘defaultŸŸ¬xin32kact8846@5a,active-semi,act8846ÇZ okay)‘defaultŸ A!L!W!b!m"y!…!regulatorsREG1‘VCC_DDR O€¸O€ÐREG2‘VDD_LOG B@¸B@ÐREG3‘VDD_ARM  Yø¸™pп6REG4‘VCC_IO 2Z ¸2Z Ð¿"REG5‘VDD_10 B@¸B@ÐREG6 ‘VDD_HDMI &% ¸&% ÐREG7‘VCC_18 w@¸w@ÐREG8‘VCCA_33 2Z ¸2Z ÐREG9 ‘VCC_RMII 2Z ¸2Z ¿ REG10 ‘VCCIO_WL 2Z ¸2Z ÐREG11 ‘VCC18_IO w@¸w@ÐREG12‘VCC_28 *¹€¸*¹€Ðpwm@20030000,rockchip,rk2928-pwmÇ äËF  disabled‘defaultŸ#pwm@20030010,rockchip,rk2928-pwmÇ äËF okay‘defaultŸ$watchdog@2004c000 ,rockchip,rk3188-wdtsnps,dw-wdtÇ ÀËK 3 okaypwm@20050020,rockchip,rk2928-pwmÇ  äËG okay‘defaultŸ%pwm@20050030,rockchip,rk2928-pwmÇ 0äËG okay‘defaultŸ&i2c@20056000,rockchip,rk3188-i2cÇ ` *ðËRÒi2c  disabled‘defaultŸ'i2c@2005a000,rockchip,rk3188-i2cÇ   +ðËSÒi2c  disabled‘defaultŸ(i2c@2005e000,rockchip,rk3188-i2cÇ à 4ðËTÒi2c  disabled‘defaultŸ)serial@20064000&,rockchip,rk3188-uartsnps,dw-apb-uartÇ @ $z„Òbaudclkapb_pclkËBN okay‘defaultŸ*serial@20068000&,rockchip,rk3188-uartsnps,dw-apb-uartÇ € %z„Òbaudclkapb_pclkËCO okay‘defaultŸ+saradc@2006c000,rockchip,saradcÇ À ïËGJÒsaradcapb_pclkW 9saradc-apb  disabledspi@20070000(,rockchip,rk3188-spirockchip,rk3066-spiËEHÒspiclkapb_pclk &Ç   $txrx  disabled‘defaultŸ,-./spi@20074000(,rockchip,rk3188-spirockchip,rk3066-spiËFIÒspiclkapb_pclk 'Ç @  $txrx  disabled‘defaultŸ0123dma-controller@20078000,arm,pl330arm,primecellÇ €@ì÷ËÁ Òapb_pclk¿cpusrockchip,rk3066-smpcpu@0cpu,arm,cortex-a94Ç,œ@Ë:5N6cpu@1cpu,arm,cortex-a94Ç:5N6cpu@2cpu,arm,cortex-a94Ç:5N6cpu@3cpu,arm,cortex-a94Ç:5N6opp-table-0,operating-points-v2Y¿5opp-312000000d˜¾k Yøyœ@opp-504000000d nkHopp-600000000d#ÃFk~ðŠopp-816000000d0£,kà˜opp-1008000000d<Ükg8opp-1200000000dG†ŒkŒ0opp-1416000000dTfrkÐopp-1608000000d_Ø"k™pdisplay-subsystem,rockchip,display-subsystem–78sram@10080000 ,mmio-sramÇ€ œ€smp-sram@0,rockchip,rk3066-smp-sramÇPvop@1010c000,rockchip,rk3188-vopÇÀ  ËþÍÒaclk_vopdclk_vophclk_vop,def 9axiahbdclk  disabledport¿7vop@1010e000,rockchip,rk3188-vopÇà ËÄ¿ÎÒaclk_vopdclk_vophclk_vop,ghi 9axiahbdclk  disabledport¿8timer@2000e000,,rockchip,rk3188-timerrockchip,rk3288-timerÇ à  .ËEW Òpclktimertimer@200380a0,,rockchip,rk3188-timerrockchip,rk3288-timerÇ €   @ËBZ Òpclktimeri2s@1011a000(,rockchip,rk3188-i2srockchip,rk3066-i2sÇ    ‘defaultŸ9ËKÆÒi2s_clki2s_hclk::$txrx£¾Ø  disabledsound@1011e000,,rockchip,rk3188-spdifrockchip,rk3066-spdifÇà ØËNÅ Òmclkhclk:$tx  ‘defaultŸ; okay¿Aclock-controller@20000000,rockchip,rk3188-cruÇ Ë<Òxin24mðŸé¿efuse@20010000,rockchip,rk3188-efuseÇ @Ë[ Òpclk_efusecpu_leakage@17Çpinctrl,rockchip,rk3188-pinctrlðö=œgpio@2000a000,rockchip,rk3188-gpio-bank0Ç   6ËUTi¿gpio@2003c000,rockchip,gpio-bankÇ À 7ËVTigpio@2003e000,rockchip,gpio-bankÇ à 8ËWTi¿Dgpio@20080000,rockchip,gpio-bankÇ  9ËXTi¿pcfg-pull-up¿?pcfg-pull-down,pcfg-pull-none;¿>emmcemmc-clkH>emmc-cmdH?emmc-rstH>emacemac-xfer€H>>>>>>>>¿ emac-mdio H>>¿ i2c0i2c0-xfer H>>¿i2c1i2c1-xfer H>>¿i2c2i2c2-xfer H>>¿'i2c3i2c3-xfer H>>¿(i2c4i2c4-xfer H>>¿)lcdc1lcdc1-dclkH>lcdc1-denH>lcdc1-hsyncH>lcdc1-vsyncH>lcdc1-rgb24€H>>>>>>>>> > > > > >>>>>>>>>>>pwm0pwm0-outH>¿#pwm1pwm1-outH>¿$pwm2pwm2-outH>¿%pwm3pwm3-outH>¿&spi0spi0-clkH?¿,spi0-cs0H?¿/spi0-txH?¿-spi0-rxH?¿.spi0-cs1H?spi1spi1-clkH?¿0spi1-cs0H?¿3spi1-rxH?¿2spi1-txH?¿1spi1-cs1H?uart0uart0-xfer H?>¿uart0-ctsH>uart0-rtsH>uart1uart1-xfer H?>¿uart1-ctsH>uart1-rtsH>uart2uart2-xfer H? >¿*uart3uart3-xfer H ? >¿+uart3-ctsH >uart3-rtsH >sd0sd0-clkH>¿sd0-cmdH>¿sd0-cdH>¿sd0-wpH >sd0-pwrH>sd0-bus-width1H>sd0-bus-width4@H>>>>¿sdmmc-pwrH>¿Fsd1sd1-clkH>sd1-cmdH>sd1-cdH>sd1-wpH>sd1-bus-width1H>sd1-bus-width4@H>>>>i2s0i2s0-bus`H>>>>>>¿9spdifspdif-txH>¿;pcfg-output-lowV¿@act8846act8846-dvs0-ctlH@¿ hym8563rtc-intH?¿lan8720aphy-intH?¿ ir-receiverir-recv-pinH >¿Cusbhost-vbus-drvH>¿Gotg-vbus-drvH>¿Ememory@60000000memoryÇ`€gpio-keys ,gpio-keysakey-power lrt}GPIO Key Powerƒ”¢dgpio-leds ,gpio-ledsled-0}rock:green:user1 l ´offled-1}rock:blue:user2 l´offled-2}rock:red:power l´offsound,simple-audio-cardÂSPDIFsimple-audio-card,dai-link@1cpuÙAcodecÙBspdif-out,linux,spdif-ditØ¿Bir-receiver,gpio-ir-receiver l ‘defaultŸCusb-otg-regulator,regulator-fixedã öD‘defaultŸE ‘otg-vbus LK@¸LK@Ðûsdmmc-regulator,regulator-fixed ‘sdmmc-supply 2Z ¸2Z  ö‘defaultŸF † "¿usb-host-regulator,regulator-fixedã ö‘defaultŸG ‘host-pwr LK@¸LK@Ðûvsys-regulator,regulator-fixed‘vsys LK@¸LK@û¿! #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4serial0serial1serial2serial3spi0spi1mmc0clock-frequency#clock-cellsclock-output-namesphandleregclocksclock-namesassigned-clocksassigned-clock-ratesresetsstatusinterruptsinterrupt-namespower-domainscache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthpinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modephyphy-supplydmasdma-namesfifo-depthreset-namesvmmc-supplybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qos#phy-cells#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstsystem-power-controllervp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-on#pwm-cells#io-channel-cellsenable-methoddevice_typenext-level-cacheclock-latencyoperating-points-v2cpu-supplyopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsrangesrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disablerockchip,pinsoutput-lowautorepeatgpioslinux,codelabellinux,input-typewakeup-sourcedebounce-intervaldefault-statesimple-audio-card,namesound-daienable-active-highgpioregulator-boot-onstartup-delay-usvin-supply