Ð þíkÌ8eÜ(ðe¤(,chipspark,rayeager-px2rockchip,rk3066a 7Rayeager PX2aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/serial@10124000h/serial@10126000p/serial@20064000x/serial@20068000€/spi@20070000…/spi@20074000Š/mmc@10214000�/mmc@10218000”/mmc@1021c000oscillator ,fixed-clock™n6©¶xin24mÉUgpu@10090000",rockchip,rk3066-maliarm,mali-400Ñ ÕÅÅ ÜbuscoreèÅøõá x disabledx5&gpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu36video-codec@10104000,rockchip,rk3066-vpuÑ@   &vepuvdpu ÕÎØÍ×(Üaclk_vdpuhclk_vdpuaclk_vepuhclk_vepu6cache-controller@10138000,arm,pl310-cacheÑ€DRÉHscu@1013c000,arm,cortex-a9-scuÑÀglobal-timer@1013c200,arm,cortex-a9-global-timerÑ   Õ disabledlocal-timer@1013c600,arm,cortex-a9-twd-timerÑÆ   Õinterrupt-controller@1013d000,arm,cortex-a9-gic^sÑÐÁÉserial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uartÑ@ "„ŽÜbaudclkapb_pclkÕ@Lokay› txrxªdefault ¸serial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uartÑ` #„ŽÜbaudclkapb_pclkÕAM disabled› txrxªdefault¸qos@1012d000,rockchip,rk3066-qossysconÑÐ É)qos@1012e000,rockchip,rk3066-qossysconÑà É(qos@1012f000,rockchip,rk3066-qossysconÑð É"qos@1012f080,rockchip,rk3066-qossysconÑð€ É$qos@1012f100,rockchip,rk3066-qossysconÑñ É&qos@1012f180,rockchip,rk3066-qossysconÑñ€ É#qos@1012f200,rockchip,rk3066-qossysconÑò É%qos@1012f280,rockchip,rk3066-qossysconÑò€ É'usb@10180000,rockchip,rk3066-usbsnps,dwc2Ñ ÕÃÜotgÂotgÊÜ뀀@@ ú  ÿusb2-phyokayusb@101c0000 ,snps,dwc2Ñ ÕÉÜotgÂhostú  ÿusb2-phyokayªdefault¸ ethernet@10204000,rockchip,rk3066-emacÑ @<  ÕÄD Ühclkmacrefd rmiiokay)-ªdefault ¸mdioethernet-phy@0Ñ 8Émmc@10214000,rockchip,rk2928-dw-mshcÑ!@ ÕÀHÜbiuciu› rx-txD QOresetokay™úð€[úð€ªdefault¸is~Šœmmc@10218000,rockchip,rk2928-dw-mshcÑ!€ ÕÁIÜbiuciu› rx-txD ROresetokayªdefault ¸i­~mmc@1021c000,rockchip,rk2928-dw-mshcÑ!À ÕÂJÜbiuciu› rx-txD SOresetokayiŠ­ªdefault ¸ ~!»!nand-controller@10500000,rockchip,rk2928-nfcÑP@ ÕÓÜahb disabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfdÑ 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 txrxokayªdefault¸@ABCspi@20074000,rockchip,rk3066-spiÕFIÜspiclkapb_pclk 'Ñ @›   txrx disabledªdefault¸DEFGdma-controller@20078000,arm,pl330arm,primecellÑ €@+6QÕÁ Üapb_pclkÉcpuslrockchip,rk3066-smpcpu@0zcpu,arm,cortex-a9†HÑ8—›@Ö O€íØa€*ˆ s€*ˆ 'ÀÈà°ÀÈàÂÀg8¨œ@Õ¶Icpu@1zcpu,arm,cortex-a9†HѶIdisplay-subsystem,rockchip,display-subsystemÁJKsram@10080000 ,mmio-sramÑ Çsmp-sram@0,rockchip,rk3066-smp-sramÑPvop@1010c000,rockchip,rk3066-vopÑÀœ  ÕþÍÜaclk_vopdclk_vophclk_vop6 def Oaxiahbdclk disabledportÉJendpoint@0ÑÎLÉPvop@1010e000,rockchip,rk3066-vopÑàœ ÕÄ¿ÎÜaclk_vopdclk_vophclk_vop6 ghi Oaxiahbdclk disabledportÉKendpoint@0ÑÎMÉQhdmi@10116000,rockchip,rk3066-hdmiÑ`  @ÕÙÜhclkªdefault¸NO6 Þ disabledportsport@0Ñendpoint@0ÑÎPÉLendpoint@1ÑÎQÉMport@1Ñi2s@10118000,rockchip,rk3066-i2sÑ€  ªdefault¸RÕKÆÜi2s_clki2s_hclk› txrxï Þ disabledi2s@1011a000,rockchip,rk3066-i2sÑ    ªdefault¸SÕLÇÜi2s_clki2s_hclk› txrxï Þ disabledi2s@1011c000,rockchip,rk3066-i2sÑÀ  ªdefault¸TÕMÈÜi2s_clki2s_hclk›   txrxï Þ disabledclock-controller@20000000,rockchip,rk3066a-cruÑ ÕUÜxin24m ©$@èËÔ^ÌÕ_ øׄ#g¸€á£ðÑ€xhÀá£ðÑ€xhÀÉtimer@2000e000,snps,dw-apb-timerÑ à .ÕVD Ütimerpclkefuse@20010000,rockchip,rk3066a-efuseÑ @Õ[ Üpclk_efusecpu_leakage@17Ñtimer@20038000,snps,dw-apb-timerÑ € ,ÕTB Ütimerpclktimer@2003a000,snps,dw-apb-timerÑ   -ÕUC Ütimerpclktsadc@20060000,rockchip,rk3066-tsadcÑ Õ]]Üsaradcapb_pclk N \ Osaradc-apb disabledpinctrl,rockchip,rk3066a-pinctrl Çgpio@20034000,rockchip,gpio-bankÑ @ 6ÕU1A^sÉ`gpio@2003c000,rockchip,gpio-bankÑ À 7ÕV1A^sÉgpio@2003e000,rockchip,gpio-bankÑ à 8ÕW1A^sgpio@20080000,rockchip,gpio-bankÑ  9ÕX1A^sÉ^gpio@20084000,rockchip,gpio-bankÑ @ :ÕY1A^sÉ+gpio@2000a000,rockchip,gpio-bankÑ   <ÕZ1A^sÉ/pcfg-pull-defaultMÉXpcfg-pull-nonecÉVemacemac-xfer€pVVVVVVVVÉemac-mdio pVVÉrmii-rstpWÉemmcemmc-clkpXÉemmc-cmdp XÉemmc-rstp XÉ hdmihdmi-hpdpXÉOhdmii2c-xfer pVVÉNi2c0i2c0-xfer pVVÉ*i2c1i2c1-xfer pVVÉ.i2c2i2c2-xfer pVVÉ8i2c3i2c3-xfer pVVÉ9i2c4i2c4-xfer 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©[èÉvdd_logO€O€Ø®B@dO€*okayvsys-regulator,regulator-fixedÉvsysLK@LK@Ø1É2stdby-regulator,regulator-fixed É5v_stdbyLK@LK@Ø1É]emmc-regulator,regulator-fixed Éemmc_vccq-ÆÀ-ÆÀ¼2É!sata-regulator,regulator-fixedÇ Ú+ªdefault¸\Éusb_5vLK@LK@ؼ]sdmmc-regulator,regulator-fixed Ú^ªdefault¸_Évcc_sd2Z 2Z ß† ¼3Éusb-host-regulator,regulator-fixedÇ Ú`ªdefault¸a Éhost-pwrLK@LK@ؼ]usb-otg-regulator,regulator-fixedÇ Ú`ªdefault¸bÉvcc_otgLK@LK@ؼ] #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4serial0serial1serial2serial3spi0spi1mmc0mmc1mmc2clock-frequency#clock-cellsclock-output-namesphandleregclocksclock-namesassigned-clocksassigned-clock-ratesresetsstatusinterruptsinterrupt-namespower-domainscache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modephyphy-supplyreset-gpiosfifo-depthreset-namesmax-frequencybus-widthdisable-wpvmmc-supplycap-mmc-highspeedcap-sd-highspeednon-removablevqmmc-supplyoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qos#phy-cells#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsvref-supplyenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu-supplyportsrangesremote-endpoint#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#reset-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsoutput-highwakeup-sourcelabellinux,codepwmsvoltage-tablevin-supplyenable-active-highgpiostartup-delay-us