Ð þí^½8Y€(=YH(,haoyu,marsboard-rk3066rockchip,rk3066a7MarsBoard RK3066aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/serial@10124000h/serial@10126000p/serial@20064000x/serial@20068000€/spi@20070000…/spi@20074000Š/mmc@10214000oscillator ,fixed-clock�n6Ÿ¬xin24m¿Egpu@10090000",rockchip,rk3066-maliarm,mali-400Ç ËÅÅ ÒbuscoreÞÅîõáx  disabledx5gpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3,video-codec@10104000,rockchip,rk3066-vpuÇ@   vepuvdpu ËÎØÍ×(Òaclk_vdpuhclk_vdpuaclk_vepuhclk_vepu,cache-controller@10138000,arm,pl310-cacheÇ€:H¿8scu@1013c000,arm,cortex-a9-scuÇÀglobal-timer@1013c200,arm,cortex-a9-global-timerÇ   Ë  disabledlocal-timer@1013c600,arm,cortex-a9-twd-timerÇÆ   Ëinterrupt-controller@1013d000,arm,cortex-a9-gicTiÇÐÁ¿serial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uartÇ@ "z„Òbaudclkapb_pclkË@L okay‘–txrx default®serial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uartÇ` #z„Òbaudclkapb_pclkËAM okay‘–txrx default®qos@1012d000,rockchip,rk3066-qossysconÇÐ ¿!qos@1012e000,rockchip,rk3066-qossysconÇà ¿ qos@1012f000,rockchip,rk3066-qossysconÇð ¿qos@1012f080,rockchip,rk3066-qossysconÇð€ ¿qos@1012f100,rockchip,rk3066-qossysconÇñ ¿qos@1012f180,rockchip,rk3066-qossysconÇñ€ ¿qos@1012f200,rockchip,rk3066-qossysconÇò ¿qos@1012f280,rockchip,rk3066-qossysconÇò€ ¿usb@10180000,rockchip,rk3066-usbsnps,dwc2Ç ËÃÒotg¸otgÀÒက@@ ð õusb2-phy okayusb@101c0000 ,snps,dwc2Ç ËÉÒotg¸hostð õusb2-phy okayethernet@10204000,rockchip,rk3066-emacÇ @< ÿ ËÄD Òhclkmacref drmii okay #  default ® mdioethernet-phy@0Ç¿ mmc@10214000,rockchip,rk2928-dw-mshcÇ!@ ËÀHÒbiuciu‘–rx-tx.Q9reset okay�úð€Eúð€ default®Smmc@10218000,rockchip,rk2928-dw-mshcÇ!€ ËÁIÒbiuciu‘–rx-tx.R9reset  disabled default®mmc@1021c000,rockchip,rk2928-dw-mshcÇ!À ËÂJÒbiuciu‘–rx-tx.S9reset  disablednand-controller@10500000,rockchip,rk2928-nfcÇP@ ËÓÒahb  disabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfdÇ @reboot-mode,syscon-reboot-mode_@fRBÃrRBÀRBà �RBÃpower-controller!,rockchip,rk3066-power-controllerœ¿power-domain@7LjËÃľ¿ÍÎPÇÖOÊÐÙÈÑÉÒ°œpower-domain@6Ç ËÎÍØ×° œpower-domain@8ÇËŰ!œgrf@20008000&,rockchip,rk3066-grfsysconsimple-mfdÇ €¿ usbphy,rockchip,rk3066a-usb-phy okayusb-phy@17cÇ|ËQÒphyclkŸ·¿usb-phy@188LjËRÒphyclkŸ·¿dma-controller@20018000,arm,pl330arm,primecellÇ €@ÂÍèËÀ Òapb_pclk¿dma-controller@2001c000,arm,pl330arm,primecellÇ À@ÂÍèËÀ Òapb_pclk  disabledi2c@2002d000,rockchip,rk3066-i2cÇ Ð (ÿ Òi2cËP  disabled default®"i2c@2002f000,rockchip,rk3066-i2cÇ ð )ÿ ËQÒi2c okay default®#�€tps@2dÇ-$ÿ% %%#%/&;&G%S% ,ti,tps65910regulatorsregulator@0`vcc_rtcoǃvrtcregulator@1`vcc_iooǃvio¿&regulator@2`vdd_arm˜ 'À°ã`Èoǃvdd1¿9regulator@3`vcc_ddr˜ 'À°ã`Èoǃvdd2regulator@5 `vcc18_cifoǃvdig1regulator@6`vdd_11oǃvdig2regulator@7`vcc_25oǃvpllregulator@8`vcc_18oǃvdacregulator@9 `vcc25_hdmioÇ ƒvaux1regulator@10`vcca_33oÇ ƒvaux2regulator@11 `vcc_rmiiÇ ƒvaux33¿ regulator@12 `vcc28_cifoÇ ƒvmmcregulator@4ǃvdd3regulator@13Ç ƒvbbpwm@20030000,rockchip,rk2928-pwmÇ ÚËF  disabled default®'pwm@20030010,rockchip,rk2928-pwmÇ ÚËF  disabled default®(watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdtÇ ÀËK 3 okaypwm@20050020,rockchip,rk2928-pwmÇ  ÚËG  disabled default®)pwm@20050030,rockchip,rk2928-pwmÇ 0ÚËG okay default®*¿Hi2c@20056000,rockchip,rk3066-i2cÇ ` *ÿ ËRÒi2c  disabled default®+i2c@2005a000,rockchip,rk3066-i2cÇ   +ÿ ËSÒi2c  disabled default®,i2c@2005e000,rockchip,rk3066-i2cÇ à 4ÿ ËTÒi2c  disabled default®-serial@20064000&,rockchip,rk3066-uartsnps,dw-apb-uartÇ @ $z„Òbaudclkapb_pclkËBN okay‘–txrx default®.serial@20068000&,rockchip,rk3066-uartsnps,dw-apb-uartÇ € %z„Òbaudclkapb_pclkËCO okay‘ –txrx default®/saradc@2006c000,rockchip,saradcÇ À åËGJÒsaradcapb_pclkW 9saradc-apb  disabledspi@20070000,rockchip,rk3066-spiËEHÒspiclkapb_pclk &Ç ‘  –txrx  disabled default®0123spi@20074000,rockchip,rk3066-spiËFIÒspiclkapb_pclk 'Ç @‘  –txrx  disabled default®4567dma-controller@20078000,arm,pl330arm,primecellÇ €@ÂÍèËÁ Òapb_pclk¿cpus÷rockchip,rk3066-smpcpu@0cpu,arm,cortex-a98Ç8"›@Ö O€íØa€*ˆ s€*ˆ 'ÀÈà°ÀÈàÂÀg83œ@ËA9cpu@1cpu,arm,cortex-a98ÇA9display-subsystem,rockchip,display-subsystemL:;sram@10080000 ,mmio-sramÇ Rsmp-sram@0,rockchip,rk3066-smp-sramÇPvop@1010c000,rockchip,rk3066-vopÇÀœ  ËþÍÒaclk_vopdclk_vophclk_vop,def 9axiahbdclk  disabledport¿:endpoint@0ÇY<¿@vop@1010e000,rockchip,rk3066-vopÇàœ ËÄ¿ÎÒaclk_vopdclk_vophclk_vop,ghi 9axiahbdclk  disabledport¿;endpoint@0ÇY=¿Ahdmi@10116000,rockchip,rk3066-hdmiÇ`  @ËÙÒhclk default®>?,ÿ i  disabledportsport@0Çendpoint@0ÇY@¿<endpoint@1ÇYA¿=port@1Çi2s@10118000,rockchip,rk3066-i2sÇ€   default®BËKÆÒi2s_clki2s_hclk‘–txrxz•i  disabledi2s@1011a000,rockchip,rk3066-i2sÇ     default®CËLÇÒi2s_clki2s_hclk‘–txrxz•i  disabledi2s@1011c000,rockchip,rk3066-i2sÇÀ   default®DËMÈÒi2s_clki2s_hclk‘  –txrxz•i  disabledclock-controller@20000000,rockchip,rk3066a-cruÇ ËEÒxin24mÿ Ÿ¯@ÞËÔ^ÌÕ_ îׄ#g¸€á£ðÑ€xhÀá£ðÑ€xhÀ¿timer@2000e000,snps,dw-apb-timerÇ à .ËVD Òtimerpclkefuse@20010000,rockchip,rk3066a-efuseÇ @Ë[ Òpclk_efusecpu_leakage@17Çtimer@20038000,snps,dw-apb-timerÇ € ,ËTB Òtimerpclktimer@2003a000,snps,dw-apb-timerÇ   -ËUC Òtimerpclktsadc@20060000,rockchip,rk3066-tsadcÇ Ë]]Òsaradcapb_pclk å\ 9saradc-apb  disabledpinctrl,rockchip,rk3066a-pinctrlÿ Rgpio@20034000,rockchip,gpio-bankÇ @ 6ËU¼ÌTigpio@2003c000,rockchip,gpio-bankÇ À 7ËV¼ÌTi¿gpio@2003e000,rockchip,gpio-bankÇ à 8ËW¼ÌTigpio@20080000,rockchip,gpio-bankÇ  9ËX¼ÌTi¿Igpio@20084000,rockchip,gpio-bankÇ @ :ËY¼ÌTigpio@2000a000,rockchip,gpio-bankÇ   <ËZ¼ÌTi¿$pcfg-pull-defaultØ¿Gpcfg-pull-noneî¿Femacemac-xfer€ûFFFFFFFF¿ emac-mdio ûFF¿ emmcemmc-clkûGemmc-cmdû Gemmc-rstû Ghdmihdmi-hpdûG¿?hdmii2c-xfer ûFF¿>i2c0i2c0-xfer ûFF¿"i2c1i2c1-xfer ûFF¿#i2c2i2c2-xfer ûFF¿+i2c3i2c3-xfer ûFF¿,i2c4i2c4-xfer ûFF¿-pwm0pwm0-outûF¿'pwm1pwm1-outûF¿(pwm2pwm2-outûF¿)pwm3pwm3-outûF¿*spi0spi0-clkûG¿0spi0-cs0ûG¿3spi0-txûG¿1spi0-rxûG¿2spi0-cs1ûGspi1spi1-clkûG¿4spi1-cs0ûG¿7spi1-rxûG¿6spi1-txûG¿5spi1-cs1ûGuart0uart0-xfer ûGG¿uart0-ctsûGuart0-rtsûGuart1uart1-xfer ûGG¿uart1-ctsûGuart1-rtsûGuart2uart2-xfer ûG G¿.uart3uart3-xfer ûGG¿/uart3-ctsûGuart3-rtsûGsd0sd0-clkûG¿sd0-cmdû G¿sd0-cdûG¿sd0-wpûGsd0-bus-width1û Gsd0-bus-width4@û G G G G¿sd1sd1-clkûG¿sd1-cmdûG¿sd1-cdûG¿sd1-wpûGsd1-bus-width1ûGsd1-bus-width4@ûGGGG¿i2s0i2s0-bus�ûGG G G G G GGG¿Bi2s1i2s1-bus`ûGGGGGG¿Ci2s2i2s2-bus`ûGGGGGG¿Dlan8720aphy-intûF¿memory@60000000memoryÇ`@vdd-log,pwm-regulator  Hè`vdd_log˜O€°O€oB@dO€* okaysdmmc-regulator,regulator-fixed `sdmmc-supply˜-ÆÀ°-ÆÀ I!† 2&¿vsys-regulator,regulator-fixed`vsys˜LK@°LK@È¿% #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4serial0serial1serial2serial3spi0spi1mmc0clock-frequency#clock-cellsclock-output-namesphandleregclocksclock-namesassigned-clocksassigned-clock-ratesresetsstatusinterruptsinterrupt-namespower-domainscache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modephyphy-supplyfifo-depthreset-namesmax-frequencyvmmc-supplyoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qos#phy-cells#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu-supplyportsrangesremote-endpoint#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#reset-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinspwmsvoltage-tablegpiostartup-delay-usvin-supply