Ð þí¨8ü(¨ûÈ1lg,omap3-sniperti,omap3630ti,omap36xxti,omap3 +7LG Optimus Blackchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000s/ocp@68000000/serial@49042000cpus+cpu@0arm,cortex-a8{cpu‡‹’cpuž“à¬ÀËÚæpmu@54000000arm,cortex-a8-pmu‡T€îùdebugsssocti,omap-inframpu ti,omap3-mpuùmpuiva ti,iva2.2ùivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus‡hî +ùl3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus‡ +  pinmux@30 ti,omap3-padconfpinctrl-single‡08+ *?]ÿzdefaultæçpinmux_uart3_pinsˆnpæèpinmux_dp3t_sel_pinsˆfhæépinmux_i2c1_pinsˆŠŒæêpinmux_i2c2_pinsˆŽ�æñpinmux_i2c3_pinsˆ’”æòpinmux_lp8720_en_pinˆPæópinmux_mmc1_pins0ˆæöpinmux_mmc2_pinsPˆ(*,.02468:æúpinmux_usb_otg_hs_pins`ˆrtvxz|~€‚„†ˆæpinmux_twl4030_pinsˆ°Aæëscm_conf@270sysconsimple-bus‡p0+ p0æpbias_regulator@2b0ti,pbias-omap3ti,pbias-omap‡°œpbias_mmc_omap2430£pbias_mmc_omap2430²w@Ê-ÆÀæõclocks+clock@68 ti,clksel‡hâclock-mcbsp5-mux-fckâti,composite-mux-clockïmcbsp5_mux_fck‹æ clock-mcbsp3-mux-fckâti,composite-mux-clockïmcbsp3_mux_fck‹ æclock-mcbsp4-mux-fckâti,composite-mux-clockïmcbsp4_mux_fck‹ æmcbsp5_fckâti,composite-clock‹ æclock@4 ti,clksel‡âclock-mcbsp1-mux-fckâti,composite-mux-clockïmcbsp1_mux_fck‹æ clock-mcbsp2-mux-fckâti,composite-mux-clockïmcbsp2_mux_fck‹ æmcbsp1_fckâti,composite-clock‹ æümcbsp2_fckâti,composite-clock‹æþmcbsp3_fckâti,composite-clock‹æÿmcbsp4_fckâti,composite-clock‹æclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single‡ \+ *?]ÿzdefaultpinmux_mmc1_cd_pinˆæ÷pinmux_twl4030_vpins ˆæìtarget-module@480a6000ti,sysc-omap2ti,sysc‡H `DH `HH `Lrevsyscsyss &4‹’ick+ H ` aes1@0 ti,omap3-aes‡PîA  Ftxrxtarget-module@480c5000ti,sysc-omap2ti,sysc‡H PDH PHH PLrevsyscsyss &4‹’ick+ H P aes2@0 ti,omap3-aes‡PîAABFtxrxprm@48306000 ti,omap3-prm‡H0`@î clocks+virt_16_8m_ckâ fixed-clockPYæosc_sys_ck@d40â ti,mux-clock‹‡ @æsys_ck@1270âti,divider-clock‹`‡pkæ"sys_clkout1@d70âti,gate-clock‹‡ pdpll3_x2_ckâfixed-factor-clock‹‚�dpll3_m2x2_ckâfixed-factor-clock‹‚�æ!dpll4_x2_ckâfixed-factor-clock‹ ‚�corex2_fckâfixed-factor-clock‹!‚�æ#wkup_l4_ickâfixed-factor-clock‹"‚�æbcorex2_d3_fckâfixed-factor-clock‹#‚�æŠcorex2_d5_fckâfixed-factor-clock‹#‚�æ‹clockdomainscm@48004000 ti,omap3-cm‡H@@clocks+dummy_apb_pclkâ fixed-clockPomap_32k_fckâ fixed-clockP€æHvirt_12m_ckâ fixed-clockP·ævirt_13m_ckâ fixed-clockPÆ]@ævirt_19200000_ckâ fixed-clockP$øævirt_26000000_ckâ fixed-clockPŒº€ævirt_38_4m_ckâ fixed-clockPIðædpll4_ck@d00âti,omap3-dpll-per-j-type-clock‹""‡ D 0æ dpll4_m2_ck@d48âti,divider-clock‹ `?‡ Hkæ$dpll4_m2x2_mul_ckâfixed-factor-clock‹$‚�æ%dpll4_m2x2_ck@d00âti,hsdiv-gate-clock‹%‡ —æ&omap_96m_alwon_fckâfixed-factor-clock‹&‚�æ2dpll3_ck@d00âti,omap3-dpll-core-clock‹""‡ @ 0æclock@1140 ti,clksel‡@âclock-dpll3-m3âti,divider-clock ïdpll3_m3_ck‹`kæ,clock-dpll4-m6âti,divider-clock ïdpll4_m6_ck‹ `?kæ>clock-emu-src-muxâ ti,mux-clockïemu_src_mux_ck‹"'()ævclock-pclk-fckâti,divider-clock ïpclk_fck‹*`kclock-pclkx2-fckâti,divider-clock ïpclkx2_fck‹*`kclock-atclk-fckâti,divider-clock ïatclk_fck‹*`kclock-traceclk-src-fckâ ti,mux-clockïtraceclk_src_fck‹"'()æ+clock-traceclk-fckâti,divider-clock ïtraceclk_fck‹+ `kdpll3_m3x2_mul_ckâfixed-factor-clock‹,‚�æ-dpll3_m3x2_ck@d00âti,hsdiv-gate-clock‹- ‡ —æ.emu_core_alwon_ckâfixed-factor-clock‹.‚�æ'sys_altclkâ fixed-clockPæ5mcbsp_clksâ fixed-clockPæcore_ckâfixed-factor-clock‹‚�æ/dpll1_fck@940âti,divider-clock‹/`‡ @kæ0dpll1_ck@904âti,omap3-dpll-clock‹"0‡  $ @ 4ædpll1_x2_ckâfixed-factor-clock‹‚�æ1dpll1_x2m2_ck@944âti,divider-clock‹1`‡ DkæEcm_96m_fckâfixed-factor-clock‹2‚�æ3clock@d40 ti,clksel‡ @âclock-dpll3-m2âti,divider-clock ïdpll3_m2_ck‹`kæclock-omap-96m-fckâ ti,mux-clock ïomap_96m_fck‹3"æYclock-omap-54m-fckâ ti,mux-clock ïomap_54m_fck‹45æAclock-omap-48m-fckâ ti,mux-clock ïomap_48m_fck‹65æ9clock@e40 ti,clksel‡@âclock-dpll4-m3âti,divider-clock ïdpll4_m3_ck‹ ` kæ7clock-dpll4-m4âti,divider-clock ïdpll4_m4_ck‹ `kæ:dpll4_m3x2_mul_ckâfixed-factor-clock‹7‚�æ8dpll4_m3x2_ck@d00âti,hsdiv-gate-clock‹8‡ —æ4cm_96m_d2_fckâfixed-factor-clock‹3‚�æ6omap_12m_fckâfixed-factor-clock‹9‚�æZdpll4_m4x2_mul_ckâti,fixed-factor-clock‹:­»Èæ;dpll4_m4x2_ck@d00âti,gate-clock‹;‡ —Èæ^dpll4_m5_ck@f40âti,divider-clock‹ `?‡@kæ<dpll4_m5x2_mul_ckâti,fixed-factor-clock‹<­»Èæ=dpll4_m5x2_ck@d00âti,hsdiv-gate-clock‹=‡ —Èæzdpll4_m6x2_mul_ckâfixed-factor-clock‹>‚�æ?dpll4_m6x2_ck@d00âti,hsdiv-gate-clock‹?‡ —æ@emu_per_alwon_ckâfixed-factor-clock‹@‚�æ(clock@d70 ti,clksel‡ pâclock-clkout2-src-gateâ ti,composite-no-wait-gate-clockïclkout2_src_gate_ck‹/æCclock-clkout2-src-muxâti,composite-mux-clockïclkout2_src_mux_ck‹/"3AæDclock-sys-clkout2âti,divider-clock ïsys_clkout2‹B`@Ûclkout2_src_ckâti,composite-clock‹CDæBmpu_ckâfixed-factor-clock‹E‚�æFarm_fck@924âti,divider-clock‹F‡ $`emu_mpu_alwon_ckâfixed-factor-clock‹F‚�æ)clock@a40 ti,clksel‡ @âclock-l3-ickâti,divider-clockïl3_ick‹/`kæGclock-l4-ickâti,divider-clockïl4_ick‹G`kæIclock-gpt10-mux-fckâti,composite-mux-clockïgpt10_mux_fck‹H"æVclock-gpt11-mux-fckâti,composite-mux-clockïgpt11_mux_fck‹H"æXclock-ssi-ssr-div-fck-3430es2âti,composite-divider-clockïssi_ssr_div_fck_3430es2‹#$ñæclock@c40 ti,clksel‡ @âclock-rm-ickâti,divider-clockïrm_ick‹I`kclock-gpt1-mux-fckâti,composite-mux-clock ïgpt1_mux_fck‹H"æaclock-usim-mux-fckâti,composite-mux-clock ïusim_mux_fck(‹"JKLMNOPQRkæƒclock@a00 ti,clksel‡ âclock-gpt10-gate-fckâti,composite-gate-clockïgpt10_gate_fck‹" æUclock-gpt11-gate-fckâti,composite-gate-clockïgpt11_gate_fck‹" æWclock-mmchs2-fckâti,wait-gate-clock ïmmchs2_fck‹æ¹clock-mmchs1-fckâti,wait-gate-clock ïmmchs1_fck‹æºclock-i2c3-fckâti,wait-gate-clock ïi2c3_fck‹æ»clock-i2c2-fckâti,wait-gate-clock ïi2c2_fck‹æ¼clock-i2c1-fckâti,wait-gate-clock ïi2c1_fck‹æ½clock-mcbsp5-gate-fckâti,composite-gate-clockïmcbsp5_gate_fck‹ æ clock-mcbsp1-gate-fckâti,composite-gate-clockïmcbsp1_gate_fck‹ æ clock-mcspi4-fckâti,wait-gate-clock ïmcspi4_fck‹Sæ¾clock-mcspi3-fckâti,wait-gate-clock ïmcspi3_fck‹Sæ¿clock-mcspi2-fckâti,wait-gate-clock ïmcspi2_fck‹SæÀclock-mcspi1-fckâti,wait-gate-clock ïmcspi1_fck‹SæÁclock-uart2-fckâti,wait-gate-clock ïuart2_fck‹SæÂclock-uart1-fckâti,wait-gate-clock ïuart1_fck‹S æÃclock-hdq-fckâti,wait-gate-clockïhdq_fck‹TæÄclock-modem-fckâti,omap3-interface-clock ïmodem_fck‹"æàclock-mspro-fckâti,wait-gate-clock ïmspro_fck‹clock-ssi-ssr-gate-fck-3430es2â ti,composite-no-wait-gate-clockïssi_ssr_gate_fck_3430es2‹#æ~clock-mmchs3-fckâti,wait-gate-clock ïmmchs3_fck‹æÜgpt10_fckâti,composite-clock‹UVgpt11_fckâti,composite-clock‹WXcore_96m_fckâfixed-factor-clock‹Y‚�æcore_48m_fckâfixed-factor-clock‹9‚�æScore_12m_fckâfixed-factor-clock‹Z‚�æTcore_l3_ickâfixed-factor-clock‹G‚�æ[clock@a10 ti,clksel‡ âclock-sdrc-ickâti,wait-gate-clock ïsdrc_ick‹[æŽclock-mmchs2-ickâti,omap3-interface-clock ïmmchs2_ick‹\æÅclock-mmchs1-ickâti,omap3-interface-clock ïmmchs1_ick‹\æÆclock-hdq-ickâti,omap3-interface-clockïhdq_ick‹\æÇclock-mcspi4-ickâti,omap3-interface-clock ïmcspi4_ick‹\æÈclock-mcspi3-ickâti,omap3-interface-clock ïmcspi3_ick‹\æÉclock-mcspi2-ickâti,omap3-interface-clock ïmcspi2_ick‹\æÊclock-mcspi1-ickâti,omap3-interface-clock ïmcspi1_ick‹\æËclock-i2c3-ickâti,omap3-interface-clock ïi2c3_ick‹\æÌclock-i2c2-ickâti,omap3-interface-clock ïi2c2_ick‹\æÍclock-i2c1-ickâti,omap3-interface-clock ïi2c1_ick‹\æÎclock-uart2-ickâti,omap3-interface-clock ïuart2_ick‹\æÏclock-uart1-ickâti,omap3-interface-clock ïuart1_ick‹\ æÐclock-gpt11-ickâti,omap3-interface-clock ïgpt11_ick‹\ æÑclock-gpt10-ickâti,omap3-interface-clock ïgpt10_ick‹\ æÒclock-mcbsp5-ickâti,omap3-interface-clock ïmcbsp5_ick‹\ æÓclock-mcbsp1-ickâti,omap3-interface-clock ïmcbsp1_ick‹\ æÔclock-omapctrl-ickâti,omap3-interface-clock ïomapctrl_ick‹\æÕclock-aes2-ickâti,omap3-interface-clock ïaes2_ick‹\æclock-sha12-ickâti,omap3-interface-clock ïsha12_ick‹\æÖclock-icr-ickâti,omap3-interface-clockïicr_ick‹\clock-des2-ickâti,omap3-interface-clock ïdes2_ick‹\clock-mspro-ickâti,omap3-interface-clock ïmspro_ick‹\clock-mailboxes-ickâti,omap3-interface-clockïmailboxes_ick‹\clock-sad2d-ickâti,omap3-interface-clock ïsad2d_ick‹Gæáclock-hsotgusb-ick-3430es2â"ti,omap3-hsotgusb-interface-clockïhsotgusb_ick_3430es2‹[æ�clock-ssi-ick-3430es2âti,omap3-ssi-interface-clockïssi_ick_3430es2‹]æclock-mmchs3-ickâti,omap3-interface-clock ïmmchs3_ick‹\æÛgpmc_fckâfixed-factor-clock‹[‚�core_l4_ickâfixed-factor-clock‹I‚�æ\clock@e00 ti,clksel‡âclock-dss-tv-fckâti,gate-clock ïdss_tv_fck‹Aæ´clock-dss-96m-fckâti,gate-clock ïdss_96m_fck‹Yæµclock-dss2-alwon-fckâti,gate-clockïdss2_alwon_fck‹"æ¶clock-dss1-alwon-fck-3430es2âti,dss-gate-clockïdss1_alwon_fck_3430es2‹^Èæ·dummy_ckâ fixed-clockPclock@c00 ti,clksel‡ âclock-gpt1-gate-fckâti,composite-gate-clockïgpt1_gate_fck‹"æ`clock-gpio1-dbckâti,gate-clock ïgpio1_dbck‹_æ«clock-wdt2-fckâti,wait-gate-clock ïwdt2_fck‹_æ¬clock-sr1-fckâti,wait-gate-clockïsr1_fck‹"æ clock-sr2-fckâti,wait-gate-clockïsr2_fck‹"æ clock-usim-gate-fckâti,composite-gate-clockïusim_gate_fck‹Y æ‚gpt1_fckâti,composite-clock‹`aæwkup_32k_fckâfixed-factor-clock‹H‚�æ_clock@c10 ti,clksel‡ âclock-wdt2-ickâti,omap3-interface-clock ïwdt2_ick‹bæ­clock-wdt1-ickâti,omap3-interface-clock ïwdt1_ick‹bæ®clock-gpio1-ickâti,omap3-interface-clock ïgpio1_ick‹bæ¯clock-omap-32ksync-ickâti,omap3-interface-clockïomap_32ksync_ick‹bæ°clock-gpt12-ickâti,omap3-interface-clock ïgpt12_ick‹bæ±clock-gpt1-ickâti,omap3-interface-clock ïgpt1_ick‹bæ²clock-usim-ickâti,omap3-interface-clock ïusim_ick‹b æ³per_96m_fckâfixed-factor-clock‹2‚�æ per_48m_fckâfixed-factor-clock‹9‚�æcclock@1000 ti,clksel‡âclock-uart3-fckâti,wait-gate-clock ïuart3_fck‹c æ�clock-gpt2-gate-fckâti,composite-gate-clockïgpt2_gate_fck‹"æeclock-gpt3-gate-fckâti,composite-gate-clockïgpt3_gate_fck‹"ægclock-gpt4-gate-fckâti,composite-gate-clockïgpt4_gate_fck‹"æiclock-gpt5-gate-fckâti,composite-gate-clockïgpt5_gate_fck‹"ækclock-gpt6-gate-fckâti,composite-gate-clockïgpt6_gate_fck‹"æmclock-gpt7-gate-fckâti,composite-gate-clockïgpt7_gate_fck‹"æoclock-gpt8-gate-fckâti,composite-gate-clockïgpt8_gate_fck‹" æqclock-gpt9-gate-fckâti,composite-gate-clockïgpt9_gate_fck‹" æsclock-gpio6-dbckâti,gate-clock ïgpio6_dbck‹dæ‘clock-gpio5-dbckâti,gate-clock ïgpio5_dbck‹dæ’clock-gpio4-dbckâti,gate-clock ïgpio4_dbck‹dæ“clock-gpio3-dbckâti,gate-clock ïgpio3_dbck‹dæ”clock-gpio2-dbckâti,gate-clock ïgpio2_dbck‹d æ•clock-wdt3-fckâti,wait-gate-clock ïwdt3_fck‹d æ–clock-mcbsp2-gate-fckâti,composite-gate-clockïmcbsp2_gate_fck‹æclock-mcbsp3-gate-fckâti,composite-gate-clockïmcbsp3_gate_fck‹æclock-mcbsp4-gate-fckâti,composite-gate-clockïmcbsp4_gate_fck‹æclock-uart4-fckâti,wait-gate-clock ïuart4_fck‹cæªclock@1040 ti,clksel‡@âclock-gpt2-mux-fckâti,composite-mux-clock ïgpt2_mux_fck‹H"æfclock-gpt3-mux-fckâti,composite-mux-clock ïgpt3_mux_fck‹H"æhclock-gpt4-mux-fckâti,composite-mux-clock ïgpt4_mux_fck‹H"æjclock-gpt5-mux-fckâti,composite-mux-clock ïgpt5_mux_fck‹H"ælclock-gpt6-mux-fckâti,composite-mux-clock ïgpt6_mux_fck‹H"ænclock-gpt7-mux-fckâti,composite-mux-clock ïgpt7_mux_fck‹H"æpclock-gpt8-mux-fckâti,composite-mux-clock ïgpt8_mux_fck‹H"ærclock-gpt9-mux-fckâti,composite-mux-clock ïgpt9_mux_fck‹H"ætgpt2_fckâti,composite-clock‹efægpt3_fckâti,composite-clock‹ghgpt4_fckâti,composite-clock‹ijgpt5_fckâti,composite-clock‹klgpt6_fckâti,composite-clock‹mngpt7_fckâti,composite-clock‹opgpt8_fckâti,composite-clock‹qrgpt9_fckâti,composite-clock‹stper_32k_alwon_fckâfixed-factor-clock‹H‚�ædper_l4_ickâfixed-factor-clock‹I‚�æuclock@1010 ti,clksel‡âclock-gpio6-ickâti,omap3-interface-clock ïgpio6_ick‹uæ—clock-gpio5-ickâti,omap3-interface-clock ïgpio5_ick‹uæ˜clock-gpio4-ickâti,omap3-interface-clock ïgpio4_ick‹uæ™clock-gpio3-ickâti,omap3-interface-clock ïgpio3_ick‹uæšclock-gpio2-ickâti,omap3-interface-clock ïgpio2_ick‹u æ›clock-wdt3-ickâti,omap3-interface-clock ïwdt3_ick‹u æœclock-uart3-ickâti,omap3-interface-clock ïuart3_ick‹u æ�clock-uart4-ickâti,omap3-interface-clock ïuart4_ick‹uæžclock-gpt9-ickâti,omap3-interface-clock ïgpt9_ick‹u æŸclock-gpt8-ickâti,omap3-interface-clock ïgpt8_ick‹u æ clock-gpt7-ickâti,omap3-interface-clock ïgpt7_ick‹uæ¡clock-gpt6-ickâti,omap3-interface-clock ïgpt6_ick‹uæ¢clock-gpt5-ickâti,omap3-interface-clock ïgpt5_ick‹uæ£clock-gpt4-ickâti,omap3-interface-clock ïgpt4_ick‹uæ¤clock-gpt3-ickâti,omap3-interface-clock ïgpt3_ick‹uæ¥clock-gpt2-ickâti,omap3-interface-clock ïgpt2_ick‹uæ¦clock-mcbsp2-ickâti,omap3-interface-clock ïmcbsp2_ick‹uæ§clock-mcbsp3-ickâti,omap3-interface-clock ïmcbsp3_ick‹uæ¨clock-mcbsp4-ickâti,omap3-interface-clock ïmcbsp4_ick‹uæ©emu_src_ckâti,clkdm-gate-clock‹væ*secure_32k_fckâ fixed-clockP€æwgpt12_fckâfixed-factor-clock‹w‚�æwdt1_fckâfixed-factor-clock‹w‚�security_l4_ick2âfixed-factor-clock‹I‚�æxclock@a14 ti,clksel‡ âclock-aes1-ickâti,omap3-interface-clock ïaes1_ick‹xæclock-rng-ickâti,omap3-interface-clockïrng_ick‹xæýclock-sha11-ickâti,omap3-interface-clock ïsha11_ick‹xclock-des1-ickâti,omap3-interface-clock ïdes1_ick‹xclock-pka-ickâti,omap3-interface-clockïpka_ick‹yclock@f00 ti,clksel‡âclock-cam-mclkâti,gate-clock ïcam_mclk‹zÈclock-csi2-96m-fckâti,gate-clock ïcsi2_96m_fck‹æÞcam_ick@f10â!ti,omap3-no-wait-interface-clock‹I‡æÝsecurity_l3_ickâfixed-factor-clock‹G‚�æyssi_l4_ickâfixed-factor-clock‹I‚�æ]sr_l4_ickâfixed-factor-clock‹I‚�dpll2_fck@40âti,divider-clock‹/`‡@kæ{dpll2_ck@4âti,omap3-dpll-clock‹"{‡$@4ýæ|dpll2_m2_ck@44âti,divider-clock‹|`‡Dkæ}iva2_ck@0âti,wait-gate-clock‹}‡æßclock@a18 ti,clksel‡ âclock-mad2d-ickâti,omap3-interface-clock ïmad2d_ick‹Gæâclock-usbtll-ickâti,omap3-interface-clock ïusbtll_ick‹\æÚssi_ssr_fck_3430es2âti,composite-clock‹~æ€ssi_sst_fck_3430es2âfixed-factor-clock‹€‚�æsys_d2_ckâfixed-factor-clock‹"‚�æJomap_96m_d2_fckâfixed-factor-clock‹Y‚�æKomap_96m_d4_fckâfixed-factor-clock‹Y‚�æLomap_96m_d8_fckâfixed-factor-clock‹Y‚�æMomap_96m_d10_fckâfixed-factor-clock‹Y‚� æNdpll5_m2_d4_ckâfixed-factor-clock‹�‚�æOdpll5_m2_d8_ckâfixed-factor-clock‹�‚�æPdpll5_m2_d16_ckâfixed-factor-clock‹�‚�æQdpll5_m2_d20_ckâfixed-factor-clock‹�‚�æRusim_fckâti,composite-clock‹‚ƒdpll5_ck@d04âti,omap3-dpll-clock‹""‡  $ L 4ýæ„dpll5_m2_ck@d50âti,divider-clock‹„`‡ Pkæ�sgx_gate_fck@b00âti,composite-gate-clock‹/‡ æŒcore_d3_ckâfixed-factor-clock‹/‚�æ…core_d4_ckâfixed-factor-clock‹/‚�æ†core_d6_ckâfixed-factor-clock‹/‚�æ‡omap_192m_alwon_fckâfixed-factor-clock‹&‚�æˆcore_d2_ckâfixed-factor-clock‹/‚�æ‰sgx_mux_fck@b40âti,composite-mux-clock ‹…†‡3ˆ‰Š‹‡ @æ�sgx_fckâti,composite-clock‹Œ�æ sgx_ick@b10âti,wait-gate-clock‹G‡ æãcpefuse_fck@a08âti,gate-clock‹"‡ æ×ts_fck@a08âti,gate-clock‹H‡ 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target-module@480cb000ti,sysc-omap3630-srti,syscùsmartreflex_core‡H °8sysc &‹ ’fck+ H °smartreflex@0ti,omap3-smartreflex-core‡îtarget-module@480c9000ti,sysc-omap3630-srti,syscùsmartreflex_mpu_iva‡H �8sysc &‹ ’fck+ H �smartreflex@480c9000ti,omap3-smartreflex-mpu-iva‡îtarget-module@50000000ti,sysc-omap4ti,sysc‡PþPþ revsysc + &‹ ã’fckick+ Popp-tableoperating-points-v2-ti-cpuœæopp50-300000000ïá£össssssÿÿÿÿopp100-600000000ï#ÃFöO€O€O€O€O€O€ÿÿÿÿopp130-800000000ï/¯ö7È7È7È7È7È7Èÿÿÿÿopp1g-1000000000ï;šÊöûûûûûûÿÿÿÿopp_supplyti,omap-opp-supply!ûthermal-zonescpu-thermal<úRè`N m tripscpu_alert}8€‰Ð‚passiveæcpu_crit}_�‰Ð ‚criticalcooling-mapsmap0” ™ÿÿÿÿÿÿÿÿmemory@80000000{memory‡€  compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-points-v2vbb-supply#cooling-cellscpu0-supplyphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsclock-output-namesti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,dividersti,low-power-stopti,lockti,low-power-bypassti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsti,no-reset-on-initinterrupts-extendedpinctrl-0ti,use_poweroffbci3v1-supplyio-channelsio-channel-namesregulator-always-onusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cellsenable-gpios#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplycd-gpiosbus-widthti,non-removablestatus#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinsmultipointnum-epsram-bitsinterface-typeusb-phyphysphy-namespowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendti,absolute-max-voltage-uvpolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-device