Ð þíó68éX( Þé Dcompulab,omap3-sbc-t3517compulab,omap3-cm-t3517ti,am3517ti,omap3 +!7CompuLab SBC-T3517 with CM-T3517chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000s/ocp@68000000/serial@4809e000{/ocp@68000000/can@5c050000/dvi-connectorˆ/svideo-connectorcpus+cpu@0arm,cortex-a8‘cpu�¡¨cpu´“àÂpmu@54000000arm,cortex-a8-pmu�T€Öádebugsssocti,omap-inframpu ti,omap3-mpuámpuiva ti,iva2.2áiva ëdisableddsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus�hÖ +òál3_mainl4@48000000ti,omap3-l4-coresimple-bus+ òHscm@2000ti,omap3-scmsimple-bus� + ò pinmux@30 ti,omap3-padconfpinctrl-single�08+ù.Lÿidefaultwpinmux_uart3_pins�np•Ðpinmux_mmc1_pins0�•Øpinmux_green_led_pins�²•öpinmux_dss_dpi_pins_common°�¤¦¨ª¸º¼¾ÀÂÄÆÈÊÌÎÐÒÔÖØÚ•ïpinmux_dss_dpi_pins_cm_t35x0�¬®°²´¶•ðpinmux_ads7846_pins�Š•Ôpinmux_mcspi1_pins �˜šœž•Ópinmux_i2c1_pins�ŠŒ•Ñpinmux_mcbsp2_pins � •ápinmux_hsusb1_phy_reset_pins�H•ùpinmux_hsusb2_phy_reset_pins�J•ûpinmux_otg_drv_vbus�à•ópinmux_mmc2_pins0�(*,.02•Üpinmux_wl12xx_core_pins�ˆF•þpinmux_usb_hub_pins�T•pinmux_smsc2_pins�†¢•ëpinmux_tfp410_pins�„•pinmux_i2c3_pins�’”•Òpinmux_sb_t35_audio_amp�˜•pinmux_mmc1_aux_pins��D•Ùpinmux_sb_t35_usb_hub_pins�¼•scm_conf@270sysconsimple-bus�p0+ òp0•pbias_regulator@2b0ti,pbias-omap3ti,pbias-omap�°�pbias_mmc_omap2430¤pbias_mmc_omap2430³w@Ë-ÆÀ•×clocks+clock@68 ti,clksel�hãclock-mcbsp5-mux-fckãti,composite-mux-clockðmcbsp5_mux_fck¡• clock-mcbsp3-mux-fckãti,composite-mux-clockðmcbsp3_mux_fck¡ •clock-mcbsp4-mux-fckãti,composite-mux-clockðmcbsp4_mux_fck¡ •mcbsp5_fckãti,composite-clock¡ •äclock@4 ti,clksel�ãclock-mcbsp1-mux-fckãti,composite-mux-clockðmcbsp1_mux_fck¡• clock-mcbsp2-mux-fckãti,composite-mux-clockðmcbsp2_mux_fck¡ •mcbsp1_fckãti,composite-clock¡ •ßmcbsp2_fckãti,composite-clock¡•àmcbsp3_fckãti,composite-clock¡•âmcbsp4_fckãti,composite-clock¡•ãemac_ick@32cãti,am35xx-gate-clock¡�,•zemac_fck@32cãti,gate-clock¡�, •ôvpfe_ick@32cãti,am35xx-gate-clock¡�,•{vpfe_fck@32cãti,gate-clock¡�, hsotgusb_ick_am35xx@32cãti,am35xx-gate-clock¡�,•|hsotgusb_fck_am35xx@32cãti,gate-clock¡�,•}hecc_ck@32cãti,am35xx-gate-clock¡�,•~clockdomainspinmux@a00 ti,omap3-padconfpinctrl-single� \+ù.Lÿpinmux_wl12xx_wkup_pins�•ýprm@48306000 ti,omap3-prm�H0`@Ö clocks+virt_16_8m_ckã fixed-clockY•osc_sys_ck@d40ã ti,mux-clock¡� @•sys_ck@1270ãti,divider-clock¡ �p+•sys_clkout1@d70ãti,gate-clock¡� pdpll3_x2_ckãfixed-factor-clock¡BMdpll3_m2x2_ckãfixed-factor-clock¡ BM•"dpll4_x2_ckãfixed-factor-clock¡!BMcorex2_fckãfixed-factor-clock¡"BM•#wkup_l4_ickãfixed-factor-clock¡BM•Xcorex2_d3_fckãfixed-factor-clock¡#BM•tcorex2_d5_fckãfixed-factor-clock¡#BM•uclockdomainscm@48004000 ti,omap3-cm�H@@clocks+dummy_apb_pclkã fixed-clockomap_32k_fckã fixed-clock€•Hvirt_12m_ckã fixed-clock·•virt_13m_ckã fixed-clockÆ]@•virt_19200000_ckã fixed-clock$ø•virt_26000000_ckã fixed-clockŒº€•virt_38_4m_ckã fixed-clockIð•dpll4_ck@d00ãti,omap3-dpll-per-clock¡� D 0•!dpll4_m2_ck@d48ãti,divider-clock¡! ?� H+•$dpll4_m2x2_mul_ckãfixed-factor-clock¡$BM•%dpll4_m2x2_ck@d00ãti,gate-clock¡%� W•&omap_96m_alwon_fckãfixed-factor-clock¡&BM•2dpll3_ck@d00ãti,omap3-dpll-core-clock¡� @ 0•clock@1140 ti,clksel�@ãclock-dpll3-m3ãti,divider-clock ðdpll3_m3_ck¡ +•,clock-dpll4-m6ãti,divider-clock ðdpll4_m6_ck¡! ?+•>clock-emu-src-muxã ti,mux-clockðemu_src_mux_ck¡'()•lclock-pclk-fckãti,divider-clock ðpclk_fck¡* +clock-pclkx2-fckãti,divider-clock ðpclkx2_fck¡* +clock-atclk-fckãti,divider-clock ðatclk_fck¡* +clock-traceclk-src-fckã ti,mux-clockðtraceclk_src_fck¡'()•+clock-traceclk-fckãti,divider-clock ðtraceclk_fck¡+  +dpll3_m3x2_mul_ckãfixed-factor-clock¡,BM•-dpll3_m3x2_ck@d00ãti,gate-clock¡- � W•.emu_core_alwon_ckãfixed-factor-clock¡.BM•'sys_altclkã fixed-clock•5mcbsp_clksã fixed-clock•core_ckãfixed-factor-clock¡ BM•/dpll1_fck@940ãti,divider-clock¡/ � @+•0dpll1_ck@904ãti,omap3-dpll-clock¡0�  $ @ 4•dpll1_x2_ckãfixed-factor-clock¡BM•1dpll1_x2m2_ck@944ãti,divider-clock¡1 � D+•Ecm_96m_fckãfixed-factor-clock¡2BM•3clock@d40 ti,clksel� @ãclock-dpll3-m2ãti,divider-clock ðdpll3_m2_ck¡ +• clock-omap-96m-fckã ti,mux-clock ðomap_96m_fck¡3•Pclock-omap-54m-fckã ti,mux-clock ðomap_54m_fck¡45•Aclock-omap-48m-fckã ti,mux-clock ðomap_48m_fck¡65•9clock@e40 ti,clksel�@ãclock-dpll4-m3ãti,divider-clock ðdpll4_m3_ck¡! +•7clock-dpll4-m4ãti,divider-clock ðdpll4_m4_ck¡! +•:dpll4_m3x2_mul_ckãfixed-factor-clock¡7BM•8dpll4_m3x2_ck@d00ãti,gate-clock¡8� W•4cm_96m_d2_fckãfixed-factor-clock¡3BM•6omap_12m_fckãfixed-factor-clock¡9BM•Qdpll4_m4x2_mul_ckãti,fixed-factor-clock¡:m{ˆ•;dpll4_m4x2_ck@d00ãti,gate-clock¡;� Wˆ•Tdpll4_m5_ck@f40ãti,divider-clock¡! ?�@+•<dpll4_m5x2_mul_ckãti,fixed-factor-clock¡<m{ˆ•=dpll4_m5x2_ck@d00ãti,gate-clock¡=� Wˆdpll4_m6x2_mul_ckãfixed-factor-clock¡>BM•?dpll4_m6x2_ck@d00ãti,gate-clock¡?� W•@emu_per_alwon_ckãfixed-factor-clock¡@BM•(clock@d70 ti,clksel� pãclock-clkout2-src-gateã ti,composite-no-wait-gate-clockðclkout2_src_gate_ck¡/•Cclock-clkout2-src-muxãti,composite-mux-clockðclkout2_src_mux_ck¡/3A•Dclock-sys-clkout2ãti,divider-clock ðsys_clkout2¡B @›clkout2_src_ckãti,composite-clock¡CD•Bmpu_ckãfixed-factor-clock¡EBM•Farm_fck@924ãti,divider-clock¡F� $ emu_mpu_alwon_ckãfixed-factor-clock¡FBM•)clock@a40 ti,clksel� @ãclock-l3-ickãti,divider-clockðl3_ick¡/ +•Gclock-l4-ickãti,divider-clockðl4_ick¡G +•Iclock-gpt10-mux-fckãti,composite-mux-clockðgpt10_mux_fck¡H•Mclock-gpt11-mux-fckãti,composite-mux-clockðgpt11_mux_fck¡H•Oclock@c40 ti,clksel� @ãclock-rm-ickãti,divider-clockðrm_ick¡I +clock-gpt1-mux-fckãti,composite-mux-clock ðgpt1_mux_fck¡H•Wclock@a00 ti,clksel� ãclock-gpt10-gate-fckãti,composite-gate-clockðgpt10_gate_fck¡ •Lclock-gpt11-gate-fckãti,composite-gate-clockðgpt11_gate_fck¡ •Nclock-mmchs2-fckãti,wait-gate-clock ðmmchs2_fck¡•¦clock-mmchs1-fckãti,wait-gate-clock ðmmchs1_fck¡•§clock-i2c3-fckãti,wait-gate-clock ði2c3_fck¡•¨clock-i2c2-fckãti,wait-gate-clock ði2c2_fck¡•©clock-i2c1-fckãti,wait-gate-clock ði2c1_fck¡•ªclock-mcbsp5-gate-fckãti,composite-gate-clockðmcbsp5_gate_fck¡ • clock-mcbsp1-gate-fckãti,composite-gate-clockðmcbsp1_gate_fck¡ • clock-mcspi4-fckãti,wait-gate-clock ðmcspi4_fck¡J•«clock-mcspi3-fckãti,wait-gate-clock ðmcspi3_fck¡J•¬clock-mcspi2-fckãti,wait-gate-clock ðmcspi2_fck¡J•­clock-mcspi1-fckãti,wait-gate-clock ðmcspi1_fck¡J•®clock-uart2-fckãti,wait-gate-clock ðuart2_fck¡J•¯clock-uart1-fckãti,wait-gate-clock ðuart1_fck¡J •°clock-hdq-fckãti,wait-gate-clockðhdq_fck¡K•±clock-uart4-fck-am35xxãti,wait-gate-clockðuart4_fck_am35xx¡Jclock-mmchs3-fckãti,wait-gate-clock ðmmchs3_fck¡•Êgpt10_fckãti,composite-clock¡LMgpt11_fckãti,composite-clock¡NOcore_96m_fckãfixed-factor-clock¡PBM•core_48m_fckãfixed-factor-clock¡9BM•Jcore_12m_fckãfixed-factor-clock¡QBM•Kcore_l3_ickãfixed-factor-clock¡GBM•Rclock@a10 ti,clksel� ãclock-sdrc-ickãti,wait-gate-clock ðsdrc_ick¡R•yclock-mmchs2-ickãti,omap3-interface-clock ðmmchs2_ick¡S•²clock-mmchs1-ickãti,omap3-interface-clock ðmmchs1_ick¡S•³clock-hdq-ickãti,omap3-interface-clockðhdq_ick¡S•´clock-mcspi4-ickãti,omap3-interface-clock ðmcspi4_ick¡S•µclock-mcspi3-ickãti,omap3-interface-clock ðmcspi3_ick¡S•¶clock-mcspi2-ickãti,omap3-interface-clock ðmcspi2_ick¡S•·clock-mcspi1-ickãti,omap3-interface-clock ðmcspi1_ick¡S•¸clock-i2c3-ickãti,omap3-interface-clock ði2c3_ick¡S•¹clock-i2c2-ickãti,omap3-interface-clock ði2c2_ick¡S•ºclock-i2c1-ickãti,omap3-interface-clock ði2c1_ick¡S•»clock-uart2-ickãti,omap3-interface-clock ðuart2_ick¡S•¼clock-uart1-ickãti,omap3-interface-clock ðuart1_ick¡S •½clock-gpt11-ickãti,omap3-interface-clock ðgpt11_ick¡S •¾clock-gpt10-ickãti,omap3-interface-clock ðgpt10_ick¡S •¿clock-mcbsp5-ickãti,omap3-interface-clock ðmcbsp5_ick¡S •Àclock-mcbsp1-ickãti,omap3-interface-clock ðmcbsp1_ick¡S •Áclock-omapctrl-ickãti,omap3-interface-clock ðomapctrl_ick¡S•Âclock-aes2-ickãti,omap3-interface-clock ðaes2_ick¡S•Ãclock-sha12-ickãti,omap3-interface-clock ðsha12_ick¡S•Äclock-ipss-ickãti,am35xx-interface-clock ðipss_ick¡R•clock-uart4-ick-am35xxãti,omap3-interface-clockðuart4_ick_am35xx¡Sclock-mmchs3-ickãti,omap3-interface-clock ðmmchs3_ick¡S•Égpmc_fckãfixed-factor-clock¡RBMcore_l4_ickãfixed-factor-clock¡IBM•Sclock@e00 ti,clksel�ãclock-dss-tv-fckãti,gate-clock ðdss_tv_fck¡A•¡clock-dss-96m-fckãti,gate-clock ðdss_96m_fck¡P•¢clock-dss2-alwon-fckãti,gate-clockðdss2_alwon_fck¡•£clock-dss1-alwon-fck-3430es2ãti,dss-gate-clockðdss1_alwon_fck_3430es2¡Tˆ•¤dummy_ckã fixed-clockclock@c00 ti,clksel� ãclock-gpt1-gate-fckãti,composite-gate-clockðgpt1_gate_fck¡•Vclock-gpio1-dbckãti,gate-clock ðgpio1_dbck¡U•™clock-wdt2-fckãti,wait-gate-clock ðwdt2_fck¡U•šgpt1_fckãti,composite-clock¡VW•åwkup_32k_fckãfixed-factor-clock¡HBM•Uclock@c10 ti,clksel� ãclock-wdt2-ickãti,omap3-interface-clock ðwdt2_ick¡X•›clock-wdt1-ickãti,omap3-interface-clock ðwdt1_ick¡X•œclock-gpio1-ickãti,omap3-interface-clock ðgpio1_ick¡X•�clock-omap-32ksync-ickãti,omap3-interface-clockðomap_32ksync_ick¡X•žclock-gpt12-ickãti,omap3-interface-clock ðgpt12_ick¡X•Ÿclock-gpt1-ickãti,omap3-interface-clock ðgpt1_ick¡X• per_96m_fckãfixed-factor-clock¡2BM• per_48m_fckãfixed-factor-clock¡9BM•Yclock@1000 ti,clksel�ãclock-uart3-fckãti,wait-gate-clock ðuart3_fck¡Y •clock-gpt2-gate-fckãti,composite-gate-clockðgpt2_gate_fck¡•[clock-gpt3-gate-fckãti,composite-gate-clockðgpt3_gate_fck¡•]clock-gpt4-gate-fckãti,composite-gate-clockðgpt4_gate_fck¡•_clock-gpt5-gate-fckãti,composite-gate-clockðgpt5_gate_fck¡•aclock-gpt6-gate-fckãti,composite-gate-clockðgpt6_gate_fck¡•cclock-gpt7-gate-fckãti,composite-gate-clockðgpt7_gate_fck¡•eclock-gpt8-gate-fckãti,composite-gate-clockðgpt8_gate_fck¡ •gclock-gpt9-gate-fckãti,composite-gate-clockðgpt9_gate_fck¡ •iclock-gpio6-dbckãti,gate-clock ðgpio6_dbck¡Z•€clock-gpio5-dbckãti,gate-clock ðgpio5_dbck¡Z•�clock-gpio4-dbckãti,gate-clock ðgpio4_dbck¡Z•‚clock-gpio3-dbckãti,gate-clock ðgpio3_dbck¡Z•ƒclock-gpio2-dbckãti,gate-clock ðgpio2_dbck¡Z •„clock-wdt3-fckãti,wait-gate-clock ðwdt3_fck¡Z •…clock-mcbsp2-gate-fckãti,composite-gate-clockðmcbsp2_gate_fck¡•clock-mcbsp3-gate-fckãti,composite-gate-clockðmcbsp3_gate_fck¡•clock-mcbsp4-gate-fckãti,composite-gate-clockðmcbsp4_gate_fck¡•clock@1040 ti,clksel�@ãclock-gpt2-mux-fckãti,composite-mux-clock ðgpt2_mux_fck¡H•\clock-gpt3-mux-fckãti,composite-mux-clock ðgpt3_mux_fck¡H•^clock-gpt4-mux-fckãti,composite-mux-clock ðgpt4_mux_fck¡H•`clock-gpt5-mux-fckãti,composite-mux-clock ðgpt5_mux_fck¡H•bclock-gpt6-mux-fckãti,composite-mux-clock ðgpt6_mux_fck¡H•dclock-gpt7-mux-fckãti,composite-mux-clock ðgpt7_mux_fck¡H•fclock-gpt8-mux-fckãti,composite-mux-clock ðgpt8_mux_fck¡H•hclock-gpt9-mux-fckãti,composite-mux-clock ðgpt9_mux_fck¡H•jgpt2_fckãti,composite-clock¡[\•ægpt3_fckãti,composite-clock¡]^gpt4_fckãti,composite-clock¡_`gpt5_fckãti,composite-clock¡abgpt6_fckãti,composite-clock¡cdgpt7_fckãti,composite-clock¡efgpt8_fckãti,composite-clock¡ghgpt9_fckãti,composite-clock¡ijper_32k_alwon_fckãfixed-factor-clock¡HBM•Zper_l4_ickãfixed-factor-clock¡IBM•kclock@1010 ti,clksel�ãclock-gpio6-ickãti,omap3-interface-clock ðgpio6_ick¡k•†clock-gpio5-ickãti,omap3-interface-clock ðgpio5_ick¡k•‡clock-gpio4-ickãti,omap3-interface-clock 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fixed-clock€•mgpt12_fckãfixed-factor-clock¡mBM•çwdt1_fckãfixed-factor-clock¡mBMrmii_ckã fixed-clockúð€•pclk_ckã fixed-clock›üÀ•dpll5_ck@d04ãti,omap3-dpll-clock¡�  $ L 4±Ã•ndpll5_m2_ck@d50ãti,divider-clock¡n � P+•xsgx_gate_fck@b00ãti,composite-gate-clock¡/� •vcore_d3_ckãfixed-factor-clock¡/BM•ocore_d4_ckãfixed-factor-clock¡/BM•pcore_d6_ckãfixed-factor-clock¡/BM•qomap_192m_alwon_fckãfixed-factor-clock¡&BM•rcore_d2_ckãfixed-factor-clock¡/BM•ssgx_mux_fck@b40ãti,composite-mux-clock ¡opq3rstu� @•wsgx_fckãti,composite-clock¡vw•õsgx_ick@b10ãti,wait-gate-clock¡G� •Ëcpefuse_fck@a08ãti,gate-clock¡� •Åts_fck@a08ãti,gate-clock¡H� •Æusbtll_fck@a08ãti,wait-gate-clock¡x� •Çclock@a18 ti,clksel� ãclock-usbtll-ickãti,omap3-interface-clock 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§•Ýwl12xx_vaux2regulator-fixed¤vwl1271_vaux2³w@Ëw@•Þencoder ti,tfp410 ºÖidefaultwports+port@0�endpointt•òport@1�endpointt•dvi-connectordvi-connectorŒdviportendpointt•audio_ampregulator-fixed ¤audio_ampidefaultw Ö Êregulator-vddvario-sb-t35regulator-fixed ¤vddvario Ê•íregulator-vdd33a-sb-t35regulator-fixed¤vdd33a Ê•î compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2serial3candisplay0display1device_typeregclocksclock-namesclock-latencyoperating-points-v2interruptsti,hwmodsstatusranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsclock-output-namesti,bit-shiftclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockreg-namesti,sysc-sidleti,sysc-maskti,sysc-midleti,syss-mask#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendeddmasdma-namespagesize#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-repwakeup-sourceti,dual-voltpbias-supplybus-widthvmmc-supplywp-gpioscd-gpiosvqmmc-supplynon-removablecap-power-off-cardref-clock-frequency#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport1-modeport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,page-burst-access-nsgpmc,access-nsgpmc,cycle2cycle-delay-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,bus-turnaround-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsremote-endpointti,channelsdata-linesti,davinci-ctrl-reg-offsetti,davinci-ctrl-mod-reg-offsetti,davinci-ctrl-ram-offsetti,davinci-ctrl-ram-sizeti,davinci-rmii-enlocal-mac-addressbus_freqopp-hzopp-microvoltopp-supported-hwopp-suspendlinux,default-triggerstartup-delay-us#phy-cellsreset-gpiosenable-active-highpowerdown-gpiosregulator-always-on