Ð þíQ8( =Ü3logicpd,dm3730-torpedo-devkitti,omap3430ti,omap3 +.7LogicPD Zoom OMAP35xx Torpedo Development Kitchosen=/ocp@68000000/serial@4806a000aliasesI/ocp@68000000/i2c@48070000N/ocp@68000000/i2c@48072000S/ocp@68000000/i2c@48060000X/ocp@68000000/mmc@4809c000]/ocp@68000000/mmc@480b4000b/ocp@68000000/mmc@480ad000g/ocp@68000000/serial@4806a000o/ocp@68000000/serial@4806c000w/ocp@68000000/serial@49020000 /displaycpus+cpu@0arm,cortex-a8ˆcpu”˜Ÿcpu«“à¹ÍÜèpmu@54000000arm,cortex-a8-pmu”T€ðûdebugsssocti,omap-inframpu ti,omap3-mpuûmpuiva ti,iva2.2ûivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus”hð +ûl3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus” +  pinmux@30 ti,omap3-padconfpinctrl-single”08+ ,A_ÿèåpinmux_mcbsp2_pins | èpinmux_uart2_pins(|DFHJhèæpinmux_mcspi1_pins |˜šœžè÷pinmux_hsusb_otg_pins`|rtvxz|~€‚„†ˆè pinmux_i2c1_pins|ŠŒèçpinmux_i2c2_pins|Ž�èïpinmux_i2c3_pins|’”èópinmux_twl4030_pins|°Aèépinmux_gpio_key_pins|¦¬è hdq_pins|–èøpinmux_pwm_pins|ˆè$pinmux_led_pins|¨ªèpinmux_mmc1_pins0|èúpinmux_tsc2004_pins|Vèõpinmux_backlight_pins|Xè)pinmux_isp_pins`|ÜÞàâæèêìîðòôèpinmux_panel_pwr_pins|Zè&pinmux_dss_dpi_pins1°|¤¦¨ª¸º¼¾ÀÂÄÆÈÊÌÎÐ Ò Ô Ö Ø Ú èpinmux_isp1763_pins|$è scm_conf@270sysconsimple-bus”p0+ p0èpbias_regulator@2b0ti,pbias-omap3ti,pbias-omap”°�pbias_mmc_omap2430—pbias_mmc_omap2430¦w@¾-ÆÀèùclocks+clock@68 ti,clksel”hÖclock-mcbsp5-mux-fckÖti,composite-mux-clockãmcbsp5_mux_fck˜öè clock-mcbsp3-mux-fckÖti,composite-mux-clockãmcbsp3_mux_fck˜èclock-mcbsp4-mux-fckÖti,composite-mux-clockãmcbsp4_mux_fck˜öèmcbsp5_fckÖti,composite-clock˜ èclock@4 ti,clksel”Öclock-mcbsp1-mux-fckÖti,composite-mux-clockãmcbsp1_mux_fck˜öè clock-mcbsp2-mux-fckÖti,composite-mux-clockãmcbsp2_mux_fck˜öèmcbsp1_fckÖti,composite-clock˜ èþmcbsp2_fckÖti,composite-clock˜ èmcbsp3_fckÖti,composite-clock˜èmcbsp4_fckÖti,composite-clock˜èclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single” \+ ,A_ÿpinmux_twl4030_vpins |èêpinmux_gpio_key_pins_wkup| è!pinmux_lan9221_pins|Zè pinmux_mmc1_cd|Tèûtarget-module@480a6000ti,sysc-omap2ti,sysc”H `DH `HH `Lrevsyscsyss  (˜Ÿick+ H ` aes1@0 ti,omap3-aes”Pð5  :txrxtarget-module@480c5000ti,sysc-omap2ti,sysc”H PDH PHH PLrevsyscsyss  (˜Ÿick+ H P aes2@0 ti,omap3-aes”Pð5AB:txrxprm@48306000 ti,omap3-prm”H0`@ð clocks+virt_16_8m_ckÖ fixed-clockDYèosc_sys_ck@d40Ö ti,mux-clock˜” @èsys_ck@1270Öti,divider-clock˜öT”p_è!sys_clkout1@d70Öti,gate-clock˜” pödpll3_x2_ckÖfixed-factor-clock˜v�dpll3_m2x2_ckÖfixed-factor-clock˜v�è dpll4_x2_ckÖfixed-factor-clock˜v�corex2_fckÖfixed-factor-clock˜ v�è"wkup_l4_ickÖfixed-factor-clock˜!v�èacorex2_d3_fckÖfixed-factor-clock˜"v�è‰corex2_d5_fckÖfixed-factor-clock˜"v�èŠclockdomainscm@48004000 ti,omap3-cm”H@@clocks+dummy_apb_pclkÖ fixed-clockDomap_32k_fckÖ fixed-clockD€èGvirt_12m_ckÖ fixed-clockD·èvirt_13m_ckÖ fixed-clockDÆ]@èvirt_19200000_ckÖ fixed-clockD$øèvirt_26000000_ckÖ fixed-clockDŒº€èvirt_38_4m_ckÖ fixed-clockDIðèdpll4_ck@d00Öti,omap3-dpll-per-clock˜!!” D 0èdpll4_m2_ck@d48Öti,divider-clock˜T?” H_è#dpll4_m2x2_mul_ckÖfixed-factor-clock˜#v�è$dpll4_m2x2_ck@d00Öti,gate-clock˜$ö” ‹è%omap_96m_alwon_fckÖfixed-factor-clock˜%v�è1dpll3_ck@d00Öti,omap3-dpll-core-clock˜!!” @ 0èclock@1140 ti,clksel”@Öclock-dpll3-m3Öti,divider-clock ãdpll3_m3_ck˜öT_è+clock-dpll4-m6Öti,divider-clock ãdpll4_m6_ck˜öT?_è=clock-emu-src-muxÖ ti,mux-clockãemu_src_mux_ck˜!&'(èuclock-pclk-fckÖti,divider-clock ãpclk_fck˜)öT_clock-pclkx2-fckÖti,divider-clock ãpclkx2_fck˜)öT_clock-atclk-fckÖti,divider-clock ãatclk_fck˜)öT_clock-traceclk-src-fckÖ ti,mux-clockãtraceclk_src_fck˜!&'(öè*clock-traceclk-fckÖti,divider-clock ãtraceclk_fck˜*ö T_dpll3_m3x2_mul_ckÖfixed-factor-clock˜+v�è,dpll3_m3x2_ck@d00Öti,gate-clock˜,ö ” ‹è-emu_core_alwon_ckÖfixed-factor-clock˜-v�è&sys_altclkÖ fixed-clockDè4mcbsp_clksÖ fixed-clockDècore_ckÖfixed-factor-clock˜v�è.dpll1_fck@940Öti,divider-clock˜.öT” @_è/dpll1_ck@904Öti,omap3-dpll-clock˜!/”  $ @ 4èdpll1_x2_ckÖfixed-factor-clock˜v�è0dpll1_x2m2_ck@944Öti,divider-clock˜0T” D_èDcm_96m_fckÖfixed-factor-clock˜1v�è2clock@d40 ti,clksel” @Öclock-dpll3-m2Öti,divider-clock ãdpll3_m2_ck˜öT_èclock-omap-96m-fckÖ ti,mux-clock ãomap_96m_fck˜2!öèXclock-omap-54m-fckÖ ti,mux-clock ãomap_54m_fck˜34öè@clock-omap-48m-fckÖ ti,mux-clock ãomap_48m_fck˜54öè8clock@e40 ti,clksel”@Öclock-dpll4-m3Öti,divider-clock ãdpll4_m3_ck˜öT _è6clock-dpll4-m4Öti,divider-clock ãdpll4_m4_ck˜T_è9dpll4_m3x2_mul_ckÖfixed-factor-clock˜6v�è7dpll4_m3x2_ck@d00Öti,gate-clock˜7ö” ‹è3cm_96m_d2_fckÖfixed-factor-clock˜2v�è5omap_12m_fckÖfixed-factor-clock˜8v�èYdpll4_m4x2_mul_ckÖti,fixed-factor-clock˜9¡¯¼è:dpll4_m4x2_ck@d00Öti,gate-clock˜:ö” ‹¼è]dpll4_m5_ck@f40Öti,divider-clock˜T?”@_è;dpll4_m5x2_mul_ckÖti,fixed-factor-clock˜;¡¯¼è<dpll4_m5x2_ck@d00Öti,gate-clock˜<ö” ‹¼èydpll4_m6x2_mul_ckÖfixed-factor-clock˜=v�è>dpll4_m6x2_ck@d00Öti,gate-clock˜>ö” ‹è?emu_per_alwon_ckÖfixed-factor-clock˜?v�è'clock@d70 ti,clksel” pÖclock-clkout2-src-gateÖ ti,composite-no-wait-gate-clockãclkout2_src_gate_ck˜.öèBclock-clkout2-src-muxÖti,composite-mux-clockãclkout2_src_mux_ck˜.!2@èCclock-sys-clkout2Öti,divider-clock ãsys_clkout2˜AöT@Ïclkout2_src_ckÖti,composite-clock˜BCèAmpu_ckÖfixed-factor-clock˜Dv�èEarm_fck@924Öti,divider-clock˜E” $Temu_mpu_alwon_ckÖfixed-factor-clock˜Ev�è(clock@a40 ti,clksel” @Öclock-l3-ickÖti,divider-clockãl3_ick˜.T_èFclock-l4-ickÖti,divider-clockãl4_ick˜FöT_èHclock-gpt10-mux-fckÖti,composite-mux-clockãgpt10_mux_fck˜G!öèUclock-gpt11-mux-fckÖti,composite-mux-clockãgpt11_mux_fck˜G!öèWclock-ssi-ssr-div-fck-3430es2Öti,composite-divider-clockãssi_ssr_div_fck_3430es2˜"ö$åè~clock@c40 ti,clksel” @Öclock-rm-ickÖti,divider-clockãrm_ick˜HöT_clock-gpt1-mux-fckÖti,composite-mux-clock ãgpt1_mux_fck˜G!è`clock-usim-mux-fckÖti,composite-mux-clock ãusim_mux_fck(˜!IJKLMNOPQö_è‚clock@a00 ti,clksel” Öclock-gpt10-gate-fckÖti,composite-gate-clockãgpt10_gate_fck˜!ö èTclock-gpt11-gate-fckÖti,composite-gate-clockãgpt11_gate_fck˜!ö èVclock-mmchs2-fckÖti,wait-gate-clock ãmmchs2_fck˜öè·clock-mmchs1-fckÖti,wait-gate-clock ãmmchs1_fck˜öè¸clock-i2c3-fckÖti,wait-gate-clock ãi2c3_fck˜öè¹clock-i2c2-fckÖti,wait-gate-clock ãi2c2_fck˜öèºclock-i2c1-fckÖti,wait-gate-clock ãi2c1_fck˜öè»clock-mcbsp5-gate-fckÖti,composite-gate-clockãmcbsp5_gate_fck˜ö è clock-mcbsp1-gate-fckÖti,composite-gate-clockãmcbsp1_gate_fck˜ö è clock-mcspi4-fckÖti,wait-gate-clock ãmcspi4_fck˜Röè¼clock-mcspi3-fckÖti,wait-gate-clock ãmcspi3_fck˜Röè½clock-mcspi2-fckÖti,wait-gate-clock ãmcspi2_fck˜Röè¾clock-mcspi1-fckÖti,wait-gate-clock ãmcspi1_fck˜Röè¿clock-uart2-fckÖti,wait-gate-clock ãuart2_fck˜RöèÀclock-uart1-fckÖti,wait-gate-clock ãuart1_fck˜Rö èÁclock-hdq-fckÖti,wait-gate-clockãhdq_fck˜SöèÂclock-modem-fckÖti,omap3-interface-clock ãmodem_fck˜!öèÞclock-mspro-fckÖti,wait-gate-clock ãmspro_fck˜öclock-ssi-ssr-gate-fck-3430es2Ö ti,composite-no-wait-gate-clockãssi_ssr_gate_fck_3430es2˜"öè}clock-mmchs3-fckÖti,wait-gate-clock ãmmchs3_fck˜öèÚgpt10_fckÖti,composite-clock˜TUgpt11_fckÖti,composite-clock˜VWcore_96m_fckÖfixed-factor-clock˜Xv�ècore_48m_fckÖfixed-factor-clock˜8v�èRcore_12m_fckÖfixed-factor-clock˜Yv�èScore_l3_ickÖfixed-factor-clock˜Fv�èZclock@a10 ti,clksel” Öclock-sdrc-ickÖti,wait-gate-clock ãsdrc_ick˜Zöè�clock-mmchs2-ickÖti,omap3-interface-clock ãmmchs2_ick˜[öèÃclock-mmchs1-ickÖti,omap3-interface-clock ãmmchs1_ick˜[öèÄclock-hdq-ickÖti,omap3-interface-clockãhdq_ick˜[öèÅclock-mcspi4-ickÖti,omap3-interface-clock ãmcspi4_ick˜[öèÆclock-mcspi3-ickÖti,omap3-interface-clock ãmcspi3_ick˜[öèÇclock-mcspi2-ickÖti,omap3-interface-clock ãmcspi2_ick˜[öèÈclock-mcspi1-ickÖti,omap3-interface-clock ãmcspi1_ick˜[öèÉclock-i2c3-ickÖti,omap3-interface-clock ãi2c3_ick˜[öèÊclock-i2c2-ickÖti,omap3-interface-clock ãi2c2_ick˜[öèËclock-i2c1-ickÖti,omap3-interface-clock ãi2c1_ick˜[öèÌclock-uart2-ickÖti,omap3-interface-clock ãuart2_ick˜[öèÍclock-uart1-ickÖti,omap3-interface-clock ãuart1_ick˜[ö èÎclock-gpt11-ickÖti,omap3-interface-clock ãgpt11_ick˜[ö èÏclock-gpt10-ickÖti,omap3-interface-clock ãgpt10_ick˜[ö èÐclock-mcbsp5-ickÖti,omap3-interface-clock ãmcbsp5_ick˜[ö èÑclock-mcbsp1-ickÖti,omap3-interface-clock ãmcbsp1_ick˜[ö èÒclock-omapctrl-ickÖti,omap3-interface-clock ãomapctrl_ick˜[öèÓclock-aes2-ickÖti,omap3-interface-clock ãaes2_ick˜[öèclock-sha12-ickÖti,omap3-interface-clock ãsha12_ick˜[öèÔclock-icr-ickÖti,omap3-interface-clockãicr_ick˜[öclock-des2-ickÖti,omap3-interface-clock ãdes2_ick˜[öclock-mspro-ickÖti,omap3-interface-clock ãmspro_ick˜[öclock-mailboxes-ickÖti,omap3-interface-clockãmailboxes_ick˜[öclock-sad2d-ickÖti,omap3-interface-clock ãsad2d_ick˜Föèßclock-hsotgusb-ick-3430es2Ö"ti,omap3-hsotgusb-interface-clockãhsotgusb_ick_3430es2˜ZöèŽclock-ssi-ick-3430es2Öti,omap3-ssi-interface-clockãssi_ick_3430es2˜\öèclock-mmchs3-ickÖti,omap3-interface-clock ãmmchs3_ick˜[öèÙgpmc_fckÖfixed-factor-clock˜Zv�core_l4_ickÖfixed-factor-clock˜Hv�è[clock@e00 ti,clksel”Öclock-dss-tv-fckÖti,gate-clock ãdss_tv_fck˜@öè²clock-dss-96m-fckÖti,gate-clock ãdss_96m_fck˜Xöè³clock-dss2-alwon-fckÖti,gate-clockãdss2_alwon_fck˜!öè´clock-dss1-alwon-fck-3430es2Öti,dss-gate-clockãdss1_alwon_fck_3430es2˜]ö¼èµdummy_ckÖ fixed-clockDclock@c00 ti,clksel” Öclock-gpt1-gate-fckÖti,composite-gate-clockãgpt1_gate_fck˜!öè_clock-gpio1-dbckÖti,gate-clock ãgpio1_dbck˜^öè©clock-wdt2-fckÖti,wait-gate-clock ãwdt2_fck˜^öèªclock-sr1-fckÖti,wait-gate-clockãsr1_fck˜!öèclock-sr2-fckÖti,wait-gate-clockãsr2_fck˜!öèclock-usim-gate-fckÖti,composite-gate-clockãusim_gate_fck˜Xö è�gpt1_fckÖti,composite-clock˜_`èwkup_32k_fckÖfixed-factor-clock˜Gv�è^clock@c10 ti,clksel” Öclock-wdt2-ickÖti,omap3-interface-clock ãwdt2_ick˜aöè«clock-wdt1-ickÖti,omap3-interface-clock ãwdt1_ick˜aöè¬clock-gpio1-ickÖti,omap3-interface-clock ãgpio1_ick˜aöè­clock-omap-32ksync-ickÖti,omap3-interface-clockãomap_32ksync_ick˜aöè®clock-gpt12-ickÖti,omap3-interface-clock ãgpt12_ick˜aöè¯clock-gpt1-ickÖti,omap3-interface-clock ãgpt1_ick˜aöè°clock-usim-ickÖti,omap3-interface-clock ãusim_ick˜aö è±per_96m_fckÖfixed-factor-clock˜1v�èper_48m_fckÖfixed-factor-clock˜8v�èbclock@1000 ti,clksel”Öclock-uart3-fckÖti,wait-gate-clock ãuart3_fck˜bö è�clock-gpt2-gate-fckÖti,composite-gate-clockãgpt2_gate_fck˜!öèdclock-gpt3-gate-fckÖti,composite-gate-clockãgpt3_gate_fck˜!öèfclock-gpt4-gate-fckÖti,composite-gate-clockãgpt4_gate_fck˜!öèhclock-gpt5-gate-fckÖti,composite-gate-clockãgpt5_gate_fck˜!öèjclock-gpt6-gate-fckÖti,composite-gate-clockãgpt6_gate_fck˜!öèlclock-gpt7-gate-fckÖti,composite-gate-clockãgpt7_gate_fck˜!öènclock-gpt8-gate-fckÖti,composite-gate-clockãgpt8_gate_fck˜!ö èpclock-gpt9-gate-fckÖti,composite-gate-clockãgpt9_gate_fck˜!ö èrclock-gpio6-dbckÖti,gate-clock ãgpio6_dbck˜cöè�clock-gpio5-dbckÖti,gate-clock ãgpio5_dbck˜cöè‘clock-gpio4-dbckÖti,gate-clock ãgpio4_dbck˜cöè’clock-gpio3-dbckÖti,gate-clock ãgpio3_dbck˜cöè“clock-gpio2-dbckÖti,gate-clock ãgpio2_dbck˜cö è”clock-wdt3-fckÖti,wait-gate-clock ãwdt3_fck˜cö è•clock-mcbsp2-gate-fckÖti,composite-gate-clockãmcbsp2_gate_fck˜öè clock-mcbsp3-gate-fckÖti,composite-gate-clockãmcbsp3_gate_fck˜öèclock-mcbsp4-gate-fckÖti,composite-gate-clockãmcbsp4_gate_fck˜öèclock@1040 ti,clksel”@Öclock-gpt2-mux-fckÖti,composite-mux-clock ãgpt2_mux_fck˜G!èeclock-gpt3-mux-fckÖti,composite-mux-clock ãgpt3_mux_fck˜G!öègclock-gpt4-mux-fckÖti,composite-mux-clock ãgpt4_mux_fck˜G!öèiclock-gpt5-mux-fckÖti,composite-mux-clock ãgpt5_mux_fck˜G!öèkclock-gpt6-mux-fckÖti,composite-mux-clock ãgpt6_mux_fck˜G!öèmclock-gpt7-mux-fckÖti,composite-mux-clock ãgpt7_mux_fck˜G!öèoclock-gpt8-mux-fckÖti,composite-mux-clock ãgpt8_mux_fck˜G!öèqclock-gpt9-mux-fckÖti,composite-mux-clock ãgpt9_mux_fck˜G!öèsgpt2_fckÖti,composite-clock˜deègpt3_fckÖti,composite-clock˜fggpt4_fckÖti,composite-clock˜higpt5_fckÖti,composite-clock˜jkgpt6_fckÖti,composite-clock˜lmgpt7_fckÖti,composite-clock˜nogpt8_fckÖti,composite-clock˜pqgpt9_fckÖti,composite-clock˜rsper_32k_alwon_fckÖfixed-factor-clock˜Gv�ècper_l4_ickÖfixed-factor-clock˜Hv�ètclock@1010 ti,clksel”Öclock-gpio6-ickÖti,omap3-interface-clock ãgpio6_ick˜töè–clock-gpio5-ickÖti,omap3-interface-clock ãgpio5_ick˜töè—clock-gpio4-ickÖti,omap3-interface-clock ãgpio4_ick˜töè˜clock-gpio3-ickÖti,omap3-interface-clock ãgpio3_ick˜töè™clock-gpio2-ickÖti,omap3-interface-clock ãgpio2_ick˜tö èšclock-wdt3-ickÖti,omap3-interface-clock ãwdt3_ick˜tö è›clock-uart3-ickÖti,omap3-interface-clock ãuart3_ick˜tö èœclock-uart4-ickÖti,omap3-interface-clock ãuart4_ick˜töè�clock-gpt9-ickÖti,omap3-interface-clock ãgpt9_ick˜tö èžclock-gpt8-ickÖti,omap3-interface-clock ãgpt8_ick˜tö èŸclock-gpt7-ickÖti,omap3-interface-clock ãgpt7_ick˜töè clock-gpt6-ickÖti,omap3-interface-clock ãgpt6_ick˜töè¡clock-gpt5-ickÖti,omap3-interface-clock ãgpt5_ick˜töè¢clock-gpt4-ickÖti,omap3-interface-clock ãgpt4_ick˜töè£clock-gpt3-ickÖti,omap3-interface-clock ãgpt3_ick˜töè¤clock-gpt2-ickÖti,omap3-interface-clock ãgpt2_ick˜töè¥clock-mcbsp2-ickÖti,omap3-interface-clock ãmcbsp2_ick˜töè¦clock-mcbsp3-ickÖti,omap3-interface-clock ãmcbsp3_ick˜töè§clock-mcbsp4-ickÖti,omap3-interface-clock ãmcbsp4_ick˜töè¨emu_src_ckÖti,clkdm-gate-clock˜uè)secure_32k_fckÖ fixed-clockD€èvgpt12_fckÖfixed-factor-clock˜vv�èwdt1_fckÖfixed-factor-clock˜vv�security_l4_ick2Öfixed-factor-clock˜Hv�èwclock@a14 ti,clksel” Öclock-aes1-ickÖti,omap3-interface-clock ãaes1_ick˜wöèclock-rng-ickÖti,omap3-interface-clockãrng_ick˜wöèÿclock-sha11-ickÖti,omap3-interface-clock ãsha11_ick˜wöclock-des1-ickÖti,omap3-interface-clock ãdes1_ick˜wöclock-pka-ickÖti,omap3-interface-clockãpka_ick˜xöclock@f00 ti,clksel”Öclock-cam-mclkÖti,gate-clock ãcam_mclk˜yö¼clock-csi2-96m-fckÖti,gate-clock ãcsi2_96m_fck˜öèÜcam_ick@f10Ö!ti,omap3-no-wait-interface-clock˜H”öèÛsecurity_l3_ickÖfixed-factor-clock˜Fv�èxssi_l4_ickÖfixed-factor-clock˜Hv�è\sr_l4_ickÖfixed-factor-clock˜Hv�dpll2_fck@40Öti,divider-clock˜.öT”@_èzdpll2_ck@4Öti,omap3-dpll-clock˜!z”$@4ñ è{dpll2_m2_ck@44Öti,divider-clock˜{T”D_è|iva2_ck@0Öti,wait-gate-clock˜|”öèÝclock@a18 ti,clksel” Öclock-mad2d-ickÖti,omap3-interface-clock ãmad2d_ick˜Föèàclock-usbtll-ickÖti,omap3-interface-clock ãusbtll_ick˜[öèØssi_ssr_fck_3430es2Öti,composite-clock˜}~èssi_sst_fck_3430es2Öfixed-factor-clock˜v�èsys_d2_ckÖfixed-factor-clock˜!v�èIomap_96m_d2_fckÖfixed-factor-clock˜Xv�èJomap_96m_d4_fckÖfixed-factor-clock˜Xv�èKomap_96m_d8_fckÖfixed-factor-clock˜Xv�èLomap_96m_d10_fckÖfixed-factor-clock˜Xv� èMdpll5_m2_d4_ckÖfixed-factor-clock˜€v�èNdpll5_m2_d8_ckÖfixed-factor-clock˜€v�èOdpll5_m2_d16_ckÖfixed-factor-clock˜€v�èPdpll5_m2_d20_ckÖfixed-factor-clock˜€v�èQusim_fckÖti,composite-clock˜�‚dpll5_ck@d04Öti,omap3-dpll-clock˜!!”  $ L 4ñèƒdpll5_m2_ck@d50Öti,divider-clock˜ƒT” P_è€sgx_gate_fck@b00Öti,composite-gate-clock˜.ö” è‹core_d3_ckÖfixed-factor-clock˜.v�è„core_d4_ckÖfixed-factor-clock˜.v�è…core_d6_ckÖfixed-factor-clock˜.v�è†omap_192m_alwon_fckÖfixed-factor-clock˜%v�è‡core_d2_ckÖfixed-factor-clock˜.v�èˆsgx_mux_fck@b40Öti,composite-mux-clock ˜„…†2‡ˆ‰Š” @èŒsgx_fckÖti,composite-clock˜‹Œèsgx_ick@b10Öti,wait-gate-clock˜F” öèácpefuse_fck@a08Öti,gate-clock˜!” öèÕts_fck@a08Öti,gate-clock˜G” öèÖusbtll_fck@a08Öti,wait-gate-clock˜€” öè×dss_ick_3430es2@e10Öti,omap3-dss-interface-clock˜H”öè¶usbhost_120m_fck@1400Öti,gate-clock˜€”öèâusbhost_48m_fck@1400Öti,dss-gate-clock˜8”öèãusbhost_ick@1410Öti,omap3-dss-interface-clock˜H”öèäclockdomainscore_l3_clkdmti,clockdomain˜�Ždpll3_clkdmti,clockdomain˜dpll1_clkdmti,clockdomain˜per_clkdmti,clockdomainh˜��‘’“”•–—˜™š›œ�žŸ ¡¢£¤¥¦§¨emu_clkdmti,clockdomain˜)dpll4_clkdmti,clockdomain˜wkup_clkdmti,clockdomain$˜©ª«¬­®¯°±dss_clkdmti,clockdomain˜²³´µ¶core_l4_clkdmti,clockdomain”˜·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖרÙÚcam_clkdmti,clockdomain˜ÛÜiva2_clkdmti,clockdomain˜Ýdpll2_clkdmti,clockdomain˜{d2d_clkdmti,clockdomain ˜Þßàdpll5_clkdmti,clockdomain˜ƒsgx_clkdmti,clockdomain˜áusbhost_clkdmti,clockdomain ˜âãätarget-module@48320000ti,sysc-omap2ti,sysc”H2H2 revsysc˜^®Ÿfckick+ H2counter@0ti,omap-counter32k” interrupt-controller@48200000ti,omap3-intc,”H ètarget-module@48056000ti,sysc-omap2ti,sysc”H`H`,H`(revsyscsyss #  (˜ZŸick+ H`dma-controller@0ti,omap3430-sdmati,omap-sdma”ð -8 E`ègpio@48310000ti,omap3-gpio”H1ðûgpio1Rdt,è"gpio@49050000ti,omap3-gpio”Iðûgpio2dt,gpio@49052000ti,omap3-gpio”I ðûgpio3dt,gpio@49054000ti,omap3-gpio”I@ð ûgpio4dt,èügpio@49056000ti,omap3-gpio”I`ð!ûgpio5dt,èögpio@49058000ti,omap3-gpio”I€ð"ûgpio6dt,èserial@4806a000ti,omap3-uart”H  €HåR512:txrxûuart1DÜlserial@4806c000ti,omap3-uart”HÀ€IåJ534:txrxûuart2DÜl”default¢æserial@49020000ti,omap3-uart”I€J556:txrxûuart3DÜli2c@48070000 ti,omap3-i2c”H€ð8+ûi2c1”default¢çD'¬@twl@48”Hð ˜èŸfck ti,twl4030,”default¢éêaudioti,twl4030-audiocodecrtcti,twl4030-rtcð bciti,twl4030-bcið ¬ëºì Ævac×0Ôã–watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1¦-ÆÀ¾-ÆÀèôregulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4¦w@¾w@èñregulator-vdd1ti,twl4030-vdd1¦ 'À¾ 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mpusidetoneðYZ¹commontxrxsidetoneÉ€ûmcbsp3mcbsp3_sidetone5:txrx˜§Ÿfckick zdisabledmcbsp@49026000ti,omap3-mcbsp”I`ÿmpu ð67 ¹commontxrxÉ€ûmcbsp45:txrx˜ŸfckØ zdisabledmcbsp@48096000ti,omap3-mcbsp”H `ÿmpu ðQR ¹commontxrxÉ€ûmcbsp55:txrx˜Ÿfck zdisabledsham@480c3000ti,omap3-shamûsham”H 0dð15E:rxtarget-module@48318000ti,sysc-omap2-timerti,sysc”H1€H1€H1€revsyscsyss ' (˜°Ÿfckick+ H1€éýtimer@0ti,omap3430-timer”€˜Ÿfckð%'Gtarget-module@49032000ti,sysc-omap2-timerti,sysc”I I I revsyscsyss ' (˜¥Ÿfckick+ I timer@0ti,omap3430-timer”ð&timer@49034000ti,omap3430-timer”I@ð'ûtimer3timer@49036000ti,omap3430-timer”I`ð(ûtimer4timer@49038000ti,omap3430-timer”I€ð)ûtimer5>timer@4903a000ti,omap3430-timer”I ð*ûtimer6>timer@4903c000ti,omap3430-timer”IÀð+ûtimer7>timer@4903e000ti,omap3430-timer”Iàð,ûtimer8K>timer@49040000ti,omap3430-timer”Ið-ûtimer9Ktimer@48086000ti,omap3430-timer”H`ð.ûtimer10Kè%timer@48088000ti,omap3430-timer”H€ð/ûtimer11Ktarget-module@48304000ti,sysc-omap2-timerti,sysc”H0@H0@H0@revsyscsyss ' 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ti,omap3-ssiûssizokay”H€H�sysgddðG¹gdd_mpu+ ˜ Ÿssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-port”H H¨txrxðCDssi-port@4805b000ti,omap3-ssi-port”H°H¸txrxðEFpinmux@480025d8 ti,omap3-padconfpinctrl-single”H%Ø$+ ,A_ÿisp@480bc000 ti,omap3-isp”H ÀüH Ø|ð ��l ¤Ö”default¢èðports+port@0”endpointó ° ½ Êèòbandgap@48002524”H%$ti,omap34xx-bandgap Öètarget-module@480cb000ti,sysc-omap3430-srti,syscûsmartreflex_core”H °$sysc ˜Ÿfck+ H °smartreflex@0ti,omap3-smartreflex-core”ðtarget-module@480c9000ti,sysc-omap3430-srti,syscûsmartreflex_mpu_iva”H �$sysc ˜Ÿfck+ H �smartreflex@480c9000ti,omap3-smartreflex-mpu-iva”ðtarget-module@50000000ti,sysc-omap2ti,sysc”Prev˜áŸfckick+ P@opp-tableoperating-points-v2-ti-cpu�èopp1-125000000 ìsY@ óà˜à˜à˜ ÿÿÿÿopp2-250000000 ìæ²€ óg8g8g8 ÿÿÿÿ opp3-500000000 ìÍe óO€O€O€ ÿÿÿÿopp4-550000000 ì ÈU€ ótxtxtx ÿÿÿÿopp5-600000000 ì#ÃF ó™p™p™p ÿÿÿÿopp6-720000000 ì*êT ó™p™p™p ÿÿÿÿ thermal-zonescpu-thermal )ú ?è MN  Ztripscpu_alert j8€ vÐ�passiveècpu_crit j_� vÐ �criticalcooling-mapsmap0 � †ÿÿÿÿÿÿÿÿmemory@80000000ˆmemory”€leds gpio-leds”default¢user0 •user0 m ›noneled1 •led1 m ›cpu0led2 •led2 m ›noneoscillatorÖ fixed-clockDŒº€èègpio_keys gpio-keys”default¢ !sysboot2 •sysboot2 m" ± ¼sysboot5 •sysboot5 m" ± ¼gpio1 •gpio1 m ± ¼gpio2 •gpio2 m ± ¼soundti,omap-twl4030 Êomap3logic Ó#pwm-10ti,omap-dmtimer-pwm”default¢$ Ü%L æè*displaynewhaven,nhd-4.3-480272ef-atxl •15”default¢& ö' öportendpointó(èbacklightpwm-backlight”default¢) *LK@,  (2<FPZd $ öè'regulator-vddvarioregulator-fixed —vddvarioîè regulator-vdd33aregulator-fixed—vdd33aîè  compatibleinterrupt-parent#address-cells#size-cellsmodelstdout-pathi2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-points-v2#cooling-cellscpu0-supplyphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsclock-output-namesti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,dividersti,low-power-stopti,lockti,low-power-bypassti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyio-channelsio-channel-namesti,bb-uvoltti,bb-uampregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnsstatus#io-channel-cellsti,use_poweroffvaa-supplyvdd-supplyvdd_io-supplyinput-clock-frequencypixel-clock-frequencyremote-endpointreadonlyvio-supplytouchscreen-fuzz-xtouchscreen-fuzz-ytouchscreen-fuzz-pressuretouchscreen-size-xtouchscreen-size-ytouchscreen-max-pressureti,x-plate-ohmsti,esd-recovery-timeout-ms#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyspi-cphaspi-cpolpagesizeaddress-widthti,dual-voltpbias-supplycd-gpiosvmmc-supplybus-widthcap-power-off-card#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthti,nand-ecc-optrb-gpiosgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nsgpmc,device-widthbank-widthgpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressdr_modegpmc,wait-pingpmc,burst-lengthgpmc,wait-monitoring-nsgpmc,clk-activation-nsmultipointnum-epsram-bitsinterface-typeusb-phyphysphy-namespowervdds_dsi-supplyvdda_video-supplydata-linesiommusti,phy-typehsync-activevsync-activepclk-sample#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicelabellinux,default-triggerlinux,codewakeup-sourceti,modelti,mcbspti,timersti,clock-sourcebacklightenable-gpiospwmsbrightness-levelsdefault-brightness-level