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H1Ç"dpll4_m2x2_mul_ck¨fixed-factor-clockƒ"HSÇ#dpll4_m2x2_ck@d00¨ti,gate-clockƒ#È ]Ç$omap_96m_alwon_fck¨fixed-factor-clockƒ$HSÇ0dpll3_ck@d00¨ti,omap3-dpll-core-clockƒ  @ 0Çclock@1140 ti,clksel@¨clock-dpll3-m3¨ti,divider-clock µdpll3_m3_ckƒÈ&1Ç*clock-dpll4-m6¨ti,divider-clock µdpll4_m6_ckƒÈ&?1Ç<clock-emu-src-mux¨ ti,mux-clockµemu_src_mux_ckƒ %&'Çtclock-pclk-fck¨ti,divider-clock µpclk_fckƒ(È&1clock-pclkx2-fck¨ti,divider-clock µpclkx2_fckƒ(È&1clock-atclk-fck¨ti,divider-clock µatclk_fckƒ(È&1clock-traceclk-src-fck¨ ti,mux-clockµtraceclk_src_fckƒ %&'ÈÇ)clock-traceclk-fck¨ti,divider-clock µtraceclk_fckƒ)È &1dpll3_m3x2_mul_ck¨fixed-factor-clockƒ*HSÇ+dpll3_m3x2_ck@d00¨ti,gate-clockƒ+È  ]Ç,emu_core_alwon_ck¨fixed-factor-clockƒ,HSÇ%sys_altclk¨ fixed-clockÇ3mcbsp_clks¨ fixed-clockÇcore_ck¨fixed-factor-clockƒHSÇ-dpll1_fck@940¨ti,divider-clockƒ-È& @1Ç.dpll1_ck@904¨ti,omap3-dpll-clockƒ .  $ @ 4Çdpll1_x2_ck¨fixed-factor-clockƒHSÇ/dpll1_x2m2_ck@944¨ti,divider-clockƒ/& D1ÇCcm_96m_fck¨fixed-factor-clockƒ0HSÇ1clock@d40 ti,clksel @¨clock-dpll3-m2¨ti,divider-clock µdpll3_m2_ckƒÈ&1Çclock-omap-96m-fck¨ ti,mux-clock µomap_96m_fckƒ1 ÈÇWclock-omap-54m-fck¨ ti,mux-clock µomap_54m_fckƒ23ÈÇ?clock-omap-48m-fck¨ ti,mux-clock µomap_48m_fckƒ43ÈÇ7clock@e40 ti,clksel@¨clock-dpll4-m3¨ti,divider-clock µdpll4_m3_ckƒÈ& 1Ç5clock-dpll4-m4¨ti,divider-clock µdpll4_m4_ckƒ&1Ç8dpll4_m3x2_mul_ck¨fixed-factor-clockƒ5HSÇ6dpll4_m3x2_ck@d00¨ti,gate-clockƒ6È ]Ç2cm_96m_d2_fck¨fixed-factor-clockƒ1HSÇ4omap_12m_fck¨fixed-factor-clockƒ7HSÇXdpll4_m4x2_mul_ck¨ti,fixed-factor-clockƒ8s�ŽÇ9dpll4_m4x2_ck@d00¨ti,gate-clockƒ9È ]ŽÇ\dpll4_m5_ck@f40¨ti,divider-clockƒ&?@1Ç:dpll4_m5x2_mul_ck¨ti,fixed-factor-clockƒ:s�ŽÇ;dpll4_m5x2_ck@d00¨ti,gate-clockƒ;È ]ŽÇxdpll4_m6x2_mul_ck¨fixed-factor-clockƒ<HSÇ=dpll4_m6x2_ck@d00¨ti,gate-clockƒ=È ]Ç>emu_per_alwon_ck¨fixed-factor-clockƒ>HSÇ&clock@d70 ti,clksel p¨clock-clkout2-src-gate¨ ti,composite-no-wait-gate-clockµclkout2_src_gate_ckƒ-ÈÇAclock-clkout2-src-mux¨ti,composite-mux-clockµclkout2_src_mux_ckƒ- 1?ÇBclock-sys-clkout2¨ti,divider-clock µsys_clkout2ƒ@È&@¡clkout2_src_ck¨ti,composite-clockƒABÇ@mpu_ck¨fixed-factor-clockƒCHSÇDarm_fck@924¨ti,divider-clockƒD $&emu_mpu_alwon_ck¨fixed-factor-clockƒDHSÇ'clock@a40 ti,clksel @¨clock-l3-ick¨ti,divider-clockµl3_ickƒ-&1ÇEclock-l4-ick¨ti,divider-clockµl4_ickƒEÈ&1ÇGclock-gpt10-mux-fck¨ti,composite-mux-clockµgpt10_mux_fckƒF ÈÇTclock-gpt11-mux-fck¨ti,composite-mux-clockµgpt11_mux_fckƒF ÈÇVclock-ssi-ssr-div-fck-3430es2¨ti,composite-divider-clockµssi_ssr_div_fck_3430es2ƒ!È$·Ç}clock@c40 ti,clksel @¨clock-rm-ick¨ti,divider-clockµrm_ickƒGÈ&1clock-gpt1-mux-fck¨ti,composite-mux-clock µgpt1_mux_fckƒF Ç_clock-usim-mux-fck¨ti,composite-mux-clock µusim_mux_fck(ƒ HIJKLMNOPÈ1Ç�clock@a00 ti,clksel ¨clock-gpt10-gate-fck¨ti,composite-gate-clockµgpt10_gate_fckƒ È ÇSclock-gpt11-gate-fck¨ti,composite-gate-clockµgpt11_gate_fckƒ È ÇUclock-mmchs2-fck¨ti,wait-gate-clock µmmchs2_fckƒÈǶclock-mmchs1-fck¨ti,wait-gate-clock µmmchs1_fckƒÈÇ·clock-i2c3-fck¨ti,wait-gate-clock µi2c3_fckƒÈǸclock-i2c2-fck¨ti,wait-gate-clock µi2c2_fckƒÈǹclock-i2c1-fck¨ti,wait-gate-clock µi2c1_fckƒÈǺclock-mcbsp5-gate-fck¨ti,composite-gate-clockµmcbsp5_gate_fckƒÈ Çclock-mcbsp1-gate-fck¨ti,composite-gate-clockµmcbsp1_gate_fckƒÈ Ç clock-mcspi4-fck¨ti,wait-gate-clock µmcspi4_fckƒQÈÇ»clock-mcspi3-fck¨ti,wait-gate-clock µmcspi3_fckƒQÈǼclock-mcspi2-fck¨ti,wait-gate-clock µmcspi2_fckƒQÈǽclock-mcspi1-fck¨ti,wait-gate-clock µmcspi1_fckƒQÈǾclock-uart2-fck¨ti,wait-gate-clock µuart2_fckƒQÈÇ¿clock-uart1-fck¨ti,wait-gate-clock µuart1_fckƒQÈ ÇÀclock-hdq-fck¨ti,wait-gate-clockµhdq_fckƒRÈÇÁclock-modem-fck¨ti,omap3-interface-clock µmodem_fckƒ ÈÇÝclock-mspro-fck¨ti,wait-gate-clock µmspro_fckƒÈclock-ssi-ssr-gate-fck-3430es2¨ ti,composite-no-wait-gate-clockµssi_ssr_gate_fck_3430es2ƒ!ÈÇ|clock-mmchs3-fck¨ti,wait-gate-clock µmmchs3_fckƒÈÇÙgpt10_fck¨ti,composite-clockƒSTgpt11_fck¨ti,composite-clockƒUVcore_96m_fck¨fixed-factor-clockƒWHSÇcore_48m_fck¨fixed-factor-clockƒ7HSÇQcore_12m_fck¨fixed-factor-clockƒXHSÇRcore_l3_ick¨fixed-factor-clockƒEHSÇYclock@a10 ti,clksel ¨clock-sdrc-ick¨ti,wait-gate-clock µsdrc_ickƒYÈÇŒclock-mmchs2-ick¨ti,omap3-interface-clock µmmchs2_ickƒZÈÇÂclock-mmchs1-ick¨ti,omap3-interface-clock µmmchs1_ickƒZÈÇÃclock-hdq-ick¨ti,omap3-interface-clockµhdq_ickƒZÈÇÄclock-mcspi4-ick¨ti,omap3-interface-clock µmcspi4_ickƒZÈÇÅclock-mcspi3-ick¨ti,omap3-interface-clock µmcspi3_ickƒZÈÇÆclock-mcspi2-ick¨ti,omap3-interface-clock µmcspi2_ickƒZÈÇÇclock-mcspi1-ick¨ti,omap3-interface-clock µmcspi1_ickƒZÈÇÈclock-i2c3-ick¨ti,omap3-interface-clock µi2c3_ickƒZÈÇÉclock-i2c2-ick¨ti,omap3-interface-clock µi2c2_ickƒZÈÇÊclock-i2c1-ick¨ti,omap3-interface-clock µi2c1_ickƒZÈÇËclock-uart2-ick¨ti,omap3-interface-clock µuart2_ickƒZÈÇÌclock-uart1-ick¨ti,omap3-interface-clock µuart1_ickƒZÈ ÇÍclock-gpt11-ick¨ti,omap3-interface-clock µgpt11_ickƒZÈ ÇÎclock-gpt10-ick¨ti,omap3-interface-clock µgpt10_ickƒZÈ ÇÏclock-mcbsp5-ick¨ti,omap3-interface-clock µmcbsp5_ickƒZÈ ÇÐclock-mcbsp1-ick¨ti,omap3-interface-clock µmcbsp1_ickƒZÈ ÇÑclock-omapctrl-ick¨ti,omap3-interface-clock µomapctrl_ickƒZÈÇÒclock-aes2-ick¨ti,omap3-interface-clock µaes2_ickƒZÈÇclock-sha12-ick¨ti,omap3-interface-clock µsha12_ickƒZÈÇÓclock-icr-ick¨ti,omap3-interface-clockµicr_ickƒZÈclock-des2-ick¨ti,omap3-interface-clock µdes2_ickƒZÈclock-mspro-ick¨ti,omap3-interface-clock µmspro_ickƒZÈclock-mailboxes-ick¨ti,omap3-interface-clockµmailboxes_ickƒZÈclock-sad2d-ick¨ti,omap3-interface-clock µsad2d_ickƒEÈÇÞclock-hsotgusb-ick-3430es2¨"ti,omap3-hsotgusb-interface-clockµhsotgusb_ick_3430es2ƒYÈÇ�clock-ssi-ick-3430es2¨ti,omap3-ssi-interface-clockµssi_ick_3430es2ƒ[ÈÇïclock-mmchs3-ick¨ti,omap3-interface-clock µmmchs3_ickƒZÈÇØgpmc_fck¨fixed-factor-clockƒYHScore_l4_ick¨fixed-factor-clockƒGHSÇZclock@e00 ti,clksel¨clock-dss-tv-fck¨ti,gate-clock µdss_tv_fckƒ?ÈDZclock-dss-96m-fck¨ti,gate-clock µdss_96m_fckƒWÈDzclock-dss2-alwon-fck¨ti,gate-clockµdss2_alwon_fckƒ Èdzclock-dss1-alwon-fck-3430es2¨ti,dss-gate-clockµdss1_alwon_fck_3430es2ƒ\ÈŽÇ´dummy_ck¨ fixed-clockclock@c00 ti,clksel ¨clock-gpt1-gate-fck¨ti,composite-gate-clockµgpt1_gate_fckƒ ÈÇ^clock-gpio1-dbck¨ti,gate-clock µgpio1_dbckƒ]ÈǨclock-wdt2-fck¨ti,wait-gate-clock µwdt2_fckƒ]ÈÇ©clock-sr1-fck¨ti,wait-gate-clockµsr1_fckƒ ÈÇòclock-sr2-fck¨ti,wait-gate-clockµsr2_fckƒ ÈÇñclock-usim-gate-fck¨ti,composite-gate-clockµusim_gate_fckƒWÈ Ç€gpt1_fck¨ti,composite-clockƒ^_Çëwkup_32k_fck¨fixed-factor-clockƒFHSÇ]clock@c10 ti,clksel ¨clock-wdt2-ick¨ti,omap3-interface-clock µwdt2_ickƒ`ÈǪclock-wdt1-ick¨ti,omap3-interface-clock µwdt1_ickƒ`ÈÇ«clock-gpio1-ick¨ti,omap3-interface-clock µgpio1_ickƒ`ÈǬclock-omap-32ksync-ick¨ti,omap3-interface-clockµomap_32ksync_ickƒ`ÈÇ­clock-gpt12-ick¨ti,omap3-interface-clock µgpt12_ickƒ`ÈÇ®clock-gpt1-ick¨ti,omap3-interface-clock µgpt1_ickƒ`Èǯclock-usim-ick¨ti,omap3-interface-clock µusim_ickƒ`È ǰper_96m_fck¨fixed-factor-clockƒ0HSÇper_48m_fck¨fixed-factor-clockƒ7HSÇaclock@1000 ti,clksel¨clock-uart3-fck¨ti,wait-gate-clock µuart3_fckƒaÈ ÇŽclock-gpt2-gate-fck¨ti,composite-gate-clockµgpt2_gate_fckƒ ÈÇcclock-gpt3-gate-fck¨ti,composite-gate-clockµgpt3_gate_fckƒ ÈÇeclock-gpt4-gate-fck¨ti,composite-gate-clockµgpt4_gate_fckƒ ÈÇgclock-gpt5-gate-fck¨ti,composite-gate-clockµgpt5_gate_fckƒ ÈÇiclock-gpt6-gate-fck¨ti,composite-gate-clockµgpt6_gate_fckƒ ÈÇkclock-gpt7-gate-fck¨ti,composite-gate-clockµgpt7_gate_fckƒ ÈÇmclock-gpt8-gate-fck¨ti,composite-gate-clockµgpt8_gate_fckƒ È Çoclock-gpt9-gate-fck¨ti,composite-gate-clockµgpt9_gate_fckƒ È Çqclock-gpio6-dbck¨ti,gate-clock µgpio6_dbckƒbÈÇ�clock-gpio5-dbck¨ti,gate-clock µgpio5_dbckƒbÈÇ�clock-gpio4-dbck¨ti,gate-clock µgpio4_dbckƒbÈÇ‘clock-gpio3-dbck¨ti,gate-clock µgpio3_dbckƒbÈÇ’clock-gpio2-dbck¨ti,gate-clock µgpio2_dbckƒbÈ Ç“clock-wdt3-fck¨ti,wait-gate-clock µwdt3_fckƒbÈ Ç”clock-mcbsp2-gate-fck¨ti,composite-gate-clockµmcbsp2_gate_fckƒÈÇ clock-mcbsp3-gate-fck¨ti,composite-gate-clockµmcbsp3_gate_fckƒÈÇclock-mcbsp4-gate-fck¨ti,composite-gate-clockµmcbsp4_gate_fckƒÈÇclock@1040 ti,clksel@¨clock-gpt2-mux-fck¨ti,composite-mux-clock µgpt2_mux_fckƒF Çdclock-gpt3-mux-fck¨ti,composite-mux-clock µgpt3_mux_fckƒF ÈÇfclock-gpt4-mux-fck¨ti,composite-mux-clock µgpt4_mux_fckƒF ÈÇhclock-gpt5-mux-fck¨ti,composite-mux-clock µgpt5_mux_fckƒF ÈÇjclock-gpt6-mux-fck¨ti,composite-mux-clock µgpt6_mux_fckƒF ÈÇlclock-gpt7-mux-fck¨ti,composite-mux-clock µgpt7_mux_fckƒF ÈÇnclock-gpt8-mux-fck¨ti,composite-mux-clock µgpt8_mux_fckƒF ÈÇpclock-gpt9-mux-fck¨ti,composite-mux-clock µgpt9_mux_fckƒF ÈÇrgpt2_fck¨ti,composite-clockƒcdÇìgpt3_fck¨ti,composite-clockƒefgpt4_fck¨ti,composite-clockƒghgpt5_fck¨ti,composite-clockƒijgpt6_fck¨ti,composite-clockƒklgpt7_fck¨ti,composite-clockƒmngpt8_fck¨ti,composite-clockƒopgpt9_fck¨ti,composite-clockƒqrper_32k_alwon_fck¨fixed-factor-clockƒFHSÇbper_l4_ick¨fixed-factor-clockƒGHSÇsclock@1010 ti,clksel¨clock-gpio6-ick¨ti,omap3-interface-clock µgpio6_ickƒsÈÇ•clock-gpio5-ick¨ti,omap3-interface-clock µgpio5_ickƒsÈÇ–clock-gpio4-ick¨ti,omap3-interface-clock µgpio4_ickƒsÈÇ—clock-gpio3-ick¨ti,omap3-interface-clock µgpio3_ickƒsÈǘclock-gpio2-ick¨ti,omap3-interface-clock µgpio2_ickƒsÈ Ç™clock-wdt3-ick¨ti,omap3-interface-clock µwdt3_ickƒsÈ Çšclock-uart3-ick¨ti,omap3-interface-clock µuart3_ickƒsÈ Ç›clock-uart4-ick¨ti,omap3-interface-clock µuart4_ickƒsÈÇœclock-gpt9-ick¨ti,omap3-interface-clock µgpt9_ickƒsÈ Ç�clock-gpt8-ick¨ti,omap3-interface-clock µgpt8_ickƒsÈ Çžclock-gpt7-ick¨ti,omap3-interface-clock µgpt7_ickƒsÈÇŸclock-gpt6-ick¨ti,omap3-interface-clock µgpt6_ickƒsÈÇ clock-gpt5-ick¨ti,omap3-interface-clock µgpt5_ickƒsÈÇ¡clock-gpt4-ick¨ti,omap3-interface-clock µgpt4_ickƒsÈÇ¢clock-gpt3-ick¨ti,omap3-interface-clock µgpt3_ickƒsÈÇ£clock-gpt2-ick¨ti,omap3-interface-clock µgpt2_ickƒsÈǤclock-mcbsp2-ick¨ti,omap3-interface-clock µmcbsp2_ickƒsÈÇ¥clock-mcbsp3-ick¨ti,omap3-interface-clock µmcbsp3_ickƒsÈǦclock-mcbsp4-ick¨ti,omap3-interface-clock µmcbsp4_ickƒsÈǧemu_src_ck¨ti,clkdm-gate-clockƒtÇ(secure_32k_fck¨ fixed-clock€Çugpt12_fck¨fixed-factor-clockƒuHSÇíwdt1_fck¨fixed-factor-clockƒuHSsecurity_l4_ick2¨fixed-factor-clockƒGHSÇvclock@a14 ti,clksel ¨clock-aes1-ick¨ti,omap3-interface-clock µaes1_ickƒvÈÇclock-rng-ick¨ti,omap3-interface-clockµrng_ickƒvÈÇæclock-sha11-ick¨ti,omap3-interface-clock µsha11_ickƒvÈclock-des1-ick¨ti,omap3-interface-clock µdes1_ickƒvÈclock-pka-ick¨ti,omap3-interface-clockµpka_ickƒwÈclock@f00 ti,clksel¨clock-cam-mclk¨ti,gate-clock µcam_mclkƒxÈŽclock-csi2-96m-fck¨ti,gate-clock µcsi2_96m_fckƒÈÇÛcam_ick@f10¨!ti,omap3-no-wait-interface-clockƒGÈÇÚsecurity_l3_ick¨fixed-factor-clockƒEHSÇwssi_l4_ick¨fixed-factor-clockƒGHSÇ[sr_l4_ick¨fixed-factor-clockƒGHSdpll2_fck@40¨ti,divider-clockƒ-È&@1Çydpll2_ck@4¨ti,omap3-dpll-clockƒ y$@4ÃÕÝÇzdpll2_m2_ck@44¨ti,divider-clockƒz&D1Ç{iva2_ck@0¨ti,wait-gate-clockƒ{ÈÇÜclock@a18 ti,clksel ¨clock-mad2d-ick¨ti,omap3-interface-clock µmad2d_ickƒEÈÇßclock-usbtll-ick¨ti,omap3-interface-clock µusbtll_ickƒZÈÇ×ssi_ssr_fck_3430es2¨ti,composite-clockƒ|}Ç~ssi_sst_fck_3430es2¨fixed-factor-clockƒ~HSÇîsys_d2_ck¨fixed-factor-clockƒ HSÇHomap_96m_d2_fck¨fixed-factor-clockƒWHSÇIomap_96m_d4_fck¨fixed-factor-clockƒWHSÇJomap_96m_d8_fck¨fixed-factor-clockƒWHSÇKomap_96m_d10_fck¨fixed-factor-clockƒWHS ÇLdpll5_m2_d4_ck¨fixed-factor-clockƒHSÇMdpll5_m2_d8_ck¨fixed-factor-clockƒHSÇNdpll5_m2_d16_ck¨fixed-factor-clockƒHSÇOdpll5_m2_d20_ck¨fixed-factor-clockƒHSÇPusim_fck¨ti,composite-clockƒ€�dpll5_ck@d04¨ti,omap3-dpll-clockƒ   $ L 4ÃÕÇ‚dpll5_m2_ck@d50¨ti,divider-clockƒ‚& P1Çsgx_gate_fck@b00¨ti,composite-gate-clockƒ-È ÇŠcore_d3_ck¨fixed-factor-clockƒ-HSǃcore_d4_ck¨fixed-factor-clockƒ-HSÇ„core_d6_ck¨fixed-factor-clockƒ-HSÇ…omap_192m_alwon_fck¨fixed-factor-clockƒ$HSdžcore_d2_ck¨fixed-factor-clockƒ-HSLJsgx_mux_fck@b40¨ti,composite-mux-clock ƒƒ„…1†‡ˆ‰ @Ç‹sgx_fck¨ti,composite-clockƒŠ‹Çósgx_ick@b10¨ti,wait-gate-clockƒE ÈÇàcpefuse_fck@a08¨ti,gate-clockƒ  ÈÇÔts_fck@a08¨ti,gate-clockƒF ÈÇÕusbtll_fck@a08¨ti,wait-gate-clockƒ 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2device_typeregclocksclock-namesclock-latencyoperating-points-v2#cooling-cellsphandleinterruptsti,hwmodsstatusranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-masksysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsclock-output-namesti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,dividersti,low-power-stopti,lockti,low-power-bypassti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extended#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supply#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinsmultipointnum-epsram-bitsiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-device