Ð þí;86�(ˆ6XBeagleBoard BeagleV-Fire#!beagle,beaglev-firemicrochip,mpfscpus,B@cpu@0 !sifive,e51sifive,rocket0riscv?cpuK@^€k@x |rv64imac†rv64i$•imaczicntrzicsrzifenceizihpmª ±disabled¸interrupt-controllerÀ!riscv,cpu-intcѸ cpu@1#!sifive,u54-mcsifive,rocket0riscvæ@ù@€ ?cpuK@^@k€)4  ?riscv,sv39x |rv64imafdc†rv64i(•imafdczicntrzicsrzifenceizihpmªHR±okay¸interrupt-controllerÀ!riscv,cpu-intcѸ cpu@2#!sifive,u54-mcsifive,rocket0riscvæ@ù@€ ?cpuK@^@k€)4  ?riscv,sv39x |rv64imafdc†rv64i(•imafdczicntrzicsrzifenceizihpmªHR±okay¸interrupt-controllerÀ!riscv,cpu-intcѸ cpu@3#!sifive,u54-mcsifive,rocket0riscvæ@ù@€ ?cpuK@^@k€)4  ?riscv,sv39x |rv64imafdc†rv64i(•imafdczicntrzicsrzifenceizihpmªHR±okay¸interrupt-controllerÀ!riscv,cpu-intcѸcpu@4#!sifive,u54-mcsifive,rocket0riscvæ@ù@€ ?cpuK@^@k€)4  ?riscv,sv39x |rv64imafdc†rv64i(•imafdczicntrzicsrzifenceizihpmªHR±okay¸interrupt-controllerÀ!riscv,cpu-intcѸcpu-mapcluster0core0ccore1ccore2ccore3ccore4cmssrefclk !fixed-clockgtsY@¸syscontroller!microchip,mpfs-sys-controller„‹ ±okaymssclkclk !fixed-clockgtÄ´¸soc !simple-bus¥cache-controller@20100005!microchip,mpfs-ccachesifive,fu540-c000-ccachecachexM@¬`m ¸Æ ׸clint@2000000&!sifive,fu540-c000-clintsifive,clint0xÀPâ      interrupt-controller@c000000)!sifive,fu540-c000-plicsifive,plic-1.0.0x ÀÑHâ     öº¸ dma-controller@3000000!!microchip,mpfs-pdmasifive,pdma0x€Æ  × clkcfg@20002000!microchip,mpfs-clkcfg x >ªg¸clock-controller@38010000!microchip,mpfs-ccc@x8899g ±disabledclock-controller@38040000!microchip,mpfs-ccc@x8899g ±disabledclock-controller@38100000!microchip,mpfs-ccc@x88 99 g±okayª:&pll0_ref0pll0_ref1pll1_ref0pll1_ref1dll0_refdll1_refclock-controller@38400000!microchip,mpfs-ccc@x8@8€9@9€g ±disabledserial@20000000 !ns16550ax 2?Æ ×ZIª±okayserial@20100000 !ns16550ax 2?Æ ×[Iª ±okayserial@20102000 !ns16550ax  2?Æ ×\Iª  ±disabledserial@20104000 !ns16550ax @2?Æ ×]Iª  ±disabledserial@20106000 !ns16550ax `2?Æ ×^ª I ±disabledmmc@20008000 !microchip,mpfs-sd4hccdns,sd4hcx €Æ ×XªW ë±okayeoz‹�ª¹ÆÓàspi@20108000!microchip,mpfs-spix €Æ ×6ª ±okayspi@20109000!microchip,mpfs-spix �Æ ×7ª±okayspi@21000000.!microchip,mpfs-qspimicrochip,coreqspi-rtl-v2x!Æ ×Uª ±disabledi2c@2010a000,!microchip,mpfs-i2cmicrochip,corei2c-rtl-v7x  Æ ×:ªt† ±okayi2c@2010b000,!microchip,mpfs-i2cmicrochip,corei2c-rtl-v7x °Æ ×=ªt† ±okayeeprom@50 !atmel,24c32xPsensor@10 !sony,imx219xªîúportendpoint1.can@2010c000!microchip,mpfs-canx Àª%Æ ×8 ±disabledcan@2010d000!microchip,mpfs-canx Ъ%Æ ×9 ±disabledethernet@20110000!microchip,mpfs-macbcdns,macbx  Æ ×@ABCDEBª &pclkhclkT±okay[sgmiidethernet-phy@0x¸ethernet@20112000!microchip,mpfs-macbcdns,macbx  Æ ×FGHIJKBª &pclkhclkT ±disabledgpio@20120000!microchip,mpfs-gpiox Æ ÑÀªo ±disabledgpio@20121000!microchip,mpfs-gpiox Æ ÑÀªo ±disabledgpio@20122000!microchip,mpfs-gpiox  Æ ÑÀªo±okay€×55555555555555555555555555555555‹ ©’P8_PIN3_USER_LED_0P8_PIN4_USER_LED_1P8_PIN5_USER_LED_2P8_PIN6_USER_LED_3P8_PIN7_USER_LED_4P8_PIN8_USER_LED_5P8_PIN9_USER_LED_6P8_PIN10_USER_LED_7P8_PIN11_USER_LED_8P8_PIN12_USER_LED_9P8_PIN13_USER_LED_10P8_PIN14_USER_LED_11P8_PIN15P8_PIN16P8_PIN17P8_PIN18P8_PIN19P8_PIN20P8_PIN21P8_PIN22P8_PIN23P8_PIN24P8_PIN25P8_PIN26P8_PIN27P8_PIN28P8_PIN29P8_PIN30M2_W_DISABLE1M2_W_DISABLE2VIO_ENABLESD_DETvio-enable-hog¢Œ« ·VIO_ENABLEsd-det-hog¢ŒÁ·SD_DETrtc@20124000!microchip,mpfs-rtcx @Æ ×PQª! &rtcrtcref±okayusb@20201000!microchip,mpfs-musbx Æ ×VWªÇdmamc±okay×otgmailbox@37020000!microchip,mpfs-mailbox0x7X 1Œ@7Æ ×`ß±okay¸spi@37020100.!microchip,mpfs-qspimicrochip,coreqspi-rtl-v2x7Æ ×nª±okayflash@0!jedec,spi-norë1-ýx¸ fabric-clk3 !fixed-clockgtúð€¸fabric-clk1 !fixed-clockgtsY@fabric-bus@40000000 !simple-busx¥@@ `` àà 00gpio@41100000!microchip,coregpio-rtl-v3xAªo‹�’P8_PIN31P8_PIN32P8_PIN33P8_PIN34P8_PIN35P8_PIN36P8_PIN37P8_PIN38P8_PIN39P8_PIN40P8_PIN41P8_PIN42P8_PIN43P8_PIN44P8_PIN45P8_PIN46gpio@41200000!microchip,coregpio-rtl-v3xA ªo‹´’P9_PIN11P9_PIN12P9_PIN13P9_PIN14P9_PIN15P9_PIN16P9_PIN17P9_PIN18P9_PIN21P9_PIN22P9_PIN23P9_PIN24P9_PIN25P9_PIN26P9_PIN27P9_PIN28P9_PIN29P9_PIN31P9_PIN41P9_PIN42gpio@44000000!microchip,coregpio-rtl-v3xDªo‹’B0_HSIO70NB0_HSIO71NB0_HSIO83NB0_HSIO73N_C2P_CLKNB0_HSIO70PB0_HSIO71PB0_HSIO83PB0_HSIO73N_C2P_CLKPXCVR1_RX_VALIDXCVR1_LOCKXCVR1_ERRORXCVR2_RX_VALIDXCVR2_LOCKXCVR2_ERRORXCVR3_RX_VALIDXCVR3_LOCKXCVR3_ERRORXCVR_0B_REF_CLK_PLL_LOCKXCVR_0C_REF_CLK_PLL_LOCKB0_HSIO81Ncccrefclk !fixed-clockgtúð€¸aliases/soc/serial@20000000/soc/serial@20100000/soc/serial@20102000&/soc/serial@20104000./soc/serial@20106000chosen6serial0:115200n8memory@80000000?memoryx€@±okayreserved-memory¥hss-buffer@103fc00000!shared-dma-poolx?À@Bcamera-clk !fixed-clockgtn6¸fixedregulator-0!regulator-fixed Iimx219_vanaX*¹€p*¹€¸fixedregulator-1!regulator-fixed Iimx219_vdigXw@pw@¸fixedregulator-2!regulator-fixed Iimx219_vddlXO€pO€¸ #address-cells#size-cellsmodelcompatibletimebase-frequencydevice_typei-cache-block-sizei-cache-setsi-cache-sizeregriscv,isariscv,isa-baseriscv,isa-extensionsclocksstatusphandle#interrupt-cellsinterrupt-controllerd-cache-block-sized-cache-setsd-cache-sized-tlb-setsd-tlb-sizei-tlb-setsi-tlb-sizemmu-typetlb-splitnext-level-cachecpu#clock-cellsclock-frequencymboxesmicrochip,bitstream-flashrangescache-levelcache-unifiedinterrupt-parentinterruptsinterrupts-extendedriscv,ndevdma-channels#dma-cells#reset-cellsclock-namesreg-io-widthreg-shiftcurrent-speedmax-frequencybus-widthdisable-wpcap-sd-highspeedcap-mmc-highspeedmmc-ddr-1_8vmmc-hs200-1_8vsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104VANA-supplyVDIG-supplyVDDL-supplydata-lanesclock-noncontinuouslink-frequencieslocal-mac-addressresetsphy-modephy-handlegpio-controller#gpio-cellsngpiosgpio-line-namesgpio-hogoutput-highline-nameinputinterrupt-namesdr_mode#mbox-cellsspi-max-frequencyspi-rx-bus-widthserial0serial1serial2serial3serial4stdout-pathno-mapregulator-nameregulator-min-microvoltregulator-max-microvolt