Ð þí7™83D(U3 #Microchip PolarFire-SoC Icicle KitR!microchip,mpfs-icicle-reference-rtlv2210microchip,mpfs-icicle-kitmicrochip,mpfscpus,B@cpu@0 !sifive,e51sifive,rocket0riscv?cpuK@^€k@x |rv64imac†rv64i$•imaczicntrzicsrzifenceizihpmª ±disabled¸interrupt-controllerÀ!riscv,cpu-intcѸ cpu@1#!sifive,u54-mcsifive,rocket0riscvæ@ù@€ ?cpuK@^@k€)4  ?riscv,sv39x |rv64imafdc†rv64i(•imafdczicntrzicsrzifenceizihpmªHR±okay¸interrupt-controllerÀ!riscv,cpu-intcѸ cpu@2#!sifive,u54-mcsifive,rocket0riscvæ@ù@€ ?cpuK@^@k€)4  ?riscv,sv39x |rv64imafdc†rv64i(•imafdczicntrzicsrzifenceizihpmªHR±okay¸interrupt-controllerÀ!riscv,cpu-intcѸ cpu@3#!sifive,u54-mcsifive,rocket0riscvæ@ù@€ ?cpuK@^@k€)4  ?riscv,sv39x |rv64imafdc†rv64i(•imafdczicntrzicsrzifenceizihpmªHR±okay¸interrupt-controllerÀ!riscv,cpu-intcѸ cpu@4#!sifive,u54-mcsifive,rocket0riscvæ@ù@€ ?cpuK@^@k€)4  ?riscv,sv39x |rv64imafdc†rv64i(•imafdczicntrzicsrzifenceizihpmªHR±okay¸interrupt-controllerÀ!riscv,cpu-intcѸcpu-mapcluster0core0ccore1ccore2ccore3ccore4cmssrefclk !fixed-clockgtsY@¸syscontroller!microchip,mpfs-sys-controller„±okaymssclkclk !fixed-clockgtÄ´¸soc !simple-bus‹cache-controller@20100005!microchip,mpfs-ccachesifive,fu540-c000-ccachecachexM@’`m ž¬ ½¸clint@2000000&!sifive,fu540-c000-clintsifive,clint0xÀPÈ        interrupt-controller@c000000)!sifive,fu540-c000-plicsifive,plic-1.0.0x ÀÑHÈ   ܺ¸ dma-controller@3000000!!microchip,mpfs-pdmasifive,pdma0x€¬  ½ çôclkcfg@20002000!microchip,mpfs-clkcfg x >ªgÿ¸clock-controller@38010000!microchip,mpfs-ccc@x8899g ±disabledclock-controller@38040000!microchip,mpfs-ccc@x8899g ±disabledclock-controller@38100000!microchip,mpfs-ccc@x88 99 g±okayª: pll0_ref0pll0_ref1pll1_ref0pll1_ref1dll0_refdll1_ref¸clock-controller@38400000!microchip,mpfs-ccc@x8@8€9@9€g ±disabledserial@20000000 !ns16550ax %¬ ½Z/ª ±disabledserial@20100000 !ns16550ax %¬ ½[/ª ±okayserial@20102000 !ns16550ax  %¬ ½\/ª ±okayserial@20104000 !ns16550ax @%¬ ½]/ª ±okayserial@20106000 !ns16550ax `%¬ ½^ª /±okaymmc@20008000 !microchip,mpfs-sd4hccdns,sd4hcx €¬ ½Xª= ë±okayKU`qƒ�Ÿ¬¹Æspi@20108000!microchip,mpfs-spix €¬ ½6ª ±okayspi@20109000!microchip,mpfs-spix �¬ ½7ª±okayspi@21000000.!microchip,mpfs-qspimicrochip,coreqspi-rtl-v2x!¬ ½Uª±okayi2c@2010a000,!microchip,mpfs-i2cmicrochip,corei2c-rtl-v7x  ¬ ½:ªt† ±okayi2c@2010b000,!microchip,mpfs-i2cmicrochip,corei2c-rtl-v7x °¬ ½=ªt† ±okaypower-monitor@10!microchip,pac1934xchannel@1xÔ'îVDDREGchannel@2xÔ'îVDDA25channel@3xÔ'îVDD25channel@4xÔ' îVDDA_REGcan@2010c000!microchip,mpfs-canx Àª%¬ ½8 ±disabledcan@2010d000!microchip,mpfs-canx Ъ%¬ ½9 ±disabledethernet@20110000!microchip,mpfs-macbcdns,macbx  ¬ ½@ABCDEôª  pclkhclk±okay sgmiiethernet@20112000!microchip,mpfs-macbcdns,macbx  ¬ ½FGHIJKôª  pclkhclk±okay sgmiiethernet-phy@9x ¸ethernet-phy@8x¸gpio@20120000!microchip,mpfs-gpiox ¬ ÑÀª!1 ±disabledgpio@20121000!microchip,mpfs-gpiox ¬ ÑÀª!1 ±disabledgpio@20122000!microchip,mpfs-gpiox  ¬ ÑÀª!1±okay€½55555555555555555555555555555555¸rtc@20124000!microchip,mpfs-rtcx @¬ ½PQª!  rtcrtcref±okayusb@20201000!microchip,mpfs-musbx ¬ ½VWª=dmamc±okayMhostmailbox@37020000!microchip,mpfs-mailbox0x7X 1Œ@7¬ ½`U±okay¸spi@37020100.!microchip,mpfs-qspimicrochip,coreqspi-rtl-v2x7¬ ½nª ±disabledflash@0!jedec,spi-nora1-sxpwm@40000000!microchip,corepwm-rtl-v4x@ð„Ÿª±okayi2c@40000200!microchip,corei2c-rtl-v7x@ª¬ ½zt† ±okaypcie@3000000000!microchip,pcie-host-1.0À?pci x0Cªcfgapb´¬ ½w`¾Ìª  fic1fic3‹0€ßêõ±okay¸interrupt-controllerÀѸcccrefclk !fixed-clockgtúð€¸aliases/soc/ethernet@20112000/soc/serial@20000000/soc/serial@20100000/soc/serial@20102000&/soc/serial@20104000./soc/serial@20106000chosen6serial1:115200n8leds !gpio-ledsled-1 BHîled1led-2 BHîled2led-3 BHîled3led-4 BHîled4memory@80000000?memoryx€@±okaymemory@1040000000?memoryx@@±okayreserved-memory‹region@BFC00000x¿À@N #address-cells#size-cellsmodelcompatibletimebase-frequencydevice_typei-cache-block-sizei-cache-setsi-cache-sizeregriscv,isariscv,isa-baseriscv,isa-extensionsclocksstatusphandle#interrupt-cellsinterrupt-controllerd-cache-block-sized-cache-setsd-cache-sized-tlb-setsd-tlb-sizei-tlb-setsi-tlb-sizemmu-typetlb-splitnext-level-cachecpu#clock-cellsclock-frequencymboxesrangescache-levelcache-unifiedinterrupt-parentinterruptsinterrupts-extendedriscv,ndevdma-channels#dma-cells#reset-cellsclock-namesreg-io-widthreg-shiftcurrent-speedmax-frequencybus-widthdisable-wpcap-sd-highspeedcap-mmc-highspeedmmc-ddr-1_8vmmc-hs200-1_8vsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104shunt-resistor-micro-ohmslabellocal-mac-addressresetsphy-modephy-handlegpio-controller#gpio-cellsinterrupt-namesdr_mode#mbox-cellsspi-max-frequencyspi-rx-bus-widthmicrochip,sync-update-mask#pwm-cellsreg-namesbus-rangeinterrupt-mapinterrupt-map-maskdma-rangesmsi-parentmsi-controllerethernet0serial0serial1serial2serial3serial4stdout-pathgpioscolorno-map