Ð þíf‘8^ð(¡^¸#itead,sonoff-ihostrockchip,rv1126&7Sonoff iHost 4Galiases=/i2c@ff3f0000B/i2c@ff400000G/i2c@ff520000L/serial@ff560000T/serial@ff410000\/serial@ff570000d/serial@ff580000l/serial@ff590000t/serial@ff5a0000|/ethernet@ffc40000†/mmc@ffc50000‹/mmc@ffc70000�/mmc@ffc60000cpuscpu@f00•cpuarm,cortex-a7¡¥psci³ºÅcpu@f01•cpuarm,cortex-a7¡¥psci³ºÅcpu@f02•cpuarm,cortex-a7¡¥psci³ºÅcpu@f03•cpuarm,cortex-a7¡¥psci³ºÅarm-pmuarm,cortex-a7-pmu0Í{|}~Øpsci arm,psci-1.0¬smctimerarm,armv7-timer0Í   ën6display_subsystemrockchip,display-subsystemûoscillator fixed-clockën6xin24mÅ*syscon@fe000000&rockchip,rv1126-grfsysconsimple-mfd¡þÅ)syscon@fe020000)rockchip,rv1126-pmugrfsysconsimple-mfd¡þÅio-domains&rockchip,rv1126-pmu-io-voltage-domain!okay( 6 D R ` n| Š ˜qos@fe860000rockchip,rv1126-qossyscon¡þ† Åqos@fe860080rockchip,rv1126-qossyscon¡þ†€ Åqos@fe860200rockchip,rv1126-qossyscon¡þ† Åqos@fe86c000rockchip,rv1126-qossyscon¡þ†À Åqos@fe8a0000rockchip,rv1126-qossyscon¡þŠ Åqos@fe8a0080rockchip,rv1126-qossyscon¡þŠ€ Åqos@fe8a0100rockchip,rv1126-qossyscon¡þŠ Åqos@fe8a0180rockchip,rv1126-qossyscon¡þŠ€ Åinterrupt-controller@feff0000 arm,gic-400¦» ¡þÿþÿ þÿ@ þÿ`  Í Åpower-management@ff3e0000&rockchip,rv1126-pmusysconsimple-mfd¡ÿ>power-controller!rockchip,rv1126-power-controllerÌÅFpower-domain@15¡8³èréuêëv àÌpower-domain@16¡³æoàÌpower-domain@10¡ P³®ÙZ¯Úš°Û[àÌi2c@ff3f0000(rockchip,rv1126-i2crockchip,rk3399-i2c¡ÿ? Íç³ ! ôi2cpclkdefault!okayë€pmic@20rockchip,rk809¡ &Í rk808-clkout1rk808-clkout2default9GS_kwƒ�› §ÅdregulatorsDCDC_REG1 ³vdd_npu_vepuÂÖèÿ ë~ð/qregulator-state-memDDCDC_REG2³vdd_armÂÖèÿ ™p/qÅregulator-state-memDDCDC_REG3³vcc_ddrÂÖèregulator-state-mem]DCDC_REG4 ³vcc3v3_sysÂÖèÿ2Z 2Z Å regulator-state-mem]u2Z DCDC_REG5 ³vcc_buck5ÂÖÿ!‘À!‘ÀÅregulator-state-mem]u!‘ÀLDO_REG1³vcc_0v8ÂÖÿ 5 5regulator-state-memDLDO_REG2 ³vcc1v8_pmuÂÖÿw@w@Å regulator-state-mem]uw@LDO_REG3 ³vcc0v8_pmuÂÖÿ 5 5regulator-state-mem]u 5LDO_REG4³vcc_1v8ÂÖÿw@w@Å regulator-state-mem]uw@LDO_REG5 ³vcc_dovddÂÖÿw@w@Åregulator-state-memDLDO_REG6 ³vcc_dvddÿO€O€regulator-state-memDLDO_REG7 ³vcc_avddÿ*¹€*¹€regulator-state-memDLDO_REG8 ³vccio_sdÂÖÿw@2Z Å regulator-state-memDLDO_REG9 ³vcc3v3_sdÂÖÿ2Z 2Z Å regulator-state-memDSWITCH_REG1³vcc_5v0SWITCH_REG2³vcc_3v3ÂÖÅKi2c@ff400000(rockchip,rv1126-i2crockchip,rk3399-i2c¡ÿ@ Íç³ " ôi2cpclkdefault!okayë€rtc@51 nxp,pcf8563¡Q&Íxin32kserial@ff410000&rockchip,rv1126-uartsnps,dw-apb-uart¡ÿA Í ën6³  ôbaudclkapb_pclk‘–txrxdefault  ª !disabledpwm@ff430000(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿC ôpwmpclk³#default!· !disabledpwm@ff430010(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿC ôpwmpclk³#default"· !disabledpwm@ff430020(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿC  ôpwmpclk³#default#· !disabledpwm@ff430030(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿC0 ôpwmpclk³#default$· !disabledpwm@ff440000(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿD ôpwmpclk³$default%· !disabledpwm@ff440010(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿD ôpwmpclk³$default&· !disabledpwm@ff440020(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿD  ôpwmpclk³$default'· !disabledpwm@ff440030(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿD0 ôpwmpclk³$default(· !disabledclock-controller@ff480000rockchip,rv1126-pmucru¡ÿHç)ÂÅclock-controller@ff490000rockchip,rv1126-cru¡ÿI³*ôxin24mç)ÂÅdma-controller@ff4e0000arm,pl330arm,primecell¡ÿN@ÍÏÚ³¡ ôapb_pclkÅi2c@ff520000(rockchip,rv1126-i2crockchip,rk3399-i2c¡ÿR ͳ" ôi2cpclkdefault+ç !disabledpwm@ff550000(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿU ôpwmpclk³',default· !disabledpwm@ff550010(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿU ôpwmpclk³'-default· !disabledpwm@ff550020(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿU  ôpwmpclk³'.default· !disabledpwm@ff550030(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿU0 ôpwmpclk³'/default· !disabledserial@ff560000&rockchip,rv1126-uartsnps,dw-apb-uart¡ÿV Í ën6³úôbaudclkapb_pclk‘–txrxdefault 012 ª!okayñbluetoothrealtek,rtl8723ds-bt 3 3  30„€default 456serial@ff570000&rockchip,rv1126-uartsnps,dw-apb-uart¡ÿW Íën6³ûôbaudclkapb_pclk‘ –txrxdefault7 ª!okayserial@ff580000&rockchip,rv1126-uartsnps,dw-apb-uart¡ÿX Íën6³üôbaudclkapb_pclk‘  –txrxdefault8 ª!okayserial@ff590000&rockchip,rv1126-uartsnps,dw-apb-uart¡ÿY Íën6³ýôbaudclkapb_pclk‘  –txrxdefault9 ª!okayserial@ff5a0000&rockchip,rv1126-uartsnps,dw-apb-uart¡ÿZ Íën6³ þôbaudclkapb_pclk‘–txrxdefault: ª !disabledadc@ff5e0000.rockchip,rv1126-saradcrockchip,rk3399-saradc¡ÿ^ Í(:³, ôsaradcapb_pclkL; Ssaradc-apb!okay_ timer@ff660000,rockchip,rv1126-timerrockchip,rk3288-timer¡ÿf  ͳ - ôpclktimeri2s@ff800000rockchip,rv1126-i2s-tdm¡ÿ€ Í.³=AÍômclk_txmclk_rxhclk‘–txrxdefault(;<=>?@ABCDLcd Stx-mrx-mç)k !disabledvop@ffb00000rockchip,rv1126-vop¡ÿ°ÿ°  Í;ôaclk_vopdclk_vophclk_vop³¯šÚ SaxiahbdclkL†‡ˆ|EƒF  !disabledportÅendpoint@0¡endpoint@1¡iommu@ffb00f00rockchip,iommu¡ÿ° Í; ôaclkiface³¯Ú‘ƒF  !disabledÅEethernet@ffc40000&rockchip,rv1126-gmacsnps,dwmac-4.20a¡ÿÄ@Í_`žmacirqeth_wake_irqç)@³~ˆˆ¿ˆ‰Tôstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_mac_speedptp_refL¾ Sstmmaceth®¿ÈGØHëI!okayþ}~ˆ|}‡%úð€:outputGJRrmii[KdefaultLMNOmdiosnps,dwmac-mdioethernet-phy@0ethernet-phy-ieee802.3-c22¡defaultPfwÃP‡' ™QÅJstmmac-axi-config¥µÅÅGrx-queues-configÏÅHqueue0tx-queues-configåÅIqueue0mmc@ffc500000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc¡ÿÅ@ ÍN ³èrstôbiuciuciu-driveciu-sampleû ëƒF!okay0?defaultRSTUMZkKw mmc@ffc600000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc¡ÿÆ@ ÍL ³älmnôbiuciuciu-driveciu-sampleû ëÂ!okay„•ÈdefaultVWXYMZ§´Áw mmc@ffc700000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc¡ÿÇ@ ÍM ³æopqôbiuciuciu-driveciu-sampleûúð€ƒF!okay„ÏÜòZ?default [\]MZýk w spi@ffc90000 rockchip,sfc¡ÿÉ@ ÍPþv%Ä´ôclk_sfchclk_sfc³vêƒF !disabledpinctrlrockchip,rv1126-pinctrlç) gpio@ff460000rockchip,gpio-bank¡ÿF Í"³&.¦»Ågpio@ff620000rockchip,gpio-bank¡ÿb Í#³(.¦»Å3gpio@ff630000rockchip,gpio-bank¡ÿc Í$³).¦»ÅQgpio@ff640000rockchip,gpio-bank¡ÿd Í%³*.¦»gpio@ff650000rockchip,gpio-bank¡ÿe Í&³ +.¦»pcfg-pull-up:Åapcfg-pull-downGÅ`pcfg-pull-noneVÅ^pcfg-pull-none-drv-level-3VcÅcpcfg-pull-up-drv-level-2:cÅ_pcfg-pull-none-drv-level-0-smtVcrÅbclk_out_ethernetemmcemmc-rstnout‡^ÅUemmc-bus8€‡________ÅRemmc-clk‡_ÅTemmc-cmd‡_ÅSfspii2c0i2c0-xfer ‡ b bÅi2c2i2c2-xfer ‡bbÅi2c3i2c3m0-xfer ‡^^Å+i2s0i2s0m0-lrck-tx‡^Å>i2s0m0-lrck-rx‡^Å?i2s0m0-mclk‡^Å=i2s0m0-sclk-rx‡^Å<i2s0m0-sclk-tx‡^Å;i2s0m0-sdi0‡^Å@i2s0m0-sdo0‡^ÅAi2s0m0-sdo1-sdi3‡^ÅBi2s0m0-sdo2-sdi2‡^ÅCi2s0m0-sdo3-sdi1‡^ÅDi2s0m1-lrck-tx‡^i2s0m1-lrck-rx‡ ^i2s0m1-mclk‡^i2s0m1-sclk-rx‡ ^i2s0m1-sclk-tx‡^i2s0m1-sdi0‡^i2s0m1-sdo0‡^i2s0m1-sdo1-sdi3‡ ^i2s0m1-sdo2-sdi2‡ ^i2s0m1-sdo3-sdi1‡ ^pwm0pwm0m0-pins‡^Å!pwm1pwm1m0-pins‡^Å"pwm2pwm2m0-pins‡^Å#pwm3pwm3m0-pins‡^Å$pwm4pwm4m0-pins‡^Å%pwm5pwm5m0-pins‡^Å&pwm6pwm6m0-pins‡ ^Å'pwm7pwm7m0-pins‡ ^Å(pwm8pwm8m0-pins‡^Å,pwm9pwm9m0-pins‡^Å-pwm10pwm10m0-pins‡^Å.pwm11pwm11m0-pins‡^Å/rgmiirgmiim1-miim ‡^^ÅLrgmiim1-rxer‡^ÅMrgmiim1-bus2`‡ ^^ ^cccÅNrgmiim1-mclkinout‡^ÅOsdmmc0sdmmc0-bus4@‡____ÅXsdmmc0-clk‡_ÅVsdmmc0-cmd‡ _ÅWsdmmc0-det‡^ÅYsdmmc1sdmmc1-bus4@‡ _ ___Å]sdmmc1-clk‡ _Å[sdmmc1-cmd‡ _Å\uart0uart0-xfer ‡aaÅ0uart0-ctsn‡^Å1uart0-rtsn‡^Å2uart1uart1m0-xfer ‡aaÅ uart2uart2m1-xfer ‡aaÅ7uart3uart3m2-xfer ‡aaÅ8uart4uart4m2-xfer ‡aaÅ9uart5uart5m0-xfer ‡aaÅ:etherneteth-phy-rst‡`ÅPbtbt-enable‡^Å4bt-wake-dev‡^Å5bt-wake-host‡^Å6pmicpmic-int-l‡ aÅwifiwifi-enable-h‡^Åechosen•serial2:1500000n8regulator-vcc5v0-sysregulator-fixed ³vcc5v0_sysÂÖÿLK@LK@Åpwrseq-sdiommc-pwrseq-simple³d ôext_clockdefaulte ™3ÅZ #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c2i2c3serial0serial1serial2serial3serial4serial5ethernet0mmc0mmc1mmc2device_typeregenable-methodclockscpu-supplyphandleinterruptsinterrupt-affinityclock-frequencyportsclock-output-names#clock-cellsstatuspmuio0-supplypmuio1-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supplyinterrupt-controller#interrupt-cells#power-domain-cellspm_qosrockchip,grfclock-namespinctrl-namespinctrl-0rockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltdmasdma-namesreg-shiftreg-io-width#pwm-cells#reset-cells#dma-cellsarm,pl330-periph-burstuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiosmax-speed#io-channel-cellsresetsreset-namesvref-supply#sound-dai-cellsiommuspower-domains#iommu-cellsinterrupt-namessnps,mixed-burstsnps,tsosnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configassigned-clocksassigned-clock-parentsassigned-clock-ratesclock_in_outphy-handlephy-modephy-supplyreset-active-lowreset-assert-usreset-deassert-usreset-gpiossnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,tx-queues-to-usefifo-depthmax-frequencybus-widthcap-mmc-highspeedmmc-hs200-1_8vnon-removablerockchip,default-sample-phasevmmc-supplyvqmmc-supplycap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr104cap-sdio-irqkeep-power-in-suspendmmc-pwrseqsd-uhs-sdr50rockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-path