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Íç³ ! ôi2cpclkdefault!okayë€pmic@20rockchip,rk809¡ &Í rk808-clkout1rk808-clkout2default9GS_kwƒ�›§ÅbregulatorsDCDC_REG1 ³vdd_npu_vepuÂÖèÿ ë~ð/qregulator-state-memDDCDC_REG2³vdd_armÂÖèÿ ™p/qÅregulator-state-memDDCDC_REG3³vcc_ddrÂÖèregulator-state-mem]DCDC_REG4 ³vcc3v3_sysÂÖèÿ2Z 2Z Åregulator-state-mem]u2Z DCDC_REG5 ³vcc_buck5ÂÖÿ!‘À!‘ÀÅregulator-state-mem]u!‘ÀLDO_REG1³vcc_0v8ÂÖÿ 5 5regulator-state-memDLDO_REG2 ³vcc1v8_pmuÂÖÿw@w@Åregulator-state-mem]uw@LDO_REG3 ³vcc0v8_pmuÂÖÿ 5 5regulator-state-mem]u 5LDO_REG4³vcc_1v8ÂÖÿw@w@Å regulator-state-mem]uw@LDO_REG5 ³vcc_dovddÂÖÿw@w@Å regulator-state-memDLDO_REG6 ³vcc_dvddÿO€O€regulator-state-memDLDO_REG7 ³vcc_avddÿ*¹€*¹€regulator-state-memDLDO_REG8 ³vccio_sdÂÖÿw@2Z Å regulator-state-memDLDO_REG9 ³vcc3v3_sdÂÖÿ2Z 2Z Å regulator-state-memDSWITCH_REG1³vcc_5v0SWITCH_REG2³vcc_3v3ÂÖÅIi2c@ff400000(rockchip,rv1126-i2crockchip,rk3399-i2c¡ÿ@ Íç³ " ôi2cpclkdefault!okayë€rtc@51 nxp,pcf8563¡Q&Íxin32kserial@ff410000&rockchip,rv1126-uartsnps,dw-apb-uart¡ÿA Í ën6³  ôbaudclkapb_pclk‘–txrxdefault ª !disabledpwm@ff430000(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿC ôpwmpclk³#default· !disabledpwm@ff430010(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿC ôpwmpclk³#default · !disabledpwm@ff430020(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿC  ôpwmpclk³#default!· !disabledpwm@ff430030(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿC0 ôpwmpclk³#default"· !disabledpwm@ff440000(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿD ôpwmpclk³$default#· !disabledpwm@ff440010(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿD ôpwmpclk³$default$· !disabledpwm@ff440020(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿD  ôpwmpclk³$default%· !disabledpwm@ff440030(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿD0 ôpwmpclk³$default&· !disabledclock-controller@ff480000rockchip,rv1126-pmucru¡ÿHç'ÂÅclock-controller@ff490000rockchip,rv1126-cru¡ÿI³(ôxin24mç'ÂÅdma-controller@ff4e0000arm,pl330arm,primecell¡ÿN@ÍÏÚ³¡ ôapb_pclkÅi2c@ff520000(rockchip,rv1126-i2crockchip,rk3399-i2c¡ÿR ͳ" ôi2cpclkdefault)ç !disabledpwm@ff550000(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿU ôpwmpclk³'*default· !disabledpwm@ff550010(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿU ôpwmpclk³'+default· !disabledpwm@ff550020(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿU  ôpwmpclk³',default· !disabledpwm@ff550030(rockchip,rv1126-pwmrockchip,rk3328-pwm¡ÿU0 ôpwmpclk³'-default· !disabledserial@ff560000&rockchip,rv1126-uartsnps,dw-apb-uart¡ÿV Í ën6³úôbaudclkapb_pclk‘–txrxdefault ./0 ª!okayñbluetoothrealtek,rtl8723ds-bt 1 1  10„€default 234serial@ff570000&rockchip,rv1126-uartsnps,dw-apb-uart¡ÿW Íën6³ûôbaudclkapb_pclk‘ –txrxdefault5 ª!okayserial@ff580000&rockchip,rv1126-uartsnps,dw-apb-uart¡ÿX Íën6³üôbaudclkapb_pclk‘  –txrxdefault6 ª!okayserial@ff590000&rockchip,rv1126-uartsnps,dw-apb-uart¡ÿY Íën6³ýôbaudclkapb_pclk‘  –txrxdefault7 ª!okayserial@ff5a0000&rockchip,rv1126-uartsnps,dw-apb-uart¡ÿZ Íën6³ þôbaudclkapb_pclk‘–txrxdefault8 ª !disabledadc@ff5e0000.rockchip,rv1126-saradcrockchip,rk3399-saradc¡ÿ^ Í(:³, ôsaradcapb_pclkL; Ssaradc-apb!okay_ timer@ff660000,rockchip,rv1126-timerrockchip,rk3288-timer¡ÿf  ͳ - ôpclktimeri2s@ff800000rockchip,rv1126-i2s-tdm¡ÿ€ Í.³=AÍômclk_txmclk_rxhclk‘–txrxdefault(9:;<=>?@ABLcd Stx-mrx-mç'k !disabledvop@ffb00000rockchip,rv1126-vop¡ÿ°ÿ°  Í;ôaclk_vopdclk_vophclk_vop³¯šÚ SaxiahbdclkL†‡ˆ|CƒD  !disabledportÅendpoint@0¡endpoint@1¡iommu@ffb00f00rockchip,iommu¡ÿ° Í; ôaclkiface³¯Ú‘ƒD  !disabledÅCethernet@ffc40000&rockchip,rv1126-gmacsnps,dwmac-4.20a¡ÿÄ@Í_`žmacirqeth_wake_irqç'@³~ˆˆ¿ˆ‰Tôstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_mac_speedptp_refL¾ Sstmmaceth®¿ÈEØFëG!okayþ}~ˆ|}‡%úð€:outputGHRrmii[IdefaultJKLMmdiosnps,dwmac-mdioethernet-phy@0ethernet-phy-ieee802.3-c22¡defaultNfwÃP‡' ™OÅHstmmac-axi-config¥µÅÅErx-queues-configÏÅFqueue0tx-queues-configåÅGqueue0mmc@ffc500000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc¡ÿÅ@ ÍN ³èrstôbiuciuciu-driveciu-sampleû ëƒD!okay0?defaultPQRSMZkIw mmc@ffc600000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc¡ÿÆ@ ÍL ³älmnôbiuciuciu-driveciu-sampleû ëÂ!okay„•ÈdefaultTUVWMZ§´Áw mmc@ffc700000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc¡ÿÇ@ ÍM ³æopqôbiuciuciu-driveciu-sampleûúð€ƒD!okay„ÏÜòX?default YZ[MZýk w spi@ffc90000 rockchip,sfc¡ÿÉ@ ÍPþv%Ä´ôclk_sfchclk_sfc³vêƒD !disabledpinctrlrockchip,rv1126-pinctrlç' gpio@ff460000rockchip,gpio-bank¡ÿF Í"³&.¦»Ågpio@ff620000rockchip,gpio-bank¡ÿb Í#³(.¦»Å1gpio@ff630000rockchip,gpio-bank¡ÿc Í$³).¦»ÅOgpio@ff640000rockchip,gpio-bank¡ÿd Í%³*.¦»gpio@ff650000rockchip,gpio-bank¡ÿe Í&³ +.¦»pcfg-pull-up:Å_pcfg-pull-downGÅ^pcfg-pull-noneVÅ\pcfg-pull-none-drv-level-3VcÅapcfg-pull-up-drv-level-2:cÅ]pcfg-pull-none-drv-level-0-smtVcrÅ`clk_out_ethernetemmcemmc-rstnout‡\ÅSemmc-bus8€‡]]]]]]]]ÅPemmc-clk‡]ÅRemmc-cmd‡]ÅQfspii2c0i2c0-xfer ‡ ` `Åi2c2i2c2-xfer ‡``Åi2c3i2c3m0-xfer ‡\\Å)i2s0i2s0m0-lrck-tx‡\Å<i2s0m0-lrck-rx‡\Å=i2s0m0-mclk‡\Å;i2s0m0-sclk-rx‡\Å:i2s0m0-sclk-tx‡\Å9i2s0m0-sdi0‡\Å>i2s0m0-sdo0‡\Å?i2s0m0-sdo1-sdi3‡\Å@i2s0m0-sdo2-sdi2‡\ÅAi2s0m0-sdo3-sdi1‡\ÅBi2s0m1-lrck-tx‡\i2s0m1-lrck-rx‡ \i2s0m1-mclk‡\i2s0m1-sclk-rx‡ \i2s0m1-sclk-tx‡\i2s0m1-sdi0‡\i2s0m1-sdo0‡\i2s0m1-sdo1-sdi3‡ \i2s0m1-sdo2-sdi2‡ \i2s0m1-sdo3-sdi1‡ \pwm0pwm0m0-pins‡\Åpwm1pwm1m0-pins‡\Å pwm2pwm2m0-pins‡\Å!pwm3pwm3m0-pins‡\Å"pwm4pwm4m0-pins‡\Å#pwm5pwm5m0-pins‡\Å$pwm6pwm6m0-pins‡ \Å%pwm7pwm7m0-pins‡ \Å&pwm8pwm8m0-pins‡\Å*pwm9pwm9m0-pins‡\Å+pwm10pwm10m0-pins‡\Å,pwm11pwm11m0-pins‡\Å-rgmiirgmiim1-miim ‡\\ÅJrgmiim1-rxer‡\ÅKrgmiim1-bus2`‡ \\ \aaaÅLrgmiim1-mclkinout‡\ÅMsdmmc0sdmmc0-bus4@‡]]]]ÅVsdmmc0-clk‡]ÅTsdmmc0-cmd‡ ]ÅUsdmmc0-det‡\ÅWsdmmc1sdmmc1-bus4@‡ ] ]]]Å[sdmmc1-clk‡ ]ÅYsdmmc1-cmd‡ ]ÅZuart0uart0-xfer ‡__Å.uart0-ctsn‡\Å/uart0-rtsn‡\Å0uart1uart1m0-xfer ‡__Åuart2uart2m1-xfer ‡__Å5uart3uart3m2-xfer ‡__Å6uart4uart4m2-xfer ‡__Å7uart5uart5m0-xfer ‡__Å8etherneteth-phy-rst‡^ÅNbtbt-enable‡\Å2bt-wake-dev‡\Å3bt-wake-host‡\Å4pmicpmic-int-l‡ _Åwifiwifi-enable-h‡\Åcchosen•serial2:1500000n8regulator-vcc5v0-sysregulator-fixed ³vcc5v0_sysÂÖÿLK@LK@Åpwrseq-sdiommc-pwrseq-simple³b ôext_clockdefaultc ™1ÅX #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c2i2c3serial0serial1serial2serial3serial4serial5ethernet0mmc0mmc1mmc2device_typeregenable-methodclockscpu-supplyphandleinterruptsinterrupt-affinityclock-frequencyportsclock-output-names#clock-cellsstatuspmuio0-supplypmuio1-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supplyinterrupt-controller#interrupt-cells#power-domain-cellspm_qosrockchip,grfclock-namespinctrl-namespinctrl-0rockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltdmasdma-namesreg-shiftreg-io-width#pwm-cells#reset-cells#dma-cellsarm,pl330-periph-burstuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiosmax-speed#io-channel-cellsresetsreset-namesvref-supply#sound-dai-cellsiommuspower-domains#iommu-cellsinterrupt-namessnps,mixed-burstsnps,tsosnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configassigned-clocksassigned-clock-parentsassigned-clock-ratesclock_in_outphy-handlephy-modephy-supplyreset-active-lowreset-assert-usreset-deassert-usreset-gpiossnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,tx-queues-to-usefifo-depthmax-frequencybus-widthcap-mmc-highspeedmmc-hs200-1_8vnon-removablerockchip,default-sample-phasevmmc-supplyvqmmc-supplycap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr104cap-sdio-irqkeep-power-in-suspendmmc-pwrseqsd-uhs-sdr50rockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-path