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idisableddma-controller@ff250000arm,pl330arm,primecell/ÿ%@ê=Hck 2apb_pclk˜thermal-zonesreserve-thermalzè�ˆž7cpu-thermalzd�ˆž7tripscpu_alert0®pºÐ*passive˜8cpu_alert1®$øºÐ*passive˜9cpu_crit®_�ºÐ *criticalcooling-mapsmap0Å80Êÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1Å90Êÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿgpu-thermalzd�ˆž7tripsgpu_alert0®pºÐ*passive˜:gpu_crit®_�ºÐ *criticalcooling-mapsmap0Å: Ê;ÿÿÿÿÿÿÿÿtsadc@ff280000rockchip,rk3288-tsadc/ÿ( ê%kHZ2tsadcapb_pclk3Ÿ ]tsadc-apbºinitdefaultsleepÈ<Ù=ã<í>siokay'>˜7ethernet@ff290000rockchip,rk3288-gmac/ÿ)êYmacirqeth_wake_irq>8k—fgc˜Ä]M2stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac3B ]stmmacethiokayi—y?�inputºdefaultÈ@ABC�D¨rgmii± Ç'B@ ÜEì0õusb@ff500000 generic-ehci/ÿP êkÂþFusb idisabledusb@ff520000 generic-ohci/ÿR ê)kÂþFusb idisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/ÿT êkÃ2otg hostþG usb2-phyiokayºdefaultÈHusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/ÿX êkÁ2otg otg,>M€€@@ þI usb2-phyiokayusb@ff5c0000 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mmio-sram/ÿp€Àÿp€smp-sram@0rockchip,rk3066-smp-sram/sram@ff720000#rockchip,rk3288-pmu-srammmio-sram/ÿrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd/ÿs˜power-controller!rockchip,rk3288-power-controller�ihy ˜hpower-domain@9/ ÈkÊÍÈÌÅÆ¾¿ÔÕÖÙÑÒchgfdehilkj$¡UVWXYZ[\]�power-domain@11/ kÏop¡^_�power-domain@12/ kÐÜ¡`�power-domain@13/ kÀ¡ab�reboot-modesyscon-reboot-mode¨”¯RBûRBÃÉRBà ÙRBÃsyscon@ff740000rockchip,rk3288-sgrfsyscon/ÿtclock-controller@ff760000rockchip,rk3288-cru/ÿvk 2xin24m>êåHiÑÝjÒÞk$ò#g¸€ׄÍeá£ðÑ€xhÀá£ðÑ€xhÀ˜syscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd/ÿw˜>edp-phyrockchip,rk3288-dp-phykh224m idisabled˜xio-domains"rockchip,rk3288-io-voltage-domainiokayc)d4BDP^nzˆusbphyrockchip,rk3288-usb-phyiokayusb-phy@320/ k]2phyclkê3… ]phy-reset˜Iusb-phy@334/4k^2phyclkê3ˆ ]phy-reset˜Fusb-phy@348/Hk_2phyclkê3‹ ]phy-reset˜Gwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt/ÿ€kp êOiokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif/ÿ‹”kTÐ 2mclkhclketx ê6ºdefaultÈf> idisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s/ÿ‰” ê5kRÎ2i2s_clki2s_hclkeetxrxºdefaultÈg¥À idisabledcrypto@ff8a0000rockchip,rk3288-crypto/ÿŠ@ ê0 kÇÍ}Á2aclkhclksclkapb_pclk3® ]crypto-rstiommu@ff900800rockchip,iommu/ÿ�@ êkÊÔ 2aclkifaceÚ idisablediommu@ff914000rockchip,iommu /ÿ‘@ÿ‘P êkÍÕ 2aclkifaceÚç idisabledrga@ff920000rockchip,rk3288-rga/ÿ’€ êkÈÖj2aclkhclksclkh 3ilm ]coreaxiahbvop@ff930000rockchip,rk3288-vop /ÿ“œÿ“ êkžÑ2aclk_vopdclk_vophclk_voph 3def ]axiahbdclkiiokayport˜ endpoint@0/j˜|endpoint@1/k˜yendpoint@2/l˜sendpoint@3/m˜viommu@ff930300rockchip,iommu/ÿ“ êkÅÑ 2aclkifaceh Úiokay˜ivop@ff940000rockchip,rk3288-vop /ÿ”œÿ” êkÆ¿Ò2aclk_vopdclk_vophclk_voph 3°±² ]axiahbdclkniokayport˜ endpoint@0/o˜}endpoint@1/p˜zendpoint@2/q˜tendpoint@3/r˜wiommu@ff940300rockchip,iommu/ÿ” êkÆÒ 2aclkifaceh Úiokay˜ndsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi/ÿ–@ êk~d 2refpclkh > idisabledportsport@0/endpoint@0/s˜lendpoint@1/t˜qport@1/lvds@ff96c000rockchip,rk3288-lvds/ÿ–À@kg 2pclk_lvdsºlcdcÈuh > idisabledportsport@0/endpoint@0/v˜mendpoint@1/w˜rport@1/dp@ff970000rockchip,rk3288-dp/ÿ—@ êbkic2dppclkþxdph 3o]dp> idisabledportsport@0/endpoint@0/y˜kendpoint@1/z˜pport@1/hdmi@ff980000rockchip,rk3288-dw-hdmi/ÿ˜0 êgkhmn2iahbisfrcech >”iokay'{portsport@0/endpoint@0/|˜jendpoint@1/}˜oport@1/video-codec@ff9a0000rockchip,rk3288-vpu/ÿšê   YvepuvdpukÐÜ 2aclkhclk~h iommu@ff9a0800rockchip,iommu/ÿš ê kÐÜ 2aclkifaceÚh ˜~iommu@ff9c0440rockchip,iommu /ÿœ@@ÿœ€@ êokÏÛ 2aclkifaceÚ idisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760/ÿ£$ê YjobmmugpukÀ:Nh iokay3€˜;opp-table-1operating-points-v2˜opp-100000000«õá²~ðopp-200000000« ë²~ðopp-300000000«á£²B@opp-400000000«ׄ²Èàopp-600000000«#ÃF²Ðqos@ffaa0000rockchip,rk3288-qossyscon/ÿª ˜aqos@ffaa0080rockchip,rk3288-qossyscon/ÿª€ ˜bqos@ffad0000rockchip,rk3288-qossyscon/ÿ­ ˜Vqos@ffad0100rockchip,rk3288-qossyscon/ÿ­ ˜Wqos@ffad0180rockchip,rk3288-qossyscon/ÿ­€ ˜Xqos@ffad0400rockchip,rk3288-qossyscon/ÿ­ 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#address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-enable-ramp-delayregulator-ramp-delayvin-supplysystem-power-controllervp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supply#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplybb-supplydvp-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-busmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highio-channelsio-channel-nameskeyup-threshold-microvoltlabellinux,codepress-threshold-microvoltgpioswakeup-sourcelinux,default-triggerstartup-delay-usenable-active-high