Ð þíhý8aL(±aSedgeble,neural-compute-module-2-ioedgeble,neural-compute-module-2rockchip,rv1126&7Edgeble Neu2 IO Boardaliases=/i2c@ff3f0000B/i2c@ff400000G/i2c@ff520000L/serial@ff560000T/serial@ff410000\/serial@ff570000d/serial@ff580000l/serial@ff590000t/serial@ff5a0000|/mmc@ffc50000cpuscpu@f00�cpuarm,cortex-a7�‘psciŸ¦±cpu@f01�cpuarm,cortex-a7�‘psciŸ±cpu@f02�cpuarm,cortex-a7�‘psciŸ±cpu@f03�cpuarm,cortex-a7�‘psciŸ±arm-pmuarm,cortex-a7-pmu0¹{|}~Äpsci arm,psci-1.0˜smctimerarm,armv7-timer0¹   ×n6display_subsystemrockchip,display-subsystemçoscillator fixed-clock×n6íxin24m±*syscon@fe000000&rockchip,rv1126-grfsysconsimple-mfd�þ±)syscon@fe020000)rockchip,rv1126-pmugrfsysconsimple-mfd�þ±io-domains&rockchip,rv1126-pmu-io-voltage-domain okay " 0 > L Zh v „qos@fe860000rockchip,rv1126-qossyscon�þ† ±qos@fe860080rockchip,rv1126-qossyscon�þ†€ ±qos@fe860200rockchip,rv1126-qossyscon�þ† ±qos@fe86c000rockchip,rv1126-qossyscon�þ†À ±qos@fe8a0000rockchip,rv1126-qossyscon�þŠ ±qos@fe8a0080rockchip,rv1126-qossyscon�þŠ€ ±qos@fe8a0100rockchip,rv1126-qossyscon�þŠ ±qos@fe8a0180rockchip,rv1126-qossyscon�þŠ€ ±interrupt-controller@feff0000 arm,gic-400’§ �þÿþÿ þÿ@ þÿ`  ¹ ±power-management@ff3e0000&rockchip,rv1126-pmusysconsimple-mfd�ÿ>power-controller!rockchip,rv1126-power-controller¸±Epower-domain@15�8Ÿèréuêëv ̸power-domain@16�Ÿæo̸power-domain@10� PŸ®ÙZ¯Úš°Û[̸i2c@ff3f0000(rockchip,rv1126-i2crockchip,rk3399-i2c�ÿ? ¹ÓŸ ! ài2cpclkìdefaultú okay×€pmic@20rockchip,rk809� &¹ írk808-clkout1rk808-clkout2ìdefaultú%3?KWco{‡ “±3regulatorsDCDC_REG1 Ÿvdd_npu_vepu®ÂÔë ë~ðqregulator-state-mem0DCDC_REG2Ÿvdd_arm®ÂÔë ™pq±regulator-state-mem0DCDC_REG3Ÿvcc_ddr®ÂÔregulator-state-memIDCDC_REG4 Ÿvcc3v3_sys®ÂÔë2Z 2Z ± regulator-state-memIa2Z DCDC_REG5 Ÿvcc_buck5®Âë!‘À!‘À±regulator-state-memIa!‘ÀLDO_REG1Ÿvcc_0v8®Âë 5 5regulator-state-mem0LDO_REG2 Ÿvcc1v8_pmu®Âëw@w@± regulator-state-memIaw@LDO_REG3 Ÿvcc0v8_pmu®Âë 5 5regulator-state-memIa 5LDO_REG4Ÿvcc_1v8®Âëw@w@± regulator-state-memIaw@LDO_REG5 Ÿvcc_dovddÂëw@w@±regulator-state-mem0LDO_REG6 Ÿvcc_dvddëO€O€regulator-state-mem0LDO_REG7 Ÿvcc_avddë*¹€*¹€regulator-state-mem0LDO_REG8 Ÿvccio_sd®Âëw@2Z ± regulator-state-mem0LDO_REG9 Ÿvcc3v3_sd®Âë2Z 2Z regulator-state-mem0SWITCH_REG1Ÿvcc_5v0SWITCH_REG2Ÿvcc_3v3®Â±Ji2c@ff400000(rockchip,rv1126-i2crockchip,rk3399-i2c�ÿ@ ¹ÓŸ " ài2cpclkìdefaultú  disabledserial@ff410000&rockchip,rv1126-uartsnps,dw-apb-uart�ÿA ¹ ×n6Ÿ  àbaudclkapb_pclk}‚txrxìdefaultú Œ–  disabledpwm@ff430000(rockchip,rv1126-pwmrockchip,rk3328-pwm�ÿC àpwmpclkŸ#ìdefaultú!£  disabledpwm@ff430010(rockchip,rv1126-pwmrockchip,rk3328-pwm�ÿC àpwmpclkŸ#ìdefaultú"£  disabledpwm@ff430020(rockchip,rv1126-pwmrockchip,rk3328-pwm�ÿC  àpwmpclkŸ#ìdefaultú#£  disabledpwm@ff430030(rockchip,rv1126-pwmrockchip,rk3328-pwm�ÿC0 àpwmpclkŸ#ìdefaultú$£  disabledpwm@ff440000(rockchip,rv1126-pwmrockchip,rk3328-pwm�ÿD àpwmpclkŸ$ìdefaultú%£  disabledpwm@ff440010(rockchip,rv1126-pwmrockchip,rk3328-pwm�ÿD àpwmpclkŸ$ìdefaultú&£  disabledpwm@ff440020(rockchip,rv1126-pwmrockchip,rk3328-pwm�ÿD  àpwmpclkŸ$ìdefaultú'£  disabledpwm@ff440030(rockchip,rv1126-pwmrockchip,rk3328-pwm�ÿD0 àpwmpclkŸ$ìdefaultú(£  disabledclock-controller@ff480000rockchip,rv1126-pmucru�ÿHÓ)®±clock-controller@ff490000rockchip,rv1126-cru�ÿIŸ*àxin24mÓ)®±dma-controller@ff4e0000arm,pl330arm,primecell�ÿN@¹»ÆŸ¡ àapb_pclk±i2c@ff520000(rockchip,rv1126-i2crockchip,rk3399-i2c�ÿR ¹Ÿ" ài2cpclkìdefaultú+Ó  disabledpwm@ff550000(rockchip,rv1126-pwmrockchip,rk3328-pwm�ÿU àpwmpclkŸ'ú,ìdefault£  disabledpwm@ff550010(rockchip,rv1126-pwmrockchip,rk3328-pwm�ÿU àpwmpclkŸ'ú-ìdefault£  disabledpwm@ff550020(rockchip,rv1126-pwmrockchip,rk3328-pwm�ÿU  àpwmpclkŸ'ú.ìdefault£  disabledpwm@ff550030(rockchip,rv1126-pwmrockchip,rk3328-pwm�ÿU0 àpwmpclkŸ'ú/ìdefault£ okayserial@ff560000&rockchip,rv1126-uartsnps,dw-apb-uart�ÿV ¹ ×n6Ÿúàbaudclkapb_pclk}‚txrxìdefault ú012Œ– okaybluetoothqcom,qca9377-btŸ3 Ý4ê„€ìdefaultú5ô  serial@ff570000&rockchip,rv1126-uartsnps,dw-apb-uart�ÿW ¹×n6Ÿûàbaudclkapb_pclk} ‚txrxìdefaultú6Œ– okayserial@ff580000&rockchip,rv1126-uartsnps,dw-apb-uart�ÿX ¹×n6Ÿüàbaudclkapb_pclk}  ‚txrxìdefaultú7Œ–  disabledserial@ff590000&rockchip,rv1126-uartsnps,dw-apb-uart�ÿY ¹×n6Ÿýàbaudclkapb_pclk}  ‚txrxìdefaultú8Œ–  disabledserial@ff5a0000&rockchip,rv1126-uartsnps,dw-apb-uart�ÿZ ¹×n6Ÿ þàbaudclkapb_pclk}‚txrxìdefaultú9Œ–  disabledadc@ff5e0000.rockchip,rv1126-saradcrockchip,rk3399-saradc�ÿ^ ¹(Ÿ, àsaradcapb_pclk ; 'saradc-apb okay3 timer@ff660000,rockchip,rv1126-timerrockchip,rk3288-timer�ÿf  ¹Ÿ - àpclktimeri2s@ff800000rockchip,rv1126-i2s-tdm�ÿ€ ¹.Ÿ=AÍàmclk_txmclk_rxhclk}‚txrxìdefault(ú:;<=>?@ABC cd 'tx-mrx-mÓ)?  disabledvop@ffb00000rockchip,rv1126-vop�ÿ°ÿ°  ¹;àaclk_vopdclk_vophclk_vopŸ¯šÚ 'axiahbdclk †‡ˆPDWE   disabledport±endpoint@0�endpoint@1�iommu@ffb00f00rockchip,iommu�ÿ° ¹; àaclkifaceŸ¯ÚeWE   disabled±Dethernet@ffc40000&rockchip,rv1126-gmacsnps,dwmac-4.20a�ÿÄ@¹_`rmacirqeth_wake_irqÓ)@Ÿ~ˆˆ¿ˆ‰Tàstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_mac_speedptp_ref ¾ 'stmmaceth‚“œF¬G¿H okayÒ~ˆŠâ}ƒ ùsY@}x@inputI&rgmii/JìdefaultúKLMN:*Cmdiosnps,dwmac-mdioethernet-phy@0ethernet-phy-id001c.c916�ìdefaultúOLN \†  n±Istmmac-axi-configzŠš±Frx-queues-config¤±Gqueue0tx-queues-configº±Hqueue0mmc@ffc500000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc�ÿÅ@ ¹N Ÿèrstàbiuciuciu-driveciu-sampleÐÛ ëÂWE okayéóìdefault úPQRZJ+ mmc@ffc600000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc�ÿÆ@ ¹L Ÿälmnàbiuciuciu-driveciu-sampleÐÛ ë okayé8J[ÈìdefaultúSTUVZmz‡+ mmc@ffc700000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc�ÿÇ@ ¹M Ÿæopqàbiuciuciu-driveciu-sampleÐÛõáWE okayéJ•¢¸Wóìdefault úXYZZ‡ + spi@ffc90000 rockchip,sfc�ÿÉ@ ¹PÒvùÄ´àclk_sfchclk_sfcŸvêWE okayìdefaultú[flash@0jedec,spi-nor�Ãúð€Õæpinctrlrockchip,rv1126-pinctrlÓ)÷gpio@ff460000rockchip,gpio-bank�ÿF ¹"Ÿ& ’§±gpio@ff620000rockchip,gpio-bank�ÿb ¹#Ÿ( ’§±dgpio@ff630000rockchip,gpio-bank�ÿc ¹$Ÿ) ’§gpio@ff640000rockchip,gpio-bank�ÿd ¹%Ÿ* ’§±4gpio@ff650000rockchip,gpio-bank�ÿe ¹&Ÿ + ’§pcfg-pull-up'±_pcfg-pull-down4±^pcfg-pull-noneC±\pcfg-pull-none-drv-level-3CP±apcfg-pull-up-drv-level-2'P±]pcfg-pull-none-drv-level-0-smtCP_±`clk_out_ethernetclk-out-ethernetm1-pinst\±Nemmcemmc-bus8€t]]]]]]]]±Pemmc-clkt]±Remmc-cmdt]±Qfspifspi-pins`t^_____±[i2c0i2c0-xfer t ` `±i2c2i2c2-xfer t``±i2c3i2c3m0-xfer t\\±+i2s0i2s0m0-lrck-txt\±=i2s0m0-lrck-rxt\±>i2s0m0-mclkt\±<i2s0m0-sclk-rxt\±;i2s0m0-sclk-txt\±:i2s0m0-sdi0t\±?i2s0m0-sdo0t\±@i2s0m0-sdo1-sdi3t\±Ai2s0m0-sdo2-sdi2t\±Bi2s0m0-sdo3-sdi1t\±Ci2s0m1-lrck-txt\i2s0m1-lrck-rxt \i2s0m1-mclkt\i2s0m1-sclk-rxt \i2s0m1-sclk-txt\i2s0m1-sdi0t\i2s0m1-sdo0t\i2s0m1-sdo1-sdi3t \i2s0m1-sdo2-sdi2t \i2s0m1-sdo3-sdi1t \pwm0pwm0m0-pinst\±!pwm1pwm1m0-pinst\±"pwm2pwm2m0-pinst\±#pwm3pwm3m0-pinst\±$pwm4pwm4m0-pinst\±%pwm5pwm5m0-pinst\±&pwm6pwm6m0-pinst \±'pwm7pwm7m0-pinst \±(pwm8pwm8m0-pinst\±,pwm9pwm9m0-pinst\±-pwm10pwm10m0-pinst\±.pwm11pwm11m0-pinst\±/rgmiirgmiim1-miim t\\±Krgmiim1-bus2`t \\ \aaa±Lrgmiim1-bus4`t\\\aaa±Msdmmc0sdmmc0-bus4@t]]]]±Usdmmc0-clkt]±Ssdmmc0-cmdt ]±Tsdmmc0-dett\±Vsdmmc1sdmmc1-bus4@t ] ]]]±Zsdmmc1-clkt ]±Xsdmmc1-cmdt ]±Yuart0uart0-xfer t__±0uart0-ctsnt\±1uart0-rtsnt\±2uart1uart1m0-xfer t__± uart2uart2m1-xfer t__±6uart3uart3m0-xfer t__±7uart4uart4m0-xfer t__±8uart5uart5m0-xfer t__±9btbt-enablet\±5flashflash-vol-selt \±bpmicpmic-int-lt _±wifiwifi-enable-ht\±cetherneteth-phy-rstt^±Ovccio-flash-regulatorregulator-fixed‚ • ìdefaultúb Ÿvccio_flash®Âëw@w@šJ± pwrseq-sdiommc-pwrseq-simpleŸ3 àext_clockìdefaultúc nd±Wchosen¥serial2:1500000n8vcc12v-dcin-regulatorregulator-fixed Ÿvcc12v_dcin®Âë··±evcc5v0-sys-regulatorregulator-fixed Ÿvcc5v0_sys®ÂëLK@LK@še±v3v3-sys-regulatorregulator-fixed Ÿv3v3_sys®Âë2Z 2Z š #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c2i2c3serial0serial1serial2serial3serial4serial5mmc0device_typeregenable-methodclockscpu-supplyphandleinterruptsinterrupt-affinityclock-frequencyportsclock-output-names#clock-cellsstatuspmuio0-supplypmuio1-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supplyinterrupt-controller#interrupt-cells#power-domain-cellspm_qosrockchip,grfclock-namespinctrl-namespinctrl-0rockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltdmasdma-namesreg-shiftreg-io-width#pwm-cells#reset-cells#dma-cellsarm,pl330-periph-burstenable-gpiosmax-speedvddxo-supplyvddio-supply#io-channel-cellsresetsreset-namesvref-supply#sound-dai-cellsiommuspower-domains#iommu-cellsinterrupt-namessnps,mixed-burstsnps,tsosnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configassigned-clocksassigned-clock-parentsassigned-clock-ratesclock_in_outphy-handlephy-modephy-supplytx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiossnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,tx-queues-to-usefifo-depthmax-frequencybus-widthnon-removablerockchip,default-sample-phasevmmc-supplyvqmmc-supplycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr104cap-sdio-irqkeep-power-in-suspendmmc-pwrseqspi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsenable-active-highgpiovin-supplystdout-path