Ð þí·ò8¬d( ެ,google,veyron-fievel-rev8google,veyron-fievel-rev7google,veyron-fievel-rev6google,veyron-fievel-rev5google,veyron-fievel-rev4google,veyron-fievel-rev3google,veyron-fievel-rev2google,veyron-fievel-rev1google,veyron-fievel-rev0google,veyron-fievelgoogle,veyronrockchip,rk3288&7Google Fievelaliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000‚/i2c@ff140000‡/i2c@ff660000Œ/i2c@ff150000‘/i2c@ff160000–/i2c@ff170000›/mmc@ff0f0000¡/mmc@ff0c0000§/mmc@ff0d0000­/mmc@ff0e0000³/serial@ff180000»/serial@ff190000Ã/serial@ff690000Ë/serial@ff1b0000Ó/serial@ff1c0000Û/spi@ff110000à/spi@ff120000å/spi@ff130000ê/mmc@ff0f0000arm-pmuarm,cortex-a12-pmu0ï—˜™šúcpus rockchip,rk3066-smpcpu@500(cpuarm,cortex-a1248?Sbœ@pwr‘ �cpu@501(cpuarm,cortex-a1248?Sbœ@pwr�cpu@502(cpuarm,cortex-a1248?Sbœ@pwr�cpu@503(cpuarm,cortex-a1248?Sbœ@pwr�opp-table-0operating-points-v2¥�opp-126000000°‚›€· » opp-216000000° ßæ· » opp-408000000°Q–· » opp-600000000°#ÃF· » opp-696000000°)|·~ðopp-816000000°0£,·B@opp-1008000000°<Ü·�opp-1200000000°G†Œ·Èàopp-1416000000°Tfr·O€opp-1512000000°ZJ·Ðopp-1608000000°_Ø"·Ö opp-1704000000°e�ú·™popp-1800000000°kIÒ·\Àreserved-memoryÅdma-unusable@fe0000004þoscillator fixed-clockÌn6Üxin24mï� timerarm,armv7-timerü0ï   Ìn6 timer@ff810000rockchip,rk3288-timer4ÿ�  ïH pa  7pclktimerdisplay-subsystemrockchip,display-subsystemC mmc@ff0c0000rockchip,rk3288-dw-mshcIðÑ€ pÈDrv7biuciuciu-driveciu-sampleW ï 4ÿ @8€breset ndisabledmmc@ff0d0000rockchip,rk3288-dw-mshcIðÑ€ pÉEsw7biuciuciu-driveciu-sampleW ï!4ÿ @8�bresetnokayu��³ ¾Ìdefault Úäñþ %btmrvl@2marvell,sd8897-bt4&ï2 ÌdefaultÚmmc@ff0e0000rockchip,rk3288-dw-mshcIðÑ€ pÊFtx7biuciuciu-driveciu-sampleW ï"4ÿ@8‚breset ndisabledmmc@ff0f0000rockchip,rk3288-dw-mshcIðÑ€ pËGuy7biuciuciu-driveciu-sampleW ï#4ÿ@8ƒbresetnokayuEWžu€³¾Ìdefault Úsaradc@ff100000rockchip,saradc4ÿ ï$�pI[7saradcapb_pclk8W bsaradc-apb ndisabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spipAR7spiclkapb_pclk¡  ¦txrx ï,ÌdefaultÚ4ÿ ndisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spipBS7spiclkapb_pclk¡ ¦txrx ï-ÌdefaultÚ !4ÿ ndisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spipCT7spiclkapb_pclk¡¦txrx ï.ÌdefaultÚ"#$%4ÿnokay° flash@0jedec,spi-norÃúð€4i2c@ff140000rockchip,rk3288-i2c4ÿ ï>7i2cpMÌdefaultÚ&nokayÌ€Õ2ídtpm@20infineon,slb9645tt4 i2c@ff150000rockchip,rk3288-i2c4ÿ ï?7i2cpOÌdefaultÚ' ndisabledi2c@ff160000rockchip,rk3288-i2c4ÿ ï@7i2cpPÌdefaultÚ(nokayÌ€Õ2í,ts3a227e@3b ti,ts3a227e4;&)ïÌdefaultÚ*�ži2c@ff170000rockchip,rk3288-i2c4ÿ ïA7i2cpQÌdefaultÚ+ ndisabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart4ÿ ï7'1pMU7baudclkapb_pclk¡¦txrxÌdefault Ú,-.nokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart4ÿ ï8'1pNV7baudclkapb_pclk¡¦txrxÌdefaultÚ/nokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart4ÿi ï9'1pOW7baudclkapb_pclkÌdefaultÚ0nokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart4ÿ ï:'1pPX7baudclkapb_pclk¡¦txrxÌdefaultÚ1 ndisabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart4ÿ ï;'1pQY7baudclkapb_pclk¡  ¦txrxÌdefaultÚ2 ndisableddma-controller@ff250000arm,pl330arm,primecell4ÿ%@ï>Idp 7apb_pclk�thermal-zonesreserve-thermal{葈Ÿ3cpu-thermal{d‘ˆŸ3tripscpu_alert0¯p»Ð/passive�4cpu_alert1¯$ø»Ð/passive�5cpu_crit¯† »Ð /criticalcooling-mapsmap0Æ40Ëÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1Æ50Ëÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿgpu-thermal{d‘ˆŸ3tripsgpu_alert0¯4»Ð/passive�6gpu_crit¯† »Ð /criticalcooling-mapsmap0Æ6 Ë7ÿÿÿÿÿÿÿÿtsadc@ff280000rockchip,rk3288-tsadc4ÿ( ï%pHZ7tsadcapb_pclk8Ÿ btsadc-apbÌinitdefaultsleepÚ8Ú9ä8î:èHnokay(?�3ethernet@ff290000rockchip,rk3288-gmac4ÿ)ïZmacirqeth_wake_irq:8p—fgc˜Ä]M7stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac8B bstmmacethnokayj—z;‘inputž<©rgmii²=ÌdefaultÚ>?@A½Æ0 Ïß õ'u0 mdio0snps,dwmac-mdioethernet-phy@14�<usb@ff500000 generic-ehci4ÿP ïpÂBusbnokay'usb@ff520000 generic-ohci4ÿR ï)pÂBusb ndisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc24ÿT ïpÃ7otg=hostC usb2-phyEnokay\usb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc24ÿX ïpÁ7otg=hosts…”€€@@ D usb2-phynokayjzzD\usb@ff5c0000 generic-ehci4ÿ\ ïpÄ ndisableddma-controller@ff600000arm,pl330arm,primecell4ÿ`@ï>IdpÁ 7apb_pclk ndisabledi2c@ff650000rockchip,rk3288-i2c4ÿe ï<7i2cpLÌdefaultÚEnokayÌ€Õ2ídpmic@1brockchip,rk8084Üxin32kwifibt_32kin&)ïÌdefault ÚFGH£ ïÄÐÜèô %I2?J JIK�”regulatorsDCDC_REG1Vvdd_armey‹ q°£ »q� regulator-state-memÐDCDC_REG2Vvdd_gpuey‹ 5£Ð»q�regulator-state-memÐDCDC_REG3 Vvcc135_ddreyregulator-state-meméDCDC_REG4Vvcc_18ey‹w@£w@�regulator-state-meméw@LDO_REG3Vvdd_10ey‹B@£B@regulator-state-meméB@LDO_REG7 Vvdd10_lcdey‹B@£B@regulator-state-memÐSWITCH_REG1 Vvcc33_lcdey�aregulator-state-memÐLDO_REG6 Vvcc18_codecey‹w@£w@�bregulator-state-memÐLDO_REG2ey‹w@£w@ Vvdd18_lcdtregulator-state-memÐLDO_REG8ey‹2Z £2Z  Vvcc33_ccdregulator-state-memÐSWITCH_REG2 Vvcc33_lan�=i2c@ff660000rockchip,rk3288-i2c4ÿf ï=7i2cpNÌdefaultÚLnokay̆ Õ2í max98090@10maxim,max980904&Mï7mclkpqÌdefaultÚN��pwm@ff680000rockchip,rk3288-pwm4ÿhÌdefaultÚOp_ ndisabledpwm@ff680010rockchip,rk3288-pwm4ÿhÌdefaultÚPp_nokay�™pwm@ff680020rockchip,rk3288-pwm4ÿh ÌdefaultÚQp_ ndisabledpwm@ff680030rockchip,rk3288-pwm4ÿh0ÌdefaultÚRp_ ndisabledsram@ff700000 mmio-sram4ÿp€Åÿp€smp-sram@0rockchip,rk3066-smp-sram4sram@ff720000#rockchip,rk3288-pmu-srammmio-sram4ÿrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd4ÿs�power-controller!rockchip,rk3288-power-controller(jhz �fpower-domain@94 ÈpÊÍÈÌÅÆ¾¿ÔÕÖÙÑÒchgfdehilkj$<STUVWXYZ[(power-domain@114 pÏop<\](power-domain@124 pÐÜ<^(power-domain@134 pÀ<_`(reboot-modesyscon-reboot-modeC”JRBÃVRBÃdRBà tRBÃsyscon@ff740000rockchip,rk3288-sgrfsyscon4ÿtclock-controller@ff760000rockchip,rk3288-cru4ÿvp 7xin24m:ï€HjÑÝjÒÞk$�#g¸€ׄÍeá£ðÑ€xhÀá£ðÑ€xhÀ�syscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd4ÿw�:edp-phyrockchip,rk3288-dp-phyph724m¢ ndisabled�vio-domains"rockchip,rk3288-io-voltage-domainnokay­I·ÂÐIàIîaú busbphyrockchip,rk3288-usb-phynokayusb-phy@320¢4 p]7phyclkï8… bphy-reset�Dusb-phy@334¢44p^7phyclkï8ˆ bphy-reset�Busb-phy@348¢4Hp_7phyclkï8‹ bphy-reset�Cwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt4ÿ€pp ïOnokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif4ÿ‹ pTÐ 7mclkhclk¡c¦tx ï6ÌdefaultÚd: ndisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s4ÿ‰  ï5pRÎ7i2s_clki2s_hclk¡cc¦txrxÌdefaultÚe $ ?nokay�œcrypto@ff8a0000rockchip,rk3288-crypto4ÿŠ@ ï0 pÇÍ}Á7aclkhclksclkapb_pclk8® bcrypto-rstiommu@ff900800rockchip,iommu4ÿ�@ ïpÊÔ 7aclkiface Y ndisablediommu@ff914000rockchip,iommu 4ÿ‘@ÿ‘P ïpÍÕ 7aclkiface Y f ndisabledrga@ff920000rockchip,rk3288-rga4ÿ’€ ïpÈÖj7aclkhclksclk �f 8ilm bcoreaxiahbvop@ff930000rockchip,rk3288-vop 4ÿ“œÿ“ ïpžÑ7aclk_vopdclk_vophclk_vop �f 8def baxiahbdclk �gnokayport� endpoint@04 –h�{endpoint@14 –i�wendpoint@24 –j�qendpoint@34 –k�tiommu@ff930300rockchip,iommu4ÿ“ ïpÅÑ 7aclkiface �f  Ynokay�gvop@ff940000rockchip,rk3288-vop 4ÿ”œÿ” ïpÆ¿Ò7aclk_vopdclk_vophclk_vop �f 8°±² baxiahbdclk �l ndisabledport� endpoint@04 –m�|endpoint@14 –n�xendpoint@24 –o�rendpoint@34 –p�uiommu@ff940300rockchip,iommu4ÿ” ïpÆÒ 7aclkiface �f  Y ndisabled�ldsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi4ÿ–@ ïp~d 7refpclk �f : ndisabledportsport@04endpoint@04 –q�jendpoint@14 –r�oport@14lvds@ff96c000rockchip,rk3288-lvds4ÿ–À@pg 7pclk_lvdsÌlcdcÚs �f : ndisabledportsport@04endpoint@04 –t�kendpoint@14 –u�pport@14dp@ff970000rockchip,rk3288-dp4ÿ—@ ïbpic7dppclkvdp �f 8obdp: ndisabledportsport@04endpoint@04 –w�iendpoint@14 –x�nport@14hdmi@ff980000rockchip,rk3288-dw-hdmi4ÿ˜1 ïgphmn7iahbisfrcec �f : nokayÌdefaultunwedgeÚyÚz�Ÿportsport@04endpoint@04 –{�hendpoint@14 –|�mport@14video-codec@ff9a0000rockchip,rk3288-vpu4ÿšï   ZvepuvdpupÐÜ 7aclkhclk �} �f iommu@ff9a0800rockchip,iommu4ÿš ï pÐÜ 7aclkiface Y �f �}iommu@ff9c0440rockchip,iommu 4ÿœ@@ÿœ€@ ïopÏÛ 7aclkiface Y ndisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t7604ÿ£$ï ZjobmmugpupÀ?~S �f nokay ¦�7opp-table-1operating-points-v2�~opp-100000000°õá·~ðopp-200000000° ë·~ðopp-300000000°á£·B@opp-400000000°ׄ·Èàopp-600000000°#ÃF·Ðqos@ffaa0000rockchip,rk3288-qossyscon4ÿª �_qos@ffaa0080rockchip,rk3288-qossyscon4ÿª€ �`qos@ffad0000rockchip,rk3288-qossyscon4ÿ­ �Tqos@ffad0100rockchip,rk3288-qossyscon4ÿ­ �Uqos@ffad0180rockchip,rk3288-qossyscon4ÿ­€ �Vqos@ffad0400rockchip,rk3288-qossyscon4ÿ­ �Wqos@ffad0480rockchip,rk3288-qossyscon4ÿ­€ �Xqos@ffad0500rockchip,rk3288-qossyscon4ÿ­ �Sqos@ffad0800rockchip,rk3288-qossyscon4ÿ­ �Yqos@ffad0880rockchip,rk3288-qossyscon4ÿ­€ �Zqos@ffad0900rockchip,rk3288-qossyscon4ÿ­ �[qos@ffae0000rockchip,rk3288-qossyscon4ÿ® �^qos@ffaf0000rockchip,rk3288-qossyscon4ÿ¯ �\qos@ffaf0080rockchip,rk3288-qossyscon4ÿ¯€ �]dma-controller@ffb20000arm,pl330arm,primecell4ÿ²@ï>IdpÁ 7apb_pclk�cefuse@ffb40000rockchip,rk3288-efuse4ÿ´ pq 7pclk_efusecpu-id@74cpu_leakage@174interrupt-controller@ffc01000 arm,gic-400 ² Ç@4ÿÀÿÀ ÿÀ@ ÿÀ`  ï �pinctrlrockchip,rk3288-pinctrl:ÅÌdefaultsleepÚ€�‚ƒ„…†Ú€�‚ƒ„‡ˆgpio@ff750000rockchip,gpio-bank4ÿu ïQp@ Ø è ² Çá ôPMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LHUB_USB1_nFALUTPHY_PMEBPHY_INTRECOVERY_SW_LOTP_OUTUSB_OTG_POWER_ENAP_WARM_RESET_HUSB_OTG_nFALUTI2C0_SDA_PMICI2C0_SCL_PMICDEVMODE_LUSB_INT�)gpio@ff780000rockchip,gpio-bank4ÿx ïRpA Ø è ² Çgpio@ff790000rockchip,gpio-bank4ÿy ïSpB Ø è ² Çi ôCONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_LBL_PWR_ENTOUCH_INTTOUCH_RSTI2C3_SCL_TPI2C3_SDA_TP�“gpio@ff7a0000rockchip,gpio-bank4ÿz ïTpC Ø è ² ÇÛ ôFLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7VCC5V_GOOD_HFLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOPHY_TXD2PHY_TXD3MAC_RXD2MAC_RXD3PHY_TXD0PHY_TXD1MAC_RXD0MAC_RXD1gpio@ff7b0000rockchip,gpio-bank4ÿ{ ïUpD Ø è ² Çþ ôMAC_MDCMAC_RXDVMAC_RXERMAC_CLKPHY_TXENMAC_MDIOMAC_RXCLKPHY_RSTPHY_TXCLKUART0_RXDUART0_TXDUART0_CTS_LUART0_RTS_LSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKE�gpio@ff7c0000rockchip,gpio-bank4ÿ| ïVpE Ø è ² Ç… ôUSB_OTG_CTL1HUB_USB2_CTL1HUB_USB2_PWR_ENHUB_USB_ILIM_SELUSB_OTG_STATUS_LHUB_USB1_CTL1HUB_USB1_PWR_ENVCC50_HDMI_EN�—gpio@ff7d0000rockchip,gpio-bank4ÿ} ïWpF Ø è ² Ç’ ôI2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETHUB_USB2_nFALUTUSB_OTG_ILIM_SEL�Mgpio@ff7e0000rockchip,gpio-bank4ÿ~ ïXpG Ø è ² ǽ ôLCD_BL_PWMPWM_LOGBL_ENPWR_LED1TPM_INT_HSPK_ONAP_FLASH_WP_LCPU_NMIDVSOKEDP_HPDDVS1LCD_ENDVS2HDMI_CECI2C4_SDAI2C4_SCLI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXD�Jgpio@ff7f0000rockchip,gpio-bank4ÿ ïYpH Ø è ² Ç^ ôRAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 ‰hdmi-cec-c7 ‰hdmi-ddc ‰‰�yhdmi-ddc-unwedge Љ�zvcc50-hdmi-en ‰�˜pcfg-output-low �Špcfg-pull-up �‹pcfg-pull-down *�Œpcfg-pull-none 9�‰pcfg-pull-none-12ma 9 F ��suspendglobal-pwroff ‰�‚ddrio-pwroff ‰��ddr0-retention ‹�€ddr1-retention ‹edpedp-hpd  Œi2c0i2c0-xfer ‰‰�Ei2c1i2c1-xfer ‰‰�&i2c2i2c2-xfer  ‰ ‰�Li2c3i2c3-xfer ‰‰�'i2c4i2c4-xfer ‰‰�(i2c5i2c5-xfer ‰‰�+i2s0i2s0-bus` ‰‰‰‰‰‰�elcdclcdc-ctl@ ‰‰‰‰�ssdmmcsdmmc-clk ‰sdmmc-cmd ‹sdmmc-cd ‹sdmmc-bus1 ‹sdmmc-bus4@ ‹‹‹‹sdio0sdio0-bus1 ‹sdio0-bus4@ �����sdio0-cmd ��sdio0-clk ��sdio0-cd ‹sdio0-wp ‹sdio0-pwr ‹sdio0-bkpwr ‹sdio0-int ‹wifienable-h ‰�•bt-enable-l ‰bt-host-wake Œbt-host-wake-l ‰�bt-dev-wake-sleep Š�‡bt-dev-wake-awake Ž�…bt-dev-wake ‰sdio1sdio1-bus1 ‹sdio1-bus4@ ‹‹‹‹sdio1-cd ‹sdio1-wp ‹sdio1-bkpwr ‹sdio1-int ‹sdio1-cmd ‹sdio1-clk ‰sdio1-pwr  ‹emmcemmc-clk ��emmc-cmd ��emmc-pwr  ‹emmc-bus1 ‹emmc-bus4@ ‹‹‹‹emmc-bus8€ ���������emmc-reset  ‰�’spi0spi0-clk  ‹�spi0-cs0  ‹�spi0-tx ‹�spi0-rx ‹�spi0-cs1 ‹spi1spi1-clk  ‹�spi1-cs0  ‹�!spi1-rx ‹� spi1-tx ‹�spi2spi2-cs1 ‹spi2-clk ‹�"spi2-cs0 ‹�%spi2-rx ‹�$spi2-tx  ‹�#uart0uart0-xfer ‹‰�,uart0-cts ‹�-uart0-rts ‰�.uart1uart1-xfer ‹ ‰�/uart1-cts  ‹uart1-rts  ‰uart2uart2-xfer ‹‰�0uart3uart3-xfer ‹‰�1uart3-cts  ‹uart3-rts  ‰uart4uart4-xfer ‹‰�2uart4-cts  ‹uart4-rts  ‰tsadcotp-pin  ‰�8otp-out  ‰�9pwm0pwm0-pin ‰�Opwm1pwm1-pin ‰�Ppwm2pwm2-pin ‰�Qpwm3pwm3-pin ‰�Rgmacrgmii-pins𠉉‰‰����‰‰‰ ��‰‰�>rmii-pins  ‰‰‰‰‰‰‰‰‰‰phy-rst Ž�?phy-pmeb ‹�@phy-int ‹�Aspdifspdif-tx  ‰�dpcfg-pull-none-drv-8ma 9 F��pcfg-pull-up-drv-8ma  Fpcfg-output-high U�Žbuttonspwr-key-l ‹��pmicpmic-int-l ‹�Fdvs-1  Œ�Gdvs-2 Œ�Hrebootap-warm-reset-h  ‰�‘recovery-switchrec-mode-l  ‹tpmtpm-int-h ‰write-protectfw-wp-ap ‰codechp-det ‹�›int-codec Œ�Nmic-det  ‹�šheadsetts3a227e-int-l ‹�*buck-5vdrv-5v ‰�–ledspwr-led1-on Š�†pwr-led1-blink Ž�ˆusb-bc12usb-otg-ilim-sel Š�ƒusb-usb-ilim-sel Š�„usb-hosthub_usb1_pwr_en ‰� hub_usb2_pwr_en ‰�¡usb_otg_pwr_en  ‰�¢chosen aserial2:115200n8memory(memory4€power-button gpio-keysÌdefaultÚ�key-power mPower C) st ~d gpio-restart gpio-restart C) ÌdefaultÚ‘ �Èemmc-pwrseqmmc-pwrseq-emmcÚ’Ìdefault ™“ �sdio-pwrseqmmc-pwrseq-simplep” 7ext_clockÌdefaultÚ• ™� vcc-5vregulator-fixedVvcc_5vey‹LK@£LK@ ¥ ÚJÌdefaultÚ–�Kvcc33-sysregulator-fixed Vvcc33_sysey‹2Z £2Z �vcc50-hdmiregulator-fixed Vvcc50_hdmiey ¸K ¥ Ú—ÌdefaultÚ˜vdd-logicpwm-regulator Vvdd_logic ÙÊ È Ó{ ç”ey‹~ð£™p» sound!rockchip,rockchip-audio-max98090ÌdefaultÚš› úVEYRON-I2S œ !� 6M LM  cž zŸvccsysregulator-fixedVvccsysyevcc33-ioregulator-fixedey Vvcc33_io�Ivcc5-host1-regulatorregulator-fixed ¥ Ú—ÌdefaultÚ  Vvcc5_host1eyvcc5-host2-regulatorregulator-fixed ¥ Ú—ÌdefaultÚ¡ Vvcc5_host2eyvcc5v-otg-regulatorregulator-fixed ¥ Ú) ÌdefaultÚ¢ Vvcc5_otgeyexternal-gmac-clock fixed-clockïÌsY@ Üext_gmac�; #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2mmc0interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymarvell,wakeup-pincap-mmc-highspeedrockchip,default-sample-phasedisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesrx-sample-delay-nsspi-max-frequencyi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-handlephy-modephy-supplyrx_delaytx_delaysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-uswakeup-sourcephysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplydvs-gpiosvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosenable-active-highvin-supplypwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codec