Ð þí'Ž8t( <khadas,edge2rockchip,rk3588s + 7Khadas Edge2aliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000ƒ/i2c@feca0000ˆ/serial@fd890000�/serial@feb40000˜/serial@feb50000 /serial@feb60000¨/serial@feb70000°/serial@feb80000¸/serial@feb90000À/serial@feba0000È/serial@febb0000Ð/serial@febc0000Ø/spi@feb00000Ý/spi@feb10000â/spi@feb20000ç/spi@feb30000ì/spi@fecb0000ñ/mmc@fe2e0000ö/mmc@fe2c0000cpus+cpu-mapcluster0core0ûcore1ûcore2ûcore3ûcluster1core0ûcore1ûcluster2core0ûcore1û cpu@0ÿcpuarm,cortex-a55 psci0 7 G0£,\ l€y@‹€˜€¥@·€Ä Õäïþ cpu@100ÿcpuarm,cortex-a55 psci0 \ l€y@‹€˜€¥@·€ÄÕäïþ cpu@200ÿcpuarm,cortex-a55 psci0 \ l€y@‹€˜€¥@·€ÄÕäïþ cpu@300ÿcpuarm,cortex-a55 psci0 \ l€y@‹€˜€¥@·€ÄÕäïþ cpu@400ÿcpuarm,cortex-a76 psci0 7 G0£,\ ly@‹˜¥@·ÄÕ ïþcpu@500ÿcpuarm,cortex-a76 psci0 \ ly@‹˜¥@·ÄÕ ïþcpu@600ÿcpuarm,cortex-a76 psci0 7 G0£,\ ly@‹˜¥@·ÄÕ ïþcpu@700ÿcpuarm,cortex-a76 psci0 \ ly@‹˜¥@·ÄÕ ïþ idle-states%pscicpu-sleeparm,idle-state2CZdkx{è l2-cache-l0cachen{@�Œ˜Ä l2-cache-l1cachen{@�Œ˜Äl2-cache-l2cachen{@�Œ˜Äl2-cache-l3cachen{@�Œ˜Äl2-cache-b0cachen{@�Œ˜Äl2-cache-b1cachen{@�Œ˜Äl2-cache-b2cachen{@�Œ˜Äl2-cache-b3cachen{@�Œ˜Äl3-cachecachen0{@�Œ˜display-subsystemrockchip,display-subsystem¦firmwareopteelinaro,optee-tzsmcscmi arm,scmi-smc¬‚·+protocol@14 ½ protocol@16 Êpmu-a55arm,cortex-a55-pmu×pmu-a76arm,cortex-a76-pmu×psci arm,psci-1.0smcclock-0 fixed-clockâ)׫€òspll½timerarm,armv8-timerP×    %sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockân6òxin24m½clock-2 fixed-clockâ€òxin32k½reserved-memory+shmem@10f000arm,scmi-shmem ðgpu@fb000000*rockchip,rk3588-maliarm,mali-valhall-csf û ï7 G ëÂ0#corecoregroupstacksÕ ¦0×\]^ jobmmugpu/ =okayþ!D"Õusb@fc000000rockchip,rk3588-dwc3snps,dwc3 ü@×Ü0”“’#ref_clksuspend_clkbus_clkPotg X#$]usb2-phyusb3-phy gutmi_wide/ pRw�§¿à =disabledusb@fc800000"rockchip,rk3588-ehcigeneric-ehci ü€××0Ž�À%X&]usb/ =okayusb@fc840000"rockchip,rk3588-ohcigeneric-ohci ü„ר0Ž�À%X&]usb/ =okayusb@fc880000"rockchip,rk3588-ehcigeneric-ehci üˆ×Ú0�‘À'X(]usb/ =okayusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci üŒ×Û0�‘À'X(]usb/ =okayusb@fcd00000rockchip,rk3588-dwc3snps,dwc3 üÐ@×Þ(0jihkr&#ref_clksuspend_clkbus_clkutmipipePhostX) ]usb3-phy gutmi_widep4w¿à#=okayiommu@fc900000 arm,smmu-v3 ü� @×qsvoeventqgerrorpriqcmdq-sync= =disablediommu@fcb00000 arm,smmu-v3 ü° @×}‚{eventqgerrorpriqcmdq-sync= =disabledsyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfd ýX nsyscon@fd58c000rockchip,rk3588-sys-grfsyscon ýXÀisyscon@fd5a4000rockchip,rk3588-vop-grfsyscon ýZ@ jsyscon@fd5a6000rockchip,rk3588-vo0-grfsyscon ýZ` 0éäsyscon@fd5a8000rockchip,rk3588-vo1-grfsyscon ýZ€@0Ñksyscon@fd5ac000rockchip,rk3588-usb-grfsyscon ýZÀ@âsyscon@fd5b0000rockchip,rk3588-php-grfsyscon ý[+syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon ý[Àåsyscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon ý\@æsyscon@fd5c8000$rockchip,rk3588-usbdpphy-grfsyscon ý\€@ãsyscon@fd5d0000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd ý]@+áusb2phy@0rockchip,rk3588-usb2phy ½0 #phyclk òusb480m_phy0׉pmJphyapb =disabledàotg-portV =disabled#syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd ý]€@+usb2phy@8000rockchip,rk3588-usb2phy €½0 #phyclk òusb480m_phy2ׇpoJphyapb=okay%host-portV=okaya*&syscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd ý]À@+usb2phy@c000rockchip,rk3588-usb2phy À½0 #phyclk òusb480m_phy3׈pp Jphyapb=okay'host-portV=okaya*(syscon@fd5e0000$rockchip,rk3588-hdptxphy-grfsyscon ý^ßsyscon@fd5f0000rockchip,rk3588-iocsyscon ý_çsram@fd600000 mmio-sram ý`ý`+clock-controller@fd7c0000rockchip,rk3588-cru ý|À€7ÌÎ͆‡]qà@GA�«.à2©ø€FÏq)׫€ׄÍe/¯õáׄõá ëÂÍeZ ÀðÑ€ ëÂl+½Êi2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2c ýˆ×=0ts #i2cpclky,ƒdefault+=okayregulator@42rockchip,rk8602 B‘®vdd_cpu_big0_s0½Ñãdpû�ü(-regulator-state-mem3regulator@43 rockchip,rk8603rockchip,rk8602 C‘®vdd_cpu_big1_s0½Ñãdpû�ü(-regulator-state-mem3serial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uart ý‰×K0›œ#baudclkapb_pclkL..Qtxrxy/ƒdefault[e =disabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwm ý‹0’‘ #pwmpclky0ƒdefaultr =disabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwm ý‹0’‘ #pwmpclky1ƒdefaultr =disabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwm ý‹ 0’‘ #pwmpclky2ƒdefaultr =disabledpwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwm ý‹00’‘ #pwmpclky3ƒdefaultr =disabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfd ý�€lpower-controller!rockchip,rk3588-power-controller}+=okay power-domain@8 }+power-domain@9  0!#" ‘456}+power-domain@10 0!#"‘7}power-domain@11 0!#"‘8}power-domain@12 0‘9:;<}power-domain@13 +}power-domain@14 (0€¯­�‘=}power-domain@15  0…¯­†‘>}power-domain@16 0µ¶ ‘?@A+}power-domain@17  0ºµ¶» ‘BCD}power-domain@21 �0¯®­°›š�žŸ ¡¢£¤¥¦¨§ ‘EFGHIJKL+}power-domain@23 0CA¯‘M}power-domain@14  0€¯­�‘=}power-domain@15 0…¯­‘>}power-domain@22 0«ª‘N}power-domain@24 0[Z]‘OP+}power-domain@25 80çèæäßÞZ‘Q}power-domain@26 80Q‘RS}power-domain@27 00ÒÓÐÏÖÕ‘TUVW+}power-domain@28  0ÒÓ‘XY}power-domain@29 (0ÇÆÊÉÓ‘Z[}power-domain@30 0z{‘\}power-domain@31 @0WŒÀ�Ž��‘‘]^_`}power-domain@33 !0WZ[}power-domain@34 "0WZ[}power-domain@37 %0Š2‘a}power-domain@38 &045}power-domain@40 (‘b}video-codec@fdb50000+rockchip,rk3588-vpu121rockchip,rk3568-vpu ýµ×wvdpu0±² #aclkhclk˜c/ iommu@fdb50800,rockchip,rk3588-iommurockchip,rk3568-iommu ýµ@×v #aclkiface0±²/ =crga@fdb80000(rockchip,rk3588-rgarockchip,rk3288-rga ý¸€×t0¨§©#aclkhclksclkprqp Jcoreaxiahb/ video-codec@fdba0000rockchip,rk3588-vepu121 ýº×z0�ž #aclkhclk˜d/ iommu@fdba0800,rockchip,rk3588-iommurockchip,rk3568-iommu ýº@×y0�ž #aclkiface/ =dvideo-codec@fdba4000rockchip,rk3588-vepu121 ýº@×|0Ÿ  #aclkhclk˜e/ iommu@fdba4800,rockchip,rk3588-iommurockchip,rk3568-iommu ýºH@×{0Ÿ  #aclkiface/ =evideo-codec@fdba8000rockchip,rk3588-vepu121 ýº€×~0¡¢ #aclkhclk˜f/ iommu@fdba8800,rockchip,rk3588-iommurockchip,rk3568-iommu ýºˆ@×}0¡¢ #aclkiface/ =fvideo-codec@fdbac000rockchip,rk3588-vepu121 ýºÀ×€0£¤ #aclkhclk˜g/ iommu@fdbac800,rockchip,rk3588-iommurockchip,rk3568-iommu ýºÈ@×0£¤ #aclkiface/ =gvideo-codec@fdc70000rockchip,rk3588-av1-vpu ýÇ×lvdpu7ACGׄׄ0AC #aclkhclk/  pþýÿvop@fdd90000rockchip,rk3588-vop  ýÙBýÙPŸvopgamma-lutל80]\abcd[7#aclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_vop˜h/ li©jºkËl =disabledports+port@0+ port@1+ port@2+ port@3+ iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu  ýÙ~ýÙל0]\ #aclkiface=/  =disabledhi2s@fddc0000rockchip,rk3588-i2s-tdm ýÜ׸0ììá#mclk_txmclk_rxhclk7êØLmQtx/ p¸Jtx-mï =disabledi2s@fddf0000rockchip,rk3588-i2s-tdm ýß×¹0445#mclk_txmclk_rxhclk71ØLmQtx/ pØJtx-mï =disabledi2s@fddfc000rockchip,rk3588-i2s-tdm ýßÀ×½000,#mclk_txmclk_rxhclk7-ØLmQrx/ pìJrx-mï =disabledqos@fdf35000rockchip,rk3588-qossyscon ýóP 9qos@fdf35200rockchip,rk3588-qossyscon ýóR :qos@fdf35400rockchip,rk3588-qossyscon ýóT ;qos@fdf35600rockchip,rk3588-qossyscon ýóV <qos@fdf36000rockchip,rk3588-qossyscon ýó` \qos@fdf39000rockchip,rk3588-qossyscon ýó� aqos@fdf3d800rockchip,rk3588-qossyscon ýóØ bqos@fdf3e000rockchip,rk3588-qossyscon ýóà ^qos@fdf3e200rockchip,rk3588-qossyscon ýóâ ]qos@fdf3e400rockchip,rk3588-qossyscon ýóä _qos@fdf3e600rockchip,rk3588-qossyscon ýóæ `qos@fdf40000rockchip,rk3588-qossyscon ýô Zqos@fdf40200rockchip,rk3588-qossyscon ýô [qos@fdf40400rockchip,rk3588-qossyscon ýô Tqos@fdf40500rockchip,rk3588-qossyscon ýô Uqos@fdf40600rockchip,rk3588-qossyscon ýô Vqos@fdf40800rockchip,rk3588-qossyscon ýô Wqos@fdf41000rockchip,rk3588-qossyscon ýô Xqos@fdf41100rockchip,rk3588-qossyscon ýô Yqos@fdf60000rockchip,rk3588-qossyscon ýö ?qos@fdf60200rockchip,rk3588-qossyscon ýö @qos@fdf60400rockchip,rk3588-qossyscon ýö Aqos@fdf61000rockchip,rk3588-qossyscon ýö Bqos@fdf61200rockchip,rk3588-qossyscon ýö Cqos@fdf61400rockchip,rk3588-qossyscon ýö Dqos@fdf62000rockchip,rk3588-qossyscon ýö =qos@fdf63000rockchip,rk3588-qossyscon ýö0 >qos@fdf64000rockchip,rk3588-qossyscon ýö@ Mqos@fdf66000rockchip,rk3588-qossyscon ýö` Eqos@fdf66200rockchip,rk3588-qossyscon ýöb Fqos@fdf66400rockchip,rk3588-qossyscon ýöd Gqos@fdf66600rockchip,rk3588-qossyscon ýöf Hqos@fdf66800rockchip,rk3588-qossyscon ýöh Iqos@fdf66a00rockchip,rk3588-qossyscon ýöj Jqos@fdf66c00rockchip,rk3588-qossyscon ýöl Kqos@fdf66e00rockchip,rk3588-qossyscon ýön Lqos@fdf67000rockchip,rk3588-qossyscon ýöp Nqos@fdf67200rockchip,rk3588-qossyscon ýör qos@fdf70000rockchip,rk3588-qossyscon ý÷ 7qos@fdf71000rockchip,rk3588-qossyscon ý÷ 8qos@fdf72000rockchip,rk3588-qossyscon ý÷ 4qos@fdf72200rockchip,rk3588-qossyscon ý÷" 5qos@fdf72400rockchip,rk3588-qossyscon ý÷$ 6qos@fdf80000rockchip,rk3588-qossyscon ýø Qqos@fdf81000rockchip,rk3588-qossyscon ýø Rqos@fdf81200rockchip,rk3588-qossyscon ýø Sqos@fdf82000rockchip,rk3588-qossyscon ýø Oqos@fdf82200rockchip,rk3588-qossyscon ýø" Pdfi@fe060000 þrockchip,rk3588-dfi@×&0:Ënpcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?00CH>MR°)#aclk_mstaclk_slvaclk_dbipclkauxpipeÿpciP×ø÷öõôsyspmcmsglegacyerr `.oooo<M\0p0dX) ]pcie-phy/ "Tóóó ó à À À@0 @À@þóŸdbiapbconfigp). Jpwrpipe+ =disabledlegacy-interrupt-controllern  ×õopcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie@O00DI?NSs)#aclk_mstaclk_slvaclk_dbipclkauxpipeÿpciP×ýüûúùsyspmcmsglegacyerr `.qqqq<M\@p@dXr ]pcie-phy/ "Tôôô ô à @0 A@þôŸdbiapbconfigp*/ Jpwrpipe+=okayƒdefaultys ƒt�ulegacy-interrupt-controllern  ×úqethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20a þ ×êémacirqeth_wake_irq(067Y^50#stmmacethclk_mac_refpclk_macaclk_macptp_ref/ !p$ JstmmacethliŸ+°vÀÑwäx÷ =disabledmdiosnps,dwmac-mdio+stmmac-axi-config vrx-queues-config*wqueue0queue1tx-queues-config@xqueue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci þ!×(0b_eTo#satapmaliverxoobrefasicV+ =disabledsata-port@0 h@Xr ]sata-phyu „ sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci þ#×(0dagVq#satapmaliverxoobrefasicV+ =disabledsata-port@0 h@X) ]sata-phyu „ spi@fe2b0000 rockchip,sfc þ+@×Î0/0#clk_sfchclk_sfc+=okayƒdefaultyyflash@0jedec,spi-nor “õ᥶mmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc þ,@×Ë 0  ­®#biuciuciu-driveciu-sampleÇ— ëƒdefaultyz{|}/ (=okay¬Òãîõý ~mmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc þ-@×Ì 0Š‹«¬#biuciuciu-driveciu-sampleÇ— ëƒdefaulty€/ % =disabledmmc@fe2e0000rockchip,rk3588-dwcmshc þ.×Í7-., G ëÂn6 ëÂ(0,*+-.#corebusaxiblocktimer— ëÂy�‚ƒ„…ƒdefault(pJcorebusaxiblocktimer=okay¬õ$*8Gi2s@fe470000rockchip,rk3588-i2s-tdm þG×´0+/(#mclk_txmclk_rxhclk7)-ØL..Qtxrx/ &p*+ Jtx-mrx-maƒdefault(y†‡ˆ‰Š‹Œ�Ž�ï =disabledi2s@fe480000rockchip,rk3588-i2s-tdm þH×µ0y}u#mclk_txmclk_rxhclkL..Qtxrxp^_ Jtx-mrx-maƒdefault(y�‘’“”•–—˜™ï =disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2s þI×¶0#i2s_clki2s_hclk7ØLššQtxrx/ &ƒdefaulty›œ�žï =disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2s þJ×·0%#i2s_clki2s_hclk7"ØLššQtxrx/ &ƒdefaultyŸ ¡¢ï =disabledinterrupt-controller@fe600000 arm,gic-v3  þ`þh× n|þa†¨8‘ +msi-controller@fe640000arm,gic-v3-its þd‘ pmsi-controller@fe660000arm,gic-v3-its þf‘ ppi-partitionsinterrupt-partition-0«interrupt-partition-1« dma-controller@fea10000arm,pl330arm,primecell þ¡@ ×VW´0n #apb_pclkË.dma-controller@fea30000arm,pl330arm,primecell þ£@ ×XY´0o #apb_pclkËši2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c þ©0ƒ{ #i2cpclk×>y£ƒdefault+ =disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c þª0„| #i2cpclk×?y¤ƒdefault+=okayrtc@51haoyu,hym8563 Q½òhym8563Öi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c þ«0…} #i2cpclk×@y¥ƒdefault+ =disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c þ¬0†~ #i2cpclk×Ay¦ƒdefault+ =disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c þ­0‡ #i2cpclk×By§ƒdefault+ =disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer þ® ×!0TW #pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt þ¯0dc #tclkpclk×;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spi þ°×F0—’#spiclkapb_pclkL..Qtxrxä y¨©ªƒdefault+ =disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spi þ±×G0˜“#spiclkapb_pclkL..Qtxrxä y«¬­ƒdefault+ =disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spi þ²×H0™”#spiclkapb_pclkLššQtxrxäy®¯ƒdefault+=okay7™G ëÂpmic@0rockchip,rk806  °×ƒdefaulty±²³´“B@ë - - - '- 3- ?- K- W- c- o- |µ ‰- –¶ £¶ °- ¼ Ìdvs1-null-pins Øgpio_pwrctrl1 Ýpin_fun0²dvs2-null-pins Øgpio_pwrctrl2 Ýpin_fun0³dvs3-null-pins Øgpio_pwrctrl3 Ýpin_fun0´regulatorsdcdc-reg1Ñ æ�ãdpû~ð ®vdd_gpu_s00Ô"regulator-state-mem3dcdc-reg2½Ñãdpû~ð®vdd_cpu_lit_s00Ôregulator-state-mem3dcdc-reg3½Ñã L¸û q° ®vdd_log_s00Ôregulator-state-mem3  q°dcdc-reg4½Ñãdpû~ð ®vdd_vdenc_s00Ôregulator-state-mem3dcdc-reg5½Ñã L¸û »  ®vdd_ddr_s00Ôregulator-state-mem3  øPdcdc-reg6½Ñ ®vdd2_ddr_s3regulator-state-mem dcdc-reg7½Ñã„€û„€®vdd_2v0_pldo_s30Ôµregulator-state-mem  „€dcdc-reg8½Ñã2Z û2Z  ®vcc_3v3_s3øregulator-state-mem  2Z dcdc-reg9½Ñ ®vddq_ddr_s0regulator-state-mem3dcdc-reg10½Ñãw@ûw@ ®vcc_1v8_s3regulator-state-mem  w@pldo-reg1½Ñãw@ûw@ ®avcc_1v8_s0Øregulator-state-mem3pldo-reg2½Ñãw@ûw@ ®vcc_1v8_s0regulator-state-mem3 w@pldo-reg3½ÑãO€ûO€ ®avdd_1v2_s0regulator-state-mem3pldo-reg4½Ñã2Z û2Z 0Ô ®vcc_3v3_s0regulator-state-mem3pldo-reg5½Ñãw@û2Z 0Ô ®vccio_sd_s0regulator-state-mem3pldo-reg6½Ñãw@ûw@ ®pldo6_s3regulator-state-mem  w@nldo-reg1½Ñã q°û q° ®vdd_0v75_s3regulator-state-mem   q°nldo-reg2½Ñã øPû øP®vdd_ddr_pll_s0regulator-state-mem3  øPnldo-reg3½Ñã q°û q° ®avdd_0v75_s0regulator-state-mem3nldo-reg4½Ñã øPû øP ®vdd_0v85_s0regulator-state-mem3nldo-reg5½Ñã q°û q° ®vdd_0v75_s0regulator-state-mem3spi@feb30000(rockchip,rk3588-spirockchip,rk3066-spi þ³×I0š•#spiclkapb_pclkLššQtxrxä y·¸¹ƒdefault+ =disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uart þ´×L0«Ÿ#baudclkapb_pclkL.. Qtxrxyºƒdefaulte[ =disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uart þµ×M0¯ #baudclkapb_pclkL. . Qtxrxy»ƒdefaulte[=okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uart þ¶×N0³¡#baudclkapb_pclkL. . Qtxrxy¼ƒdefaulte[ =disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uart þ·×O0·¢#baudclkapb_pclkLš š Qtxrxy½ƒdefaulte[ =disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uart þ¸×P0»£#baudclkapb_pclkLš š Qtxrxy¾ƒdefaulte[ =disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uart þ¹×Q0¿¤#baudclkapb_pclkLš šQtxrxy¿ƒdefaulte[ =disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uart þº×R0Ã¥#baudclkapb_pclkLmmQtxrxyÀƒdefaulte[ =disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uart þ»×S0Ǧ#baudclkapb_pclkLm m QtxrxyÁƒdefaulte[ =disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uart þ¼×T0˧#baudclkapb_pclkLm m QtxrxyÂÃdefaulte[=okaypwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm þ½0LK #pwmpclkyădefaultr =disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm þ½0LK #pwmpclkyŃdefaultr =disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm þ½ 0LK #pwmpclkyƃdefaultr =disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm þ½00LK #pwmpclkyǃdefaultr =disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¾0ON #pwmpclkyȃdefaultr =disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¾0ON #pwmpclkyɃdefaultr =disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¾ 0ON #pwmpclkyʃdefaultr =disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¾00ON #pwmpclky˃defaultr=okayópwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¿0RQ #pwmpclkỹdefaultr =disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¿0RQ #pwmpclky̓defaultr =disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¿ 0RQ #pwmpclky΃defaultr=okayôpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¿00RQ #pwmpclkyσdefaultr=okayõthermal-zonespackage-thermal 6 L ZÐtripspackage-crit jÁ8 v criticalbigcore0-thermal 6d L ZÐtripsbigcore0-alert jL vÐpassiveÑbigcore0-crit jÁ8 v criticalcooling-mapsmap0 �Ñ †ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿbigcore2-thermal 6d L ZÐtripsbigcore2-alert jL vÐpassiveÒbigcore2-crit jÁ8 v criticalcooling-mapsmap0 �Ò †ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿlittlecore-thermal 6d L ZÐtripslittlecore-alert jL vÐpassiveÓlittlecore-crit jÁ8 v criticalcooling-mapsmap0 �Ó0 †ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcenter-thermal 6 L ZÐtripscenter-crit jÁ8 v criticalgpu-thermal 6d L ZÐtripsgpu-alert jL vÐpassiveÔgpu-crit jÁ8 v criticalcooling-mapsmap0 �Ô †Õÿÿÿÿÿÿÿÿnpu-thermal 6 L ZÐtripsnpu-crit jÁ8 v criticaltsadc@fec00000rockchip,rk3588-tsadc þÀ×�0ž�#tsadcapb_pclk7žG„€pVWJtsadc-apbtsadc •ÔÀ ¬ ÃyÖ Þ׃defaultsleep è=okayÐadc@fec10000rockchip,rk3588-saradc þÁ׎ þ0‘�#saradcapb_pclkpU Jsaradc-apb=okay Øði2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c þÈ0ˆ€ #i2cpclk×CyÙƒdefault+ =disabledi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c þÉ0‰� #i2cpclk×DyÚƒdefault+ =disabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c þÊ0Š‚ #i2cpclk×EyÛƒdefault+ =disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spi þË×J0›–#spiclkapb_pclkLm mQtxrxä yÜÝÞƒdefault+ =disabledefuse@fecc0000rockchip,rk3588-otp þÌ 0Œ‹��#otpapb_pclkphyarbp§¦¨ Jotpapbarb+cpu-code@2 id@7 cpu-leakage@17 cpu-leakage@18 cpu-leakage@19 log-leakage@1a gpu-leakage@1b cpu-version@1c  npu-leakage@28 (codec-leakage@29 )dma-controller@fed10000arm,pl330arm,primecell þÑ@ ×Z[´0p #apb_pclkËmphy@fed60000rockchip,rk3588-hdptx-phy þÖ 0 T#refapbV8p#cde!""Jphyapbinitcmnlaneroplllcplllß =disabledphy@fed80000rockchip,rk3588-usbdp-phy þØV0¡lVà#refclkimmortalpclkutmi(p   Jinitcmnlanepcs_apbpma_apb !á 4â Eã [ä =disabled$phy@fee00000rockchip,rk3588-naneng-combphy þà0¨vW #refapbpipe7¨GõáVp<CJphyapb k+ }å=okayrphy@fee20000rockchip,rk3588-naneng-combphy þâ0ªxW #refapbpipe7ªGõáVp>EJphyapb k+ }æ=okay)sram@ff001000 mmio-sram ÿðÿð+pinctrlrockchip,rk3588-pinctrllç+ègpio@fd8a0000rockchip,gpio-bank ýŠ×0qr ¼ “è n Ì °gpio@fec20000rockchip,gpio-bank þÂ×0st ¼ “è n Ì ñgpio@fec30000rockchip,gpio-bank þÃ×0uv ¼ “è@ n Ì gpio@fec40000rockchip,gpio-bank þÄ×0wx ¼ “è` n Ì tgpio@fec50000rockchip,gpio-bank þÅ×0yz ¼ “è€ n Ì pcfg-pull-up Ÿípcfg-pull-down ¬ëpcfg-pull-none »épcfg-pull-none-drv-level-2 » Èïpcfg-pull-up-drv-level-1 Ÿ Èîpcfg-pull-up-drv-level-2 Ÿ Èêpcfg-pull-none-smt » ×ìauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout ìé�emmc-bus8€ ìêêêêêêêê‚emmc-clk ìêƒemmc-cmd ìê„emmc-data-strobe ìë…eth1fspifspim2-pins` ìêêêêêêygmac1gpuhdmii2c0i2c0m2-xfer ììì,i2c1i2c1m0-xfer ì ì ì£i2c2i2c2m0-xfer ì ì ì¤i2c3i2c3m0-xfer ì ì ì¥i2c4i2c4m0-xfer ì ì ì¦i2c5i2c5m0-xfer ì ì ì§i2c6i2c6m0-xfer ì ì ìÙi2c7i2c7m0-xfer ì ì ìÚi2c8i2c8m0-xfer ì ì ìÛi2s0i2s0-lrck ìé†i2s0-sclk ìé‡i2s0-sdi0 ìéˆi2s0-sdi1 ìé‰i2s0-sdi2 ìéŠi2s0-sdi3 ìé‹i2s0-sdo0 ìéŒi2s0-sdo1 ìé�i2s0-sdo2 ìéŽi2s0-sdo3 ìé�i2s1i2s1m0-lrck ìé�i2s1m0-sclk ìé‘i2s1m0-sdi0 ìé’i2s1m0-sdi1 ìé“i2s1m0-sdi2 ìé”i2s1m0-sdi3 ìé•i2s1m0-sdo0 ì é–i2s1m0-sdo1 ì é—i2s1m0-sdo2 ì é˜i2s1m0-sdo3 ì é™i2s2i2s2m1-lrck ìé›i2s2m1-sclk ì éœi2s2m1-sdi ì é�i2s2m1-sdo ì éži2s3i2s3-lrck ìéŸi2s3-sclk ìé i2s3-sdi ìé¡i2s3-sdo ìé¢jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp ìíéééééé±pmupwm0pwm0m0-pins ìé0pwm1pwm1m0-pins ìé1pwm2pwm2m0-pins ìé2pwm3pwm3m0-pins ìé3pwm4pwm4m0-pins ì éÄpwm5pwm5m0-pins ì éÅpwm6pwm6m0-pins ì éÆpwm7pwm7m0-pins ì éÇpwm8pwm8m0-pins ì éÈpwm9pwm9m0-pins ì éÉpwm10pwm10m0-pins ì éÊpwm11pwm11m1-pins ì éËpwm12pwm12m0-pins ì éÌpwm13pwm13m0-pins ì éÍpwm14pwm14m1-pins ì éÎpwm15pwm15m1-pins ì éÏrefclksatasata0sata1sata2sdiosdiom1-pins` ìéííííí€sdmmcsdmmc-bus4@ ìêêêê}sdmmc-clk ìêzsdmmc-cmd ìê{sdmmc-det ìí|spdif0spdif1spi0spi0m0-pins0 ìîîîªspi0m0-cs0 ìî¨spi0m0-cs1 ìî©spi1spi1m1-pins0 ìîîî­spi1m1-cs0 ìî«spi1m1-cs1 ìî¬spi2spi2m2-pins0 ìî îî¯spi2m2-cs0 ì î®spi3spi3m1-pins0 ìî îî¹spi3m1-cs0 ìî·spi3m1-cs1 ìî¸spi4spi4m0-pins0 ìîîîÞspi4m0-cs0 ìîÜspi4m0-cs1 ìîÝtsadctsadc-shut-org ìéÖuart0uart0m1-xfer ìí í/uart1uart1m1-xfer ì í íºuart2uart2m0-xfer ì í í»uart3uart3m1-xfer ì í í¼uart4uart4m1-xfer ì í í½uart5uart5m1-xfer ì í í¾uart6uart6m1-xfer ì í í¿uart7uart7m1-xfer ì í íÀuart8uart8m1-xfer ì í íÁuart9uart9m2-xfer ì í íÂuart9m2-ctsn ì éÃvopbt656gpio-functsadc-gpio-func ìé×vdd_sdvdd-sd-en ìíùpcie2pcie2-2-rst ìéspcie2-2-vcc-en ìéöusbvcc5v0-host-en ì é÷ir-receiverir-receiver-pin ìéòwireless-bluetoothbt-reset-pin ìébt-wake-pin ìíbt-wake-host-irq ìëopp-table-cluster0operating-points-v2 ú opp-1008000000 <Ü L¸ L¸~ð œ@opp-1200000000 G†Œ ß4 ß4~ð œ@opp-1416000000 Tfr ¢„ ¢„~ð œ@ +opp-1608000000 _Ø" øP øP~ð œ@opp-1800000000 kIÒ ~ð~ð~ð œ@opp-table-cluster1operating-points-v2 úopp-1200000000 G†Œ L¸ L¸B@ œ@opp-1416000000 Tfr  B@ œ@opp-1608000000 _Ø" ¢„ ¢„B@ œ@opp-1800000000 kIÒ øP øPB@ œ@opp-2016000000 x)¸ HHB@ œ@opp-2208000000 ƒ›h llB@ œ@opp-2400000000 �  B@B@B@ œ@opp-table-cluster2operating-points-v2 úopp-1200000000 G†Œ L¸ L¸B@ œ@opp-1416000000 Tfr  B@ œ@opp-1608000000 _Ø" ¢„ ¢„B@ œ@opp-1800000000 kIÒ øP øPB@ œ@opp-2016000000 x)¸ HHB@ œ@opp-2208000000 ƒ›h llB@ œ@opp-2400000000 �  B@B@B@ œ@opp-table-gpuoperating-points-v2!opp-300000000 ᣠL¸ L¸ øPopp-400000000 ׄ L¸ L¸ øPopp-500000000 Íe L¸ L¸ øPopp-600000000 #ÃF L¸ L¸ øPopp-700000000 )¹' ®` ®` øPopp-800000000 /¯ q° q° øPopp-900000000 5¤é 5 5 øPopp-1000000000 ;šÊ øP øP øPchosen 7serial2:1500000n8adc-keys adc-keys Cð Obuttons `w@ zdbutton-function ˆFunction ŽÐ ™Bhir-receivergpio-ir-receiver ‰ñƒdefaultyòleds pwm-ledsled-0 ˆred_led ³ ¹off Ýindicator Çnone Ýÿ ìóa¨led-1 ˆgreen_led ³ ¹on Ýpower Çdefault-on Ýÿ ìôa¨led-2 ˆblue_led ³ ¹off Ýindicator Çnone Ýÿ ìõa¨vcc3v3-pcie-wl-regulatorregulator-fixed ñ ‰°ƒdefaultyö®vcc3v3_pcie_wlã2Z û2Z  ˆ(-uvcc5v0-host-regulatorregulator-fixed ®vcc5v0_hostѽãLK@ûLK@ ñ ñ ƒdefaulty÷(-*vcc5v0-sys-regulatorregulator-fixed ®vcc5v0_sys½ÑãLK@ûLK@-vcc-1v1-nldo-s3-regulatorregulator-fixed®vcc_1v1_nldo_s3½ÑãÈàûÈà(-¶vdd-3v3-sd-regulatorregulator-fixed ®vdd_3v3_sd ‰ñÑ ñã2Z û2Z (øƒdefaultyù~ compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4mmc0mmc1cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesno-mapclock-namespower-domainsstatusmali-supplydr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosiommusreg-namesrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesinterrupt-controllerreset-gpiosvpcie3v3-supplyrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxspi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthfifo-depthcap-sd-highspeeddisable-wpno-mmcno-sdiosd-uhs-sdr104vmmc-supplyvqmmc-supplyno-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellswakeup-sourcenum-cssystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplybitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltcolordefault-statelinux,default-triggermax-brightnesspwmsenable-active-highstartup-delay-usgpio