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+éÝsyscon@fd5a8000rockchip,rk3588-vo1-grfsysconýZ€@+Ñjsyscon@fd5ac000rockchip,rk3588-usb-grfsysconýZÀ@Ûsyscon@fd5b0000rockchip,rk3588-php-grfsysconý[*syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsysconý[ÀÞsyscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsysconý\@ßsyscon@fd5c8000$rockchip,rk3588-usbdpphy-grfsysconý\€@Üsyscon@fd5d0000.rockchip,rk3588-usb2phy-grfsysconsimple-mfdý]@+Úusb2phy@0rockchip,rk3588-usb2phy¸+ phyclk íusb480m_phy0Ò‰_m9phyapb 8disabledÙotg-portE 8disabled"syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfdý]€@+usb2phy@8000rockchip,rk3588-usb2phy€¸+ phyclk íusb480m_phy2Ò‡_o9phyapb8okay$host-portE8okayP)%syscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfdý]À@+usb2phy@c000rockchip,rk3588-usb2phyÀ¸+ phyclk íusb480m_phy3Òˆ_p 9phyapb8okay&host-portE8okayP)'syscon@fd5e0000$rockchip,rk3588-hdptxphy-grfsysconý^Øsyscon@fd5f0000rockchip,rk3588-iocsysconý_àsram@fd600000 mmio-sramý`ý`+clock-controller@fd7c0000rockchip,rk3588-cruý|À€2ÌÎ͆‡]qà@BA�«.à2©ø€FÏq)׫€ׄÍe/¯õáׄõá ëÂÍeZ ÀðÑ€ ëÂ[*¸Åi2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2cýˆÒ=+ts i2cpclkh+rdefault+8okayregulator@42rockchip,rk8602B€�vdd_cpu_big0_s0¬ÀÒdpê�ü,regulator-state-mem"regulator@43 rockchip,rk8603rockchip,rk8602C€�vdd_cpu_big1_s0¬ÀÒdpê�ü,regulator-state-mem"serial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartý‰ÒK+›œbaudclkapb_pclk;--@txrxh.rdefaultJT 8disabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwmý‹+’‘ pwmpclkh/rdefaulta 8disabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwmý‹+’‘ pwmpclkh0rdefaulta 8disabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwmý‹ +’‘ pwmpclkh1rdefaulta8okaypwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwmý‹0+’‘ pwmpclkh2rdefaulta 8disabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfdý�€kpower-controller!rockchip,rk3588-power-controllerl+8okay power-domain@8l+power-domain@9  +!#" €345l+power-domain@10 +!#"€6lpower-domain@11 +!#"€7lpower-domain@12 +€89:;lpower-domain@13 +lpower-domain@14(+€¯­�€<lpower-domain@15 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iommu@fdba4800,rockchip,rk3588-iommurockchip,rk3568-iommuýºH@Ò{+Ÿ  aclkiface* ,dvideo-codec@fdba8000rockchip,rk3588-vepu121ýº€Ò~+¡¢ aclkhclk‡e* iommu@fdba8800,rockchip,rk3588-iommurockchip,rk3568-iommuýºˆ@Ò}+¡¢ aclkiface* ,evideo-codec@fdbac000rockchip,rk3588-vepu121ýºÀÒ€+£¤ aclkhclk‡f* iommu@fdbac800,rockchip,rk3588-iommurockchip,rk3568-iommuýºÈ@Ò+£¤ aclkiface* ,fvideo-codec@fdc70000rockchip,rk3588-av1-vpuýÇÒlvdpu2ACBׄׄ+AC aclkhclk*  _þýÿvop@fdd90000rockchip,rk3588-vop ýÙBýÙPŽvopgamma-lutÒœ8+]\abcd[7aclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_vop‡g* [h˜i©jºk 8disabledports+port@0+port@1+port@2+port@3+iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu ýÙ~ýÙÒœ+]\ aclkiface,*  8disabledgi2s@fddc0000rockchip,rk3588-i2s-tdmýÜÒ¸+ììámclk_txmclk_rxhclk2êÇ;l@tx* _¸9tx-mÞ 8disabledi2s@fddf0000rockchip,rk3588-i2s-tdmýßÒ¹+445mclk_txmclk_rxhclk21Ç;l@tx* _Ø9tx-mÞ 8disabledi2s@fddfc000rockchip,rk3588-i2s-tdmýßÀÒ½+00,mclk_txmclk_rxhclk2-Ç;l@rx* _ì9rx-mÞ 8disabledqos@fdf35000rockchip,rk3588-qossysconýóP 8qos@fdf35200rockchip,rk3588-qossysconýóR 9qos@fdf35400rockchip,rk3588-qossysconýóT :qos@fdf35600rockchip,rk3588-qossysconýóV ;qos@fdf36000rockchip,rk3588-qossysconýó` [qos@fdf39000rockchip,rk3588-qossysconýó� `qos@fdf3d800rockchip,rk3588-qossysconýóØ aqos@fdf3e000rockchip,rk3588-qossysconýóà ]qos@fdf3e200rockchip,rk3588-qossysconýóâ \qos@fdf3e400rockchip,rk3588-qossysconýóä ^qos@fdf3e600rockchip,rk3588-qossysconýóæ _qos@fdf40000rockchip,rk3588-qossysconýô Yqos@fdf40200rockchip,rk3588-qossysconýô Zqos@fdf40400rockchip,rk3588-qossysconýô Sqos@fdf40500rockchip,rk3588-qossysconýô Tqos@fdf40600rockchip,rk3588-qossysconýô Uqos@fdf40800rockchip,rk3588-qossysconýô Vqos@fdf41000rockchip,rk3588-qossysconýô Wqos@fdf41100rockchip,rk3588-qossysconýô Xqos@fdf60000rockchip,rk3588-qossysconýö >qos@fdf60200rockchip,rk3588-qossysconýö ?qos@fdf60400rockchip,rk3588-qossysconýö @qos@fdf61000rockchip,rk3588-qossysconýö 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Nqos@fdf82200rockchip,rk3588-qossysconýø" Odfi@fe060000þrockchip,rk3588-dfi@Ò&0:ºmpcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcieï0?0+CH>MR°)aclk_mstaclk_slvaclk_dbipclkauxpipeúpciPÒø÷öõôsyspmcmsglegacyerrù `nnnn+<K0o0SG( Lpcie-phy* "Tóóó ó à À À@0 @À@þóŽdbiapbconfig_). 9pwrpipe+ 8disabledlegacy-interrupt-controller]ù Òõnpcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcieï@O0+DI?NSs)aclk_mstaclk_slvaclk_dbipclkauxpipeúpciPÒýüûúùsyspmcmsglegacyerrù `pppp+<K@o@SGq Lpcie-phy* "Tôôô ô à @0 A@þôŽdbiapbconfig_*/ 9pwrpipe+ 8disabledlegacy-interrupt-controller]ù Òúpethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20aþ Òêémacirqeth_wake_irq(+67Y^50stmmacethclk_mac_refpclk_macaclk_macptp_ref* !_$ 9stmmaceth[hr*ƒr“¤s·tÊ 8disabledmdiosnps,dwmac-mdio+stmmac-axi-configÓÝírrx-queues-configýsqueue0queue1tx-queues-configtqueue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahciþ!Ò(+b_eTosatapmaliverxoobrefasic)+ 8disabledsata-port@0;@Gq Lsata-phyH W sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahciþ#Ò(+dagVqsatapmaliverxoobrefasic)+ 8disabledsata-port@0;@G( Lsata-phyH W spi@fe2b0000 rockchip,sfcþ+@ÒÎ+/0clk_sfchclk_sfc+ 8disabledmmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshcþ,@ÒË +  ­®biuciuciu-driveciu-samplefq ëÂrdefaulthuvwx* ( 8disabledmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshcþ-@ÒÌ +Š‹«¬biuciuciu-driveciu-samplefq ëÂrdefaulthy* % 8disabledmmc@fe2e0000rockchip,rk3588-dwcmshcþ.ÒÍ2-., B ëÂn6 ëÂ(+,*+-.corebusaxiblocktimerq ëÂhz{|}~rdefault(_9corebusaxiblocktimer8okay‰˜²ºÀi2s@fe470000rockchip,rk3588-i2s-tdmþGÒ´++/(mclk_txmclk_rxhclk2)-Ç;--@txrx* &_*+ 9tx-mrx-mÎrdefault(h€�‚ƒ„…†‡ˆÞ 8disabledi2s@fe480000rockchip,rk3588-i2s-tdmþHÒµ+y}umclk_txmclk_rxhclk;--@txrx_^_ 9tx-mrx-mÎrdefault(h‰Š‹Œ�Ž��‘’Þ 8disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sþIÒ¶+i2s_clki2s_hclk2Ç;““@txrx* &rdefaulth”•–—Þ 8disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sþJÒ·+%i2s_clki2s_hclk2"Ç;““@txrx* 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tclkpclkÒ;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiþ°ÒF+—’spiclkapb_pclk;--@txrxQ h£¤¥rdefault+ 8disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiþ±ÒG+˜“spiclkapb_pclk;--@txrxQ h¦§¨rdefault+ 8disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiþ²ÒH+™”spiclkapb_pclk;““@txrxQh©ªrdefault+8okay2™B ëÂpmic@0rockchip,rk806Xh žÒrdefaulth«¬­®tB@†ž,ª,¶,Â,Î,Ú,æ,ò,þ, , ¯ $, 1° >° K,dvs1-null-pins Wgpio_pwrctrl1 \pin_fun0¬dvs2-null-pins Wgpio_pwrctrl2 \pin_fun0­dvs3-null-pins Wgpio_pwrctrl3 \pin_fun0®regulatorsdcdc-reg1 �vdd_gpu_s0À e�Òdpê~ð0Ôregulator-state-mem"dcdc-reg2�vdd_cpu_lit_s0¬ÀÒdpê~ð0Ôregulator-state-mem"dcdc-reg3 �vdd_log_s0¬ÀÒ L¸ê q°0Ôregulator-state-mem" � q°dcdc-reg4 �vdd_vdenc_s0¬ÀÒdpê~ð0Ôregulator-state-mem"dcdc-reg5 �vdd_ddr_s0¬ÀÒ L¸ê » 0Ôregulator-state-mem" � øPdcdc-reg6 �vdd2_ddr_s3¬Àregulator-state-mem �dcdc-reg7�vdd_2v0_pldo_s3¬ÀÒ„€ê„€¯regulator-state-mem � �„€dcdc-reg8 �vcc_3v3_s3¬ÀÒ2Z ê2Z regulator-state-mem � �2Z dcdc-reg9 �vddq_ddr_s0¬Àregulator-state-mem"dcdc-reg10 �vcc_1v8_s3¬ÀÒw@êw@regulator-state-mem � �w@pldo-reg1 �avcc_1v8_s0¬ÀÒw@êw@regulator-state-mem"pldo-reg2 �vcc_1v8_s0¬ÀÒw@êw@Ñregulator-state-mem" �w@pldo-reg3 �avdd_1v2_s0¬ÀÒO€êO€regulator-state-mem"pldo-reg4 �vcc_3v3_s0¬ÀÒ2Z ê2Z regulator-state-mem"pldo-reg5 �vccio_sd_s0¬ÀÒw@ê2Z regulator-state-mem"pldo-reg6 �pldo6_s3¬ÀÒw@êw@regulator-state-mem � �w@nldo-reg1 �vdd_0v75_s3¬ÀÒ q°ê q°regulator-state-mem � � q°nldo-reg2�vdd_ddr_pll_s0¬ÀÒ øPê øPregulator-state-mem" � øPnldo-reg3 �avdd_0v75_s0¬ÀÒ Ç|ê Ç|regulator-state-mem"nldo-reg4 �vdd_0v85_s0¬ÀÒ øPê øPregulator-state-mem"nldo-reg5 �vdd_0v75_s0¬ÀÒ q°ê q°regulator-state-mem"spi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiþ³ÒI+š•spiclkapb_pclk;““@txrxQ h±²³rdefault+ 8disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartþ´ÒL+«Ÿbaudclkapb_pclk;-- @txrxh´rdefaultTJ 8disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartþµÒM+¯ baudclkapb_pclk;- - @txrxhµrdefaultTJ8okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartþ¶ÒN+³¡baudclkapb_pclk;- - @txrxh¶rdefaultTJ 8disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartþ·ÒO+·¢baudclkapb_pclk;“ “ @txrxh·rdefaultTJ 8disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartþ¸ÒP+»£baudclkapb_pclk;“ “ @txrxh¸rdefaultTJ 8disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartþ¹ÒQ+¿¤baudclkapb_pclk;“ “@txrxh¹rdefaultTJ 8disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartþºÒR+Ã¥baudclkapb_pclk;ll@txrxhºrdefaultTJ 8disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartþ»ÒS+Ǧbaudclkapb_pclk;l l @txrxh»rdefaultTJ 8disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartþ¼ÒT+˧baudclkapb_pclk;l l @txrxh¼rdefaultTJ 8disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½+LK pwmpclkh½rdefaulta 8disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½+LK pwmpclkh¾rdefaulta 8disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½ +LK pwmpclkh¿rdefaulta 8disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½0+LK pwmpclkhÀrdefaulta 8disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾+ON pwmpclkhÁrdefaulta 8disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾+ON pwmpclkhÂrdefaulta 8disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾ +ON pwmpclkhÃrdefaulta 8disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾0+ON pwmpclkhÄrdefaulta 8disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿+RQ pwmpclkhÅrdefaulta 8disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿+RQ pwmpclkhÆrdefaulta 8disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿ +RQ pwmpclkhÇrdefaulta 8disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿0+RQ pwmpclkhÈrdefaulta 8disabledthermal-zonespackage-thermal µ Ë ÙÉtripspackage-crit éÁ8 õ criticalbigcore0-thermal µd Ë ÙÉtripsbigcore0-alert éL õÐpassiveÊbigcore0-crit éÁ8 õ criticalcooling-mapsmap0 Ê ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿbigcore2-thermal µd Ë ÙÉtripsbigcore2-alert éL õÐpassiveËbigcore2-crit éÁ8 õ criticalcooling-mapsmap0 Ë ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿlittlecore-thermal µd Ë ÙÉtripslittlecore-alert éL õÐpassiveÌlittlecore-crit éÁ8 õ criticalcooling-mapsmap0 Ì0 ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcenter-thermal µ Ë ÙÉtripscenter-crit éÁ8 õ criticalgpu-thermal µd Ë ÙÉtripsgpu-alert éL õÐpassiveÍgpu-crit éÁ8 õ criticalcooling-mapsmap0 Í Îÿÿÿÿÿÿÿÿnpu-thermal µ Ë ÙÉtripsnpu-crit éÁ8 õ criticaltsadc@fec00000rockchip,rk3588-tsadcþÀÒ�+ž�tsadcapb_pclk2žB„€_VW9tsadc-apbtsadc ÔÀ + BhÏ ]Ðrdefaultsleep g8okayÉadc@fec10000rockchip,rk3588-saradcþÁÒŽ }+‘�saradcapb_pclk_U 9saradc-apb8okay �Ñi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2cþÈ+ˆ€ i2cpclkÒChÒrdefault+ 8disabledi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2cþÉ+‰� i2cpclkÒDhÓrdefault+ 8disabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2cþÊ+Š‚ i2cpclkÒEhÔrdefault+ 8disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiþËÒJ+›–spiclkapb_pclk;l l@txrxQ hÕÖ×rdefault+ 8disabledefuse@fecc0000rockchip,rk3588-otpþÌ +Œ‹��otpapb_pclkphyarb_§¦¨ 9otpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c ›npu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecellþÑ@ ÒZ[!+p apb_pclk8lphy@fed60000rockchip,rk3588-hdptx-phyþÖ + TrefapbE8_#cde!""9phyapbinitcmnlaneroplllcpll[Ø 8disabledphy@fed80000rockchip,rk3588-usbdp-phyþØE+¡lVÙrefclkimmortalpclkutmi(_   9initcmnlanepcs_apbpma_apb  Ú ³Û ÄÜ ÚÝ 8disabled#phy@fee00000rockchip,rk3588-naneng-combphyþà+¨vW refapbpipe2¨BõáE_<C9phyapb ê* üÞ8okayqphy@fee20000rockchip,rk3588-naneng-combphyþâ+ªxW refapbpipe2ªBõáE_>E9phyapb ê* üß8okay(sram@ff001000 mmio-sramÿðÿð+pinctrlrockchip,rk3588-pinctrl[à+ágpio@fd8a0000rockchip,gpio-bankýŠÒ+qrX á ]hùžgpio@fec20000rockchip,gpio-bankþÂÒ+stX á ]hùgpio@fec30000rockchip,gpio-bankþÃÒ+uvX á@ ]hùgpio@fec40000rockchip,gpio-bankþÄÒ+wxX á` ]hùgpio@fec50000rockchip,gpio-bankþÅÒ+yzX ဠ]hùûpcfg-pull-up æpcfg-pull-down +äpcfg-pull-none :âpcfg-pull-none-drv-level-2 : Gèpcfg-pull-up-drv-level-1  Gçpcfg-pull-up-drv-level-2  Gãpcfg-pull-none-smt : Våauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout kâzemmc-bus8€ kãããããããã{emmc-clk kã|emmc-cmd kã}emmc-data-strobe kä~eth1fspigmac1gpuhdmii2c0i2c0m2-xfer kåå+i2c1i2c1m0-xfer k å åœi2c2i2c2m0-xfer k å å�i2c3i2c3m0-xfer k å å i2c4i2c4m0-xfer k å å¡i2c5i2c5m0-xfer k å å¢i2c6i2c6m0-xfer k å åÒi2c7i2c7m0-xfer k å åÓi2c8i2c8m0-xfer k å åÔi2s0i2s0-lrck kâi2s0-sclk kâ€i2s0-sdi0 kâ�i2s0-sdi1 kâ‚i2s0-sdi2 kâƒi2s0-sdi3 kâ„i2s0-sdo0 kâ…i2s0-sdo1 kâ†i2s0-sdo2 kâ‡i2s0-sdo3 kâˆi2s1i2s1m0-lrck kâ‰i2s1m0-sclk kâŠi2s1m0-sdi0 kâ‹i2s1m0-sdi1 kâŒi2s1m0-sdi2 kâ�i2s1m0-sdi3 kâŽi2s1m0-sdo0 k â�i2s1m0-sdo1 k â�i2s1m0-sdo2 k â‘i2s1m0-sdo3 k â’i2s2i2s2m1-lrck kâ”i2s2m1-sclk k â•i2s2m1-sdi k â–i2s2m1-sdo k â—i2s3i2s3-lrck kâ˜i2s3-sclk kâ™i2s3-sdi kâši2s3-sdo kâ›jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp kæââââââ«pmupwm0pwm0m0-pins kâ/pwm1pwm1m0-pins kâ0pwm2pwm2m0-pins kâ1pwm3pwm3m0-pins kâ2pwm4pwm4m0-pins k â½pwm5pwm5m0-pins k â¾pwm6pwm6m0-pins k â¿pwm7pwm7m0-pins k âÀpwm8pwm8m0-pins k âÁpwm9pwm9m0-pins k âÂpwm10pwm10m0-pins k âÃpwm11pwm11m0-pins k âÄpwm12pwm12m0-pins k âÅpwm13pwm13m0-pins k âÆpwm14pwm14m0-pins k âÇpwm15pwm15m0-pins k âÈrefclksatasata0sata1sata2sdiosdiom1-pins` kâæææææysdmmcsdmmc-bus4@ kããããxsdmmc-clk kãusdmmc-cmd kãvsdmmc-det kæwspdif0spdif1spi0spi0m0-pins0 kççç¥spi0m0-cs0 kç£spi0m0-cs1 kç¤spi1spi1m1-pins0 kççç¨spi1m1-cs0 kç¦spi1m1-cs1 kç§spi2spi2m2-pins0 kç ççªspi2m2-cs0 k ç©spi3spi3m1-pins0 kç çç³spi3m1-cs0 kç±spi3m1-cs1 kç²spi4spi4m0-pins0 kççç×spi4m0-cs0 kçÕspi4m0-cs1 kçÖtsadctsadc-shut-org kâÏuart0uart0m1-xfer kæ æ.uart1uart1m1-xfer k æ æ´uart2uart2m0-xfer k æ æµuart3uart3m1-xfer k æ æ¶uart4uart4m1-xfer k æ æ·uart5uart5m1-xfer k æ æ¸uart6uart6m1-xfer k æ æ¹uart7uart7m1-xfer k æ æºuart8uart8m1-xfer k æ æ»uart9uart9m1-xfer k æ æ¼vopbt656gpio-functsadc-gpio-func kâÐeth0gmac0gmac0-miim kââõgmac0-rx-bus20 kâââ÷gmac0-tx-bus20 kâââögmac0-rgmii-clk kâ âøgmac0-rgmii-bus@ kââ â âùrtl8211frtl8211f-rst k âúhym8563hym8563-int kæŸusbvcc5v0-host-en kâusb@fc400000rockchip,rk3588-dwc3snps,dwc3ü@@ÒÝ+—–•ref_clksuspend_clkbus_clk?otg GéêLusb2-phyusb3-phy Vutmi_wide* _Sf®Ïð 8disabledsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsysconý[€syscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsysconý\ÿsyscon@fd5cc000$rockchip,rk3588-usbdpphy-grfsysconý\À@þsyscon@fd5d4000.rockchip,rk3588-usb2phy-grfsysconsimple-mfdý]@@+ýusb2phy@4000rockchip,rk3588-usb2phy@¸+ phyclk íusb480m_phy1ÒŠ_n9phyapb 8disabledüotg-portE 8disabledéi2s@fddc8000rockchip,rk3588-i2s-tdmýÜ€Ò¼+ññîmclk_txmclk_rxhclk2ïÇ;l@tx* _º9tx-mÞ 8disabledi2s@fddf4000rockchip,rk3588-i2s-tdmýß@Òº+99?mclk_txmclk_rxhclk26Ç;l@tx* _Ú9tx-mÞ 8disabledi2s@fddf8000rockchip,rk3588-i2s-tdmý߀Ò»+++'mclk_txmclk_rxhclk2(Ç;l@rx* _Ç9rx-mÞ 8disabledi2s@fde00000rockchip,rk3588-i2s-tdmýàÒ¾+&&"mclk_txmclk_rxhclk2#Ç;l@rx* _î9rx-mÞ 8disabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+ï0+@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipeúpciPÒsyspmcmsglegacyerrù `ëëëë+<KìSGí Lpcie-phy* "Tððð ð à @0 @@þðŽdbiapbconfig_&+ 9pwrpipe 8disabledlegacy-interrupt-controller]ù Òëpcie-ep@fe150000rockchip,rk3588-pcie-epP @ @þ @ @0Ždbidbi2apbaddr_spaceatu0+@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipe�Ò +syspmcmsglegacyerrdma0dma1dma2dma3<SGí Lpcie-phy* "_&+ 9pwrpipe 8disabledpcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+ï0+AF<KPu)aclk_mstaclk_slvaclk_dbipclkauxpipeúpciPÒÿþsyspmcmsglegacyerrù `îîîî+<KìSGí Lpcie-phy* "Tñññ ñ à @ @@0 @@@þñŽdbiapbconfig_', 9pwrpipe 8disabledlegacy-interrupt-controller]ù Òÿîpcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcieï /0+BG=LQ¯)aclk_mstaclk_slvaclk_dbipclkauxpipeúpciPÒóòñðïsyspmcmsglegacyerrù `ïïïï+<K o SGð Lpcie-phy* "Tòòò ò à € €@0 @€@þòŽdbiapbconfig_(- 9pwrpipe+ 8disabledlegacy-interrupt-controller]ù Òðïethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20aþ Òãâmacirqeth_wake_irq(+67X]40stmmacethclk_mac_refpclk_macaclk_macptp_ref* !_# 9stmmaceth[hr*ƒñ“¤ò·óÊ8okay youtput †ô ‘rgmii-rxidhõö÷øùrdefault š £Cmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-id001c.c916rdefaulthú ¬N  ¼†  Îû ôstmmac-axi-configÓÝíñrx-queues-configýòqueue0queue1tx-queues-configóqueue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahciþ"Ò(+c`fUpsatapmaliverxoobrefasic)+ 8disabledsata-port@0;@Gð Lsata-phyH W phy@fed90000rockchip,rk3588-usbdp-phyþÙE+¡mWürefclkimmortalpclkutmi(_9initcmnlanepcs_apbpma_apb  ý ³Û Äþ ÚÝ 8disabledêphy@fee10000rockchip,rk3588-naneng-combphyþá+©wW refapbpipe2©BõáE_=D9phyapb ê* üÿ 8disabledðphy@fee80000rockchip,rk3588-pcie3-phyþèE+ypclk_H9phy ê* Ú 8disabledíopp-table-cluster0operating-points-v2 ë opp-1008000000 ö<Ü ý L¸ L¸~ð œ@opp-1200000000 öG†Œ ý ß4 ß4~ð œ@opp-1416000000 öTfr ý ¢„ ¢„~ð œ@ opp-1608000000 ö_Ø" ý øP øP~ð œ@opp-1800000000 ökIÒ ý~ð~ð~ð œ@opp-table-cluster1operating-points-v2 ëopp-1200000000 öG†Œ ý L¸ L¸B@ œ@opp-1416000000 öTfr ý  B@ œ@opp-1608000000 ö_Ø" ý ¢„ ¢„B@ œ@opp-1800000000 ökIÒ ý øP øPB@ œ@opp-2016000000 öx)¸ ýHHB@ œ@opp-2208000000 öƒ›h ýllB@ œ@opp-2400000000 ö�  ýB@B@B@ œ@opp-table-cluster2operating-points-v2 ëopp-1200000000 öG†Œ ý L¸ L¸B@ œ@opp-1416000000 öTfr ý  B@ œ@opp-1608000000 ö_Ø" ý ¢„ ¢„B@ œ@opp-1800000000 ökIÒ ý øP øPB@ œ@opp-2016000000 öx)¸ ýHHB@ œ@opp-2208000000 öƒ›h ýllB@ œ@opp-2400000000 ö�  ýB@B@B@ œ@opp-table-gpuoperating-points-v2!opp-300000000 öᣠý L¸ L¸ øPopp-400000000 öׄ ý L¸ L¸ øPopp-500000000 öÍe ý L¸ L¸ øPopp-600000000 ö#ÃF ý L¸ L¸ øPopp-700000000 ö)¹' ý ®` ®` øPopp-800000000 ö/¯ ý q° q° øPopp-900000000 ö5¤é ý 5 5 øPopp-1000000000 ö;šÊ ý øP øP øPchosen (serial2:1500000n8adc-keys adc-keys 4 @buttons Qw@ kdbutton-vol-up yVolume Up s ŠBhbutton-vol-down yVolume Down r Š\èbutton-menu yMenu ‹ Š ”�button-escape yEscape  ŠØ8backlightpwm-backlight ¤ ±a¨pcie20-avdd0v85-regulatorregulator-fixed�pcie20_avdd0v85¬ÀÒ øPê øPpcie20-avdd1v8-regulatorregulator-fixed�pcie20_avdd1v8¬ÀÒw@êw@pcie30-avdd0v75-regulatorregulator-fixed�pcie30_avdd0v75¬ÀÒ q°ê q°pcie30-avdd1v8-regulatorregulator-fixed�pcie30_avdd1v8¬ÀÒw@êw@vcc12v-dcin-regulatorregulator-fixed �vcc12v_dcin¬ÀÒ·ê·vcc5v0-host-regulatorregulator-fixed ¶ Éûrdefaulth �vcc5v0_hostÀ¬ÒLK@êLK@)vcc5v0-sys-regulatorregulator-fixed �vcc5v0_sys¬ÀÒLK@êLK@,vcc5v0-usbdcin-regulatorregulator-fixed�vcc5v0_usbdcin¬ÀÒLK@êLK@ vcc5v0-usb-regulatorregulator-fixed �vcc5v0_usb¬ÀÒLK@êLK@ vcc-1v1-nldo-s3-regulatorregulator-fixed�vcc_1v1_nldo_s3¬ÀÒÈàêÈà,° compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4mmc0cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesno-mapclock-namespower-domainsstatusdr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosiommusreg-namesrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthmmc-hs400-1_8vmmc-hs400-enhanced-strobeno-sdiono-sdnon-removablerockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellswakeup-sourcenum-csgpio-controller#gpio-cellsspi-max-frequencysystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplypinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplybitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsclock_in_outphy-handlephy-moderx_delaytx_delayreset-assert-usreset-deassert-usreset-gpiosrockchip,phy-grfopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltpower-supplypwmsenable-active-highgpio