Ð þíõ´8é�( $éX ,radxa,rock-3brockchip,rk35687Radxa ROCK 3Baliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/ethernet@fe2a0000ç/ethernet@fe010000ñ/mmc@fe310000ö/mmc@fe2b0000û/mmc@fe000000cpus cpu@0cpu,arm,cortex-a55 &psci4H€U@g€t€�@“€ ±¼ cpu@100cpu,arm,cortex-a55 &psci4H€U@g€t€�@“€ ±¼ cpu@200cpu,arm,cortex-a55 &psci4H€U@g€t€�@“€ ±¼ cpu@300cpu,arm,cortex-a55 &psci4H€U@g€t€�@“€ ±¼ l3-cache,cacheÄÐJW@i¼opp-table-0,operating-points-v2Þ¼opp-408000000éQ– ð »  » Œ0þœ@opp-600000000é#ÃF ð »  » Œ0opp-816000000é0£, ð »  » Œ0opp-1104000000éAÍ´ ð »  » Œ0opp-1416000000éTfr ð »  » Œ0opp-1608000000é_Ø" ðà˜à˜Œ0opp-1800000000ékIÒ ð��Œ0opp-1992000000év»‚ ðŒ0Œ0Œ0display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc!‚, protocol@14 2¼opp-table-1,operating-points-v2¼Gopp-200000000é ë ð øP øPB@opp-300000000éᣠð øP øPB@opp-400000000éׄ ð øP øPB@opp-600000000é#ÃF ð »  » B@opp-700000000é)¹' ð~ð~ðB@opp-800000000é/¯ ðB@B@B@hdmi-sound,simple-audio-card?HDMIVi2so‰okaysimple-audio-card,codec�simple-audio-card,cpu� pmu,arm,cortex-a55-pmu0šäåæç¥ psci ,arm,psci-1.0-smctimer,arm,armv8-timer0š   ¸xin24m ,fixed-clockÏn6ßxin24m2¼xin32k ,fixed-clockÏ€ßxin32kòüdefault2sram@10f000 ,mmio-sram ð  ðsram@0,arm,scmi-shmem ¼sata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci ü@›œ�satapmaliverxoob š_ "sata-phy,> ‰disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci ü€ ¡¢satapmaliverxoob š` "sata-phy,> ‰disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3 üÀ@ 𩦧¥ref_clksuspend_clkbus_clkLotg Tutmi_wide>]”d‰okay "usb2-phyusb3-phy}usb@fd000000,rockchip,rk3568-dwc3snps,dwc3 ý@ šª©ª¨ref_clksuspend_clkbus_clkLhost "usb2-phyusb3-phy Tutmi_wide>]•d‰okayinterrupt-controller@fd400000 ,arm,gic-v3  ý@ýF š „™ªýA´(¿¼usb@fd800000 ,generic-ehci ý€ š‚½¾¼"usb‰okayusb@fd840000 ,generic-ohci ý„ šƒ½¾¼"usb‰okayusb@fd880000 ,generic-ehci ýˆ š…¿À¼"usb ‰disabledusb@fd8c0000 ,generic-ohci ýŒ š†¿À¼"usb ‰disabledsyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfd ý¼fio-domains&,rockchip,rk3568-pmu-io-voltage-domain‰okayÎÜêø"0>syscon@fdc50000 ýÅ ,rockchip,rk3568-pipe-grfsyscon¼³syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfd ýƼ syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsyscon ýȼ´syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsyscon ýɼµsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsyscon ýÊ€¼¶syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsyscon ýÊ€€¼¹clock-controller@fdd00000,rockchip,rk3568-pmucru ýÐ2L¼clock-controller@fdd20000,rockchip,rk3568-cru ýÒxin24m2LY i€G†Œ ëÂ~• ¼i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c ýÔ š.- i2cpclkò!üdefault ‰okayregulator@1c ,tcs,tcs4525 ¢¿vdd_cpuÎâô 5 Œ0$ü9"¼regulator-state-memDpmic@20,rockchip,rk809 YH~–2Hmclkßrk809-clkout1rk809-clkout2#šüdefaultò$%]n†”& &¬&¸&Ä&Ð&Ü&è&ô&¼ÝregulatorsDCDC_REG1 ¿vdd_logicÎâô¡  ™p$qregulator-state-memDDCDC_REG2¿vdd_gpuÎâô¡  ™p$q¼Hregulator-state-memDDCDC_REG3¿vcc_ddrÎâregulator-state-memDCDC_REG4¿vdd_npuô¡  ™p$qregulator-state-memDDCDC_REG5¿vcc_1v8Îâôw@ w@¼regulator-state-memDLDO_REG1¿vdda0v9_imageô »  » ¼bregulator-state-memDLDO_REG2 ¿vdda_0v9Îâô »  » regulator-state-memDLDO_REG3 ¿vdda0v9_pmuÎâô »  » regulator-state-mem/ » LDO_REG4 ¿vccio_acodecÎâô2Z  2Z ¼regulator-state-memDLDO_REG5 ¿vccio_sdÎâôw@ 2Z ¼regulator-state-memDLDO_REG6 ¿vcc3v3_pmuÎâô2Z  2Z ¼regulator-state-mem/2Z LDO_REG7 ¿vcca_1v8Îâôw@ w@¼¦regulator-state-memDLDO_REG8 ¿vcca1v8_pmuÎâôw@ w@regulator-state-mem/w@LDO_REG9¿vcca1v8_imageôw@ w@¼cregulator-state-memDSWITCH_REG1¿vcc_3v3Îâ¼regulator-state-memDSWITCH_REG2 ¿vcc3v3_sdÎâ¼mregulator-state-memDserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart ýÕ št ,baudclkapb_pclkK''ò(üdefaultP] ‰disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm ý× 0 pwmpclkò)üdefaultg ‰disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm ý× 0 pwmpclkò*üdefaultg ‰disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm ý×  0 pwmpclkò+üdefaultg ‰disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm ý×0 0 pwmpclkò,üdefaultg ‰disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfd ýÙpower-controller!,rockchip,rk3568-power-controllerr ¼power-domain@7 †-rpower-domain@8 ÌÍ †./0rpower-domain@9 ÚÛÜ †123rpower-domain@10 ñò†456789rpower-domain@11 í†:rpower-domain@13 †;rpower-domain@14  †<=>rpower-domain@15  †?@ABCDEFrgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost ýæ@$š()' �jobmmugpugpubus4G>‰okay�H¼£video-codec@fdea0400,rockchip,rk3568-vpu ýê š‹�vdpuîï aclkhclk©I> iommu@fdea0800,rockchip,rk3568-iommu ýê@ šŠ aclkifaceîï> °¼Irga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga ýë€ šZóôõaclkhclksclk]&$% ½coreaxiahb> video-codec@fdee0000,rockchip,rk3568-vepu ýî š@ýþ aclkhclk©J> iommu@fdee0800,rockchip,rk3568-iommu ýî@ š?ýþ aclkiface> °¼Jmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc þ@ šd ÁÂŽ�biuciuciu-driveciu-sampleÉÔðÑ€]ë½reset ‰disabledâìý  K+üdefault òLMN9GOSethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20a þš �macirqeth_wake_irq@†‰‰ÇÃĉÈWstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref]ì ½stmmaceth• `Pp�Q”R§‰okayY‰†~‡Å°input½S Èrgmii-idÑüdefaultòTUVWXYmdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22 ÜN ìÃP þZ¼Sstmmac-axi-config $¼Prx-queues-config4¼Qqueue0tx-queues-configJ¼Rqueue0vop@fe040000  þ0þ@`vopgamma-lut š”(ÝÞßàá%aclkhclkdclk_vp0dclk_vp1dclk_vp2©[> • ‰okay,rockchip,rk3568-vopYßà~ports ¼port@0  endpoint@2 j\¼dport@1  port@2  iommu@fe043e00,rockchip,rk3568-iommu  þ>þ? š”ÝÞ aclkiface°> ‰okay¼[dsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi þ šDpclkè"dphy]> ½apb]•  ‰disabledports port@0 port@1 dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi þ šEpclké"dphy^> ½apb]•  ‰disabledports port@0 port@1 hdmi@fe0a0000,rockchip,rk3568-dw-hdmi þ  š-(æç“(Úiahbisfrcecrefüdefault ò_`a> P• ]‰okayzbŠc¼ports port@0 endpointjd¼\port@1 endpointje¼×qos@fe128000,rockchip,rk3568-qossyscon þ€ ¼-qos@fe138080,rockchip,rk3568-qossyscon þ€€ ¼<qos@fe138100,rockchip,rk3568-qossyscon þ� ¼=qos@fe138180,rockchip,rk3568-qossyscon þ�€ ¼>qos@fe148000,rockchip,rk3568-qossyscon þ€ ¼.qos@fe148080,rockchip,rk3568-qossyscon þ€€ ¼/qos@fe148100,rockchip,rk3568-qossyscon þ� ¼0qos@fe150000,rockchip,rk3568-qossyscon þ ¼:qos@fe158000,rockchip,rk3568-qossyscon þ€ ¼4qos@fe158100,rockchip,rk3568-qossyscon þ� ¼5qos@fe158180,rockchip,rk3568-qossyscon þ�€ ¼6qos@fe158200,rockchip,rk3568-qossyscon þ‚ ¼7qos@fe158280,rockchip,rk3568-qossyscon þ‚€ ¼8qos@fe158300,rockchip,rk3568-qossyscon þƒ ¼9qos@fe180000,rockchip,rk3568-qossyscon þ qos@fe190000,rockchip,rk3568-qossyscon þ ¼?qos@fe190280,rockchip,rk3568-qossyscon þ€ ¼Cqos@fe190300,rockchip,rk3568-qossyscon þ ¼Dqos@fe190380,rockchip,rk3568-qossyscon þ€ ¼Eqos@fe190400,rockchip,rk3568-qossyscon þ ¼Fqos@fe198000,rockchip,rk3568-qossyscon þ€ ¼;qos@fe1a8000,rockchip,rk3568-qossyscon þ€ ¼1qos@fe1a8080,rockchip,rk3568-qossyscon þ€€ ¼2qos@fe1a8100,rockchip,rk3568-qossyscon þ� ¼3dfi@fe230000,rockchip,rk3568-dfi þ# š šfpcie@fe260000,rockchip,rk3568-pcie0 À@þ&ô`dbiapbconfig<šKJIHG�syspmcmsglegacyerr§(�‚ƒ„…$aclk_mstaclk_slvaclk_dbipclkauxpci™±`ÄggggÒãò    "pcie-phy>T ôôô ô à@]¡½pipe ‰okayüdefaultòh þZ "Olegacy-interrupt-controller™„ šH¼gmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc þ+@ šb °±Š‹biuciuciu-driveciu-sampleÉÔðÑ€]Ô½reset‰okayâì 2üdefaultòijklGmSmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc þ,@ šc ²³Œ�biuciuciu-driveciu-sampleÉÔðÑ€]Ö½reset ‰disabledspi@fe300000 ,rockchip,sfc þ0@ šexvclk_sfchclk_sfcònüdefault‰okay flash@0,jedec,spi-nor  =2ê O `mmc@fe310000,rockchip,rk3568-dwcmshc þ1 šY{}i ëÂn6(|zy{}corebusaxiblocktimer‰okayâ qÔ ë ƒ+üdefaultòopqrGSrng@fe388000,rockchip,rk3568-rng þ8€@po coreahb]m‰okayi2s@fe400000,rockchip,rk3568-i2s-tdm þ@ š4Y=AiFÏqFÏq?C9mclk_txmclk_rxhclkKs ’tx]PQ ½tx-mrx-m• ]‰okay¼ i2s@fe410000,rockchip,rk3568-i2s-tdm þA š5YEIiFÏqFÏqGK:mclk_txmclk_rxhclkKss ’rxtx]RS ½tx-mrx-m• üdefaultòtuvw]‰okay œ¼ßi2s@fe420000,rockchip,rk3568-i2s-tdm þB š6YMiFÏqOO;mclk_txmclk_rxhclkKss ’txrx]T½tx-m• üdefaultòxyz{] ‰disabledi2s@fe430000,rockchip,rk3568-i2s-tdm þC š7SW<mclk_txmclk_rxhclkKss ’txrx]UV ½tx-mrx-m• ] ‰disabledpdm@fe440000,rockchip,rk3568-pdm þD šLZYpdm_clkpdm_hclkKs  ’rxò|}~€�üdefault]X½pdm-m] ‰disabledspdif@fe460000,rockchip,rk3568-spdif þF šf mclkhclk_\Ks ’txüdefaultò‚] ‰disableddma-controller@fe530000,arm,pl330arm,primecell þS@š  ·  apb_pclk μ'dma-controller@fe550000,arm,pl330arm,primecell þU@š ·  apb_pclk μsi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2c þZ š/HG i2cpclkòƒüdefault  ‰disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c þ[ š0JI i2cpclkò„üdefault  ‰disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c þ\ š1LK i2cpclkò…üdefault  ‰disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c þ] š2NM i2cpclkò†üdefault  ‰disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c þ^ š3PO i2cpclkò‡üdefault ‰okayrtc@51,haoyu,hym8563 Q#š2 ßrtcic_32koutüdefaultòˆ†watchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt þ` š• tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spi þa šgRQspiclkapb_pclkK'' ’txrxüdefault ò‰Š‹  ‰disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spi þb šhTSspiclkapb_pclkK'' ’txrxüdefault òŒ�Ž  ‰disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spi þc šiVUspiclkapb_pclkK'' ’txrxüdefault ò��‘  ‰disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spi þd šjXWspiclkapb_pclkK'' ’txrxüdefault ò’“”  ‰disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uart þe šubaudclkapb_pclkK''ò•üdefaultP] ‰disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uart þf šv# baudclkapb_pclkK''ò–üdefaultP]‰okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uart þg šw'$baudclkapb_pclkK''ò—üdefaultP] ‰disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uart þh šx+(baudclkapb_pclkK'' ò˜üdefaultP] ‰disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uart þi šy/,baudclkapb_pclkK' ' ò™üdefaultP] ‰disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uart þj šz30baudclkapb_pclkK' ' òšüdefaultP] ‰disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uart þk š{74baudclkapb_pclkK''ò›üdefaultP] ‰disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uart þl š|;8baudclkapb_pclkK'' òœ�žüdefaultP] ‰disabled Ùserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uart þm š}?<baudclkapb_pclkK''òŸüdefaultP] ‰disabledthermal-zonescpu-thermal éd ÿè  tripscpu_alert0 p )Ðpassive¼¡cpu_alert1 $ø )Ðpassivecpu_crit s )Ð criticalcooling-mapsmap0 4¡0 9 ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal é ÿè  tripsgpu-threshold p )Ðpassivegpu-target $ø )Ðpassive¼¢gpu-crit s )Ð criticalcooling-mapsmap0 4¢ 9£ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadc þq šsYif@ ®`tsadcapb_pclk]�‚ו  Hsüdefaultsleepò¤ _¥ i‰okay  –¼ saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradc þr š]saradcapb_pclk]€ ½saradc-apb ±‰okay æpwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwm þnZY pwmpclkò§üdefaultg ‰disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwm þnZY pwmpclkò¨üdefaultg ‰disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwm þn ZY pwmpclkò©üdefaultg ‰disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwm þn0ZY pwmpclkòªüdefaultg ‰disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwm þo]\ pwmpclkò«üdefaultg ‰disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwm þo]\ pwmpclkò¬üdefaultg ‰disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwm þo ]\ pwmpclkò­üdefaultg ‰disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwm þo0]\ pwmpclkò®üdefaultg ‰disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwm þp`_ pwmpclkò¯üdefaultg ‰disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwm þp`_ pwmpclkò°üdefaultg ‰disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwm þp `_ pwmpclkò±üdefaultg ‰disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwm þp0`_ pwmpclkò²üdefaultg ‰disabledphy@fe830000,rockchip,rk3568-naneng-combphy þƒ"} refapbpipeY"iõá]ǽphy ϳ á´ ÷‰okay¼phy@fe840000,rockchip,rk3568-naneng-combphy þ„%~ refapbpipeY%iõá]ɽphy ϳ áµ ÷‰okay¼phy@fe870000,rockchip,rk3568-csi-dphy þ‡ypclk ÷]º½apb•  ‰disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy þ… refpclkz ÷> ½apb]» ‰disabled¼]mipi-dphy@fe860000,rockchip,rk3568-dsi-dphy þ† refpclk{ ÷> ½apb]¼ ‰disabled¼^usb2phy@fe8a0000,rockchip,rk3568-usb2phy þŠphyclkßclk_usbphy0_480m š‡ ¶2‰okay¼host-port ÷‰okayÑ·¼otg-port ÷‰okayѸ¼usb2phy@fe8b0000,rockchip,rk3568-usb2phy þ‹phyclkßclk_usbphy1_480m šˆ ¹2‰okayhost-port ÷ ‰disabled¼otg-port ÷‰okayÑ·¼pinctrl,rockchip,rk3568-pinctrl• šf  ¼ºgpio@fdd60000,rockchip,gpio-bank ýÖ š!.   "º  .„™¼#gpio@fe740000,rockchip,gpio-bank þt š"cd  "º  .„™gpio@fe750000,rockchip,gpio-bank þu š#ef  "º@  .„™¼Ègpio@fe760000,rockchip,gpio-bank þv š$gh  "º`  .„™¼Zgpio@fe770000,rockchip,gpio-bank þw š%ij  "º€  .„™pcfg-pull-up :¼½pcfg-pull-none G¼»pcfg-pull-none-drv-level-1 G T¼¿pcfg-pull-none-drv-level-2 G T¼¾pcfg-pull-none-drv-level-3 G T¼Âpcfg-pull-up-drv-level-1 : T¼Ápcfg-pull-up-drv-level-2 : T¼¼pcfg-pull-none-smt G c¼Àacodecaudiopwmbt656bt1120camcan0can0m0-pins x » »¼Ócan1can1m0-pins x»»¼Ôcan2can2m0-pins x » »¼Õcifclk32kclk32k-out0 x»¼cpuebcedpdpemmcemmc-bus8€ x ¼ ¼¼¼¼¼¼¼¼oemmc-clk x¼¼pemmc-cmd x¼¼qemmc-datastrobe x»¼reth0eth1flashfspifspi-pins` x»»»»»»¼ngmac0gmac0-miim x»»¼Ígmac0-clkinout x»¼Ògmac0-rx-bus20 x»»»¼Ïgmac0-tx-bus20 x ¾ ¾ »¼Îgmac0-rgmii-clk x»¿¼Ðgmac0-rgmii-bus@ x»»¾¾¼Ñgmac1gmac1m1-miim x»»¼Tgmac1m1-clkinout x»¼Ygmac1m1-rx-bus20 x»» »¼Vgmac1m1-tx-bus20 x¾¾»¼Ugmac1m1-rgmii-clk x»¿¼Wgmac1m1-rgmii-bus@ x»»¾¾¼Xgpuhdmitxhdmitxm0-cec x»¼ahdmitx-scl x»¼_hdmitx-sda x»¼`i2c0i2c0-xfer x À À¼!i2c1i2c1-xfer x À À¼ƒi2c2i2c2m0-xfer x ÀÀ¼„i2c3i2c3m0-xfer xÀÀ¼…i2c4i2c4m0-xfer x À À¼†i2c5i2c5m0-xfer x À À¼‡i2s1i2s1m0-lrcktx x»¼ui2s1m0-mclk x»¼%i2s1m0-sclktx x»¼ti2s1m0-sdi0 x »¼vi2s1m0-sdo0 x»¼wi2s2i2s2m0-lrcktx x»¼yi2s2m0-sclktx x»¼xi2s2m0-sdi x»¼zi2s2m0-sdo x»¼{i2s3ispjtaglcdcmcunpupcie20pcie20m1-pins0 x»»»¼hpcie30x1pcie30x2pcie30x2m1-pins0 x»»»¼Çpdmpdmm0-clk x»¼|pdmm0-clk1 x»¼}pdmm0-sdi0 x »¼~pdmm0-sdi1 x »¼pdmm0-sdi2 x »¼€pdmm0-sdi3 x»¼�pmicpmic-int-l x½¼$pmupwm0pwm0m0-pins x»¼)pwm1pwm1m0-pins x»¼*pwm2pwm2m0-pins x»¼+pwm3pwm3-pins x»¼,pwm4pwm4-pins x»¼§pwm5pwm5-pins x»¼¨pwm6pwm6-pins x»¼©pwm7pwm7-pins x»¼ªpwm8pwm8m0-pins x »¼«pwm9pwm9m0-pins x »¼¬pwm10pwm10m0-pins x »¼­pwm11pwm11m0-pins x»¼®pwm12pwm12m0-pins x»¼¯pwm13pwm13m0-pins x»¼°pwm14pwm14m0-pins x»¼±pwm15pwm15m0-pins x»¼²refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ x¼¼¼¼¼isdmmc0-clk x¼¼jsdmmc0-cmd x¼¼ksdmmc0-det x½¼lsdmmc1sdmmc2sdmmc2m0-bus4@ x¼¼¼¼¼Lsdmmc2m0-clk x¼¼Msdmmc2m0-cmd x¼¼Nspdifspdifm0-tx x»¼‚spi0spi0m0-pins0 x »»»¼‹spi0m0-cs0 x»¼‰spi0m0-cs1 x»¼Šspi1spi1m0-pins0 x »»»¼Žspi1m0-cs0 x»¼Œspi1m0-cs1 x»¼�spi2spi2m0-pins0 x»»»¼‘spi2m0-cs0 x»¼�spi2m0-cs1 x»¼�spi3spi3m0-pins0 x »» »¼”spi3m0-cs0 x»¼’spi3m0-cs1 x»¼“tsadctsadc-shutorg x»¼¤tsadc-pin x»¼¥uart0uart0-xfer x½½¼(uart1uart1m0-xfer x ½ ½¼•uart2uart2m0-xfer x½½¼–uart3uart3m0-xfer x½½¼—uart4uart4m0-xfer x½½¼˜uart5uart5m0-xfer x½½¼™uart6uart6m0-xfer x½½¼šuart7uart7m0-xfer x½½¼›uart8uart8m0-xfer x½½¼œuart8m0-ctsn x »¼�uart8m0-rtsn x »¼žuart9uart9m0-xfer x½½¼Ÿvopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2bluetoothbt-reg-on-h x »bt-wake-host-h x »host-wake-bt-h x »ir-receiverpwm3-ir x»¼Øledsled x»¼Ùpciepcie-pwren-h x»¼Úrtcrtcic-int-l x½¼ˆusbusb-host-pwren-h x»¼Ûusb-otg-pwren-h x»¼Üwifiwifi-reg-on-h x»¼Þwifi-wake-host-h x»sata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci ü–—˜satapmaliverxoob š^ "sata-phy,> ‰disabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsyscon ýǼÖqos@fe190080,rockchip,rk3568-qossyscon þ€ ¼@qos@fe190100,rockchip,rk3568-qossyscon þ ¼Aqos@fe190200,rockchip,rk3568-qossyscon þ ¼Bsyscon@fdcb8000%,rockchip,rk3568-pcie3-phy-grfsyscon ýË€¼Ãphy@fe8c0000,rockchip,rk3568-pcie3-phy þŒ ÷&'wrefclk_mrefclk_npclk]¾½phy †Ã‰okay¼Åpcie@fe270000,rockchip,rk3568-pcie §(ˆ‰Š‹Œ$aclk_mstaclk_slvaclk_dbipclkauxpci<š Ÿž�œ�syspmcmsglegacyerr™±`ÄÄÄÄÄÒãò   Å "pcie-phy>0 À@@þ'òT òòò ò à@@@`dbiapbconfig]±½pipe ‰disabledlegacy-interrupt-controller„™ š�¼Äpcie@fe280000,rockchip,rk3568-pcie §(��‘’“$aclk_mstaclk_slvaclk_dbipclkauxpci<𥤣¢¡�syspmcmsglegacyerr™±`ÄÆÆÆÆÒãò    Å "pcie-phy>0 À€@þ(ðT ððð ð à€€@`dbiapbconfig]Á½pipe‰okayüdefaultòÇ þÈlegacy-interrupt-controller„™ 𢼯ethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20a þ*š�macirqeth_wake_irq@‚……¸´µ…¹Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref]× ½stmmaceth• `Ép�ʔ˧‰okayY…‚~ƒ¶°input½Ì Èrgmii-idÑüdefaultòÍÎÏÐÑÒmdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22 ÜN ìÃP þZ¼Ìstmmac-axi-config $¼Érx-queues-config4¼Êqueue0tx-queues-configJ¼Ëqueue0can@fe570000,rockchip,rk3568v2-canfd þW šA@ baudpclk]UT ½coreapbüdefaultòÓ ‰disabledcan@fe580000,rockchip,rk3568v2-canfd þX šCB baudpclk]WV ½coreapbüdefaultòÔ ‰disabledcan@fe590000,rockchip,rk3568v2-canfd þY šED baudpclk]YX ½coreapbüdefaultòÕ ‰disabledphy@fe820000,rockchip,rk3568-naneng-combphy þ‚| refapbpipeYiõá]Žphy ϳ áÖ ÷‰okay¼chosen —serial2:1500000n8hdmi-con,hdmi-connectoraportendpointj×¼eir-receiver,gpio-ir-receiver #üdefaultòØleds ,gpio-ledsüdefaultòÙled-0 £ ©on ·heartbeat # Àheartbeatregulator-3v3-vcc-pi6c-03,regulator-fixed Ö #üdefaultòÚ¿vcc3v3_pi6c_03Îâô2Z  2Z  é'9"regulator-3v3-vcc-sys,regulator-fixed ¿vcc3v3_sysÎâô2Z  2Z 9"¼&regulator-3v3-vcc-sys2,regulator-fixed ¿vcc3v3_sys2Îâô2Z  2Z 9"¼Oregulator-5v0-vcc-sys,regulator-fixed ¿vcc5v0_sysÎâôLK@ LK@¼"regulator-5v0-vcc-usb-host,regulator-fixed Ö #üdefaultòÛ¿vcc5v0_usb_hostôLK@ LK@9"¼·regulator-5v0-vcc-usb-otg,regulator-fixed Ö #üdefaultòÜ¿vcc5v0_usb_otgôLK@ LK@9"¼¸sdio-pwrseq,mmc-pwrseq-simpleÝ ext_clocküdefaultòÞ úd LK@ þZ¼Ksound,simple-audio-cardVi2s ?Analog RK809osimple-audio-card,cpu�ßsimple-audio-card,codec�Ý interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0ethernet1mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspend#sound-dai-cellssystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencybus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr104vmmc-supplyvqmmc-supplysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modephy-supplyreset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesvpcie3v3-supplydisable-wpspi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthcap-mmc-highspeedmmc-hs200-1_8vdma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfstdout-pathcolordefault-statefunctionlinux,default-triggerenable-active-highstartup-delay-uspost-power-on-delay-mspower-off-delay-us