Ð þíù}8í( uìÐ ,radxa,rock3arockchip,rk35687Radxa ROCK 3Aaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/ethernet@fe010000ç/mmc@fe310000ì/mmc@fe2b0000ñ/mmc@fe000000cpus cpu@0öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² cpu@100öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² cpu@200öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² cpu@300öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² l3-cache,cacheºÆ@M@_²opp-table-0,operating-points-v2Ô²opp-408000000ßQ– æ »  » Œ0ôœ@opp-600000000ß#ÃF æ »  » Œ0opp-816000000ß0£, æ »  » Œ0opp-1104000000ßAÍ´ æ »  » Œ0opp-1416000000ßTfr æ »  » Œ0opp-1608000000ß_Ø" æà˜à˜Œ0opp-1800000000ßkIÒ æ��Œ0opp-1992000000ßv»‚ æŒ0Œ0Œ0display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc‚" protocol@14(²opp-table-1,operating-points-v2²Gopp-200000000ß ëÂ æ øP øPB@opp-300000000ßá£ æ øP øPB@opp-400000000ßׄ æ øP øPB@opp-600000000ß#ÃF æ »  » B@opp-700000000ß)¹' æ~ð~ðB@opp-800000000ß/¯ æB@B@B@hdmi-sound,simple-audio-card5HDMILi2seokaysimple-audio-card,codec†simple-audio-card,cpu† pmu,arm,cortex-a55-pmu0�äåæç› psci ,arm,psci-1.0#smctimer,arm,armv8-timer0�   ®xin24m ,fixed-clockÅn6Õxin24m(²xin32k ,fixed-clockÅ€Õxin32kèòdefault(sram@10f000 ,mmio-sramð ðsram@0,arm,scmi-shmem²sata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü@›œ�satapmaliverxoob �_ sata-phy"4 disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü€ ¡¢satapmaliverxoob �` sata-phy"4 disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3üÀ@ �©¦§¥ref_clksuspend_clkbus_clkBotg Jutmi_wide4S”Zokay usb2-phyusb3-physusb@fd000000,rockchip,rk3568-dwc3snps,dwc3ý@ �ª©ª¨ref_clksuspend_clkbus_clkBhost usb2-phyusb3-phy Jutmi_wide4S•Zokayinterrupt-controller@fd400000 ,arm,gic-v3 ý@ýF � z� ýAª(µ²usb@fd800000 ,generic-ehciý€ �‚½¾¼usbokayusb@fd840000 ,generic-ohciý„ �ƒ½¾¼usbokayusb@fd880000 ,generic-ehciýˆ �…¿À¼usbokayusb@fd8c0000 ,generic-ohciýŒ �†¿À¼usbokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdý²gio-domains&,rockchip,rk3568-pmu-io-voltage-domainokayÄÒàîü &4syscon@fdc50000ýÅ ,rockchip,rk3568-pipe-grfsyscon²ºsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýƲ syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýȲ»syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýɲ¼syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýÊ€²½syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýÊ€€²Àclock-controller@fdd00000,rockchip,rk3568-pmucruýÐ(B²clock-controller@fdd20000,rockchip,rk3568-cruýÒxin24m(BO _€G†Œ ëÂt‹ ²i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýÔ �.- i2cpclkè!òdefault okayregulator@1c ,tcs,tcs4525˜µvdd_cpuÄØê 5Œ0ü/"²regulator-state-mem:pmic@20,rockchip,rk809 #�OHt–(mclkHòdefaultè$%St…&‘&�&©&µ&Á&Í&Ù&å&ñ²šregulatorsDCDC_REG1 µvdd_logicÄØÿê¡ ™pqregulator-state-mem:DCDC_REG2µvdd_gpuÄÿê¡ ™pq²Hregulator-state-mem:DCDC_REG3µvcc_ddrÄØÿregulator-state-memDCDC_REG4µvdd_npuÿê¡ ™pqregulator-state-mem:DCDC_REG5µvcc_1v8ÄØêw@w@²regulator-state-mem:LDO_REG1µvdda0v9_imageê »  » ²cregulator-state-mem:LDO_REG2 µvdda_0v9ÄØê »  » regulator-state-mem:LDO_REG3 µvdda0v9_pmuÄØê »  » regulator-state-mem. » LDO_REG4 µvccio_acodecÄê2Z 2Z ²regulator-state-mem:LDO_REG5 µvccio_sdêw@2Z ²regulator-state-mem:LDO_REG6 µvcc3v3_pmuÄØê2Z 2Z ²regulator-state-mem.2Z LDO_REG7 µvcca_1v8ÄØêw@w@²­regulator-state-mem:LDO_REG8 µvcca1v8_pmuÄØêw@w@regulator-state-mem.w@LDO_REG9µvcca1v8_imageêw@w@²dregulator-state-mem:SWITCH_REG1µvcc_3v3ÄØ²regulator-state-mem:SWITCH_REG2 µvcc3v3_sd²oregulator-state-mem:serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýÕ �t ,baudclkapb_pclkJ''è(òdefaultO\ disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý× 0 pwmpclkè)òdefaultf disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý× 0 pwmpclkè*òdefaultf disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0 pwmpclkè+òdefaultf disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0 0 pwmpclkè,òdefaultf disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controllerq ²power-domain@7…-qpower-domain@8ÌÍ …./0qpower-domain@9 ÚÛÜ …123qpower-domain@10 ñò…456789qpower-domain@11 í…:qpower-domain@13 …;qpower-domain@14 …<=>qpower-domain@15 …?@ABCDEFqgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$�()' Œjobmmugpugpubus *G4okayœH²ªvideo-codec@fdea0400,rockchip,rk3568-vpuýê �‹Œvdpuîï aclkhclk¨I4 iommu@fdea0800,rockchip,rk3568-iommuýê@ �Š aclkifaceîï4 ¯²Irga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaýë€ �ZóôõaclkhclksclkS&$% ¼coreaxiahb4 video-codec@fdee0000,rockchip,rk3568-vepuýî �@ýþ aclkhclk¨J4 iommu@fdee0800,rockchip,rk3568-iommuýî@ �?ýþ aclkiface4 ¯²Jmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@ �d ÁÂŽ�biuciuciu-driveciu-sampleÈÓðÑ€Së¼resetokayáëö*K5òdefault èLMNCP]jx&„ethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ� Œmacirqeth_wake_irq@†‰‰ÇÃĉÈWstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refSì ¼stmmaceth‹ ‘O¡²PÅQØokayO‰† t‡RáinputîS ùrgmii-idòdefaultèTUVWXYmdio,snps,dwmac-mdio ethernet-phy@0,ethernet-phy-ieee802.3-c22òdefaultèZ N †  /[²Sstmmac-axi-config;EU²Orx-queues-confige²Pqueue0tx-queues-config{²Qqueue0vop@fe040000 þ0þ@‘vopgamma-lut �”(ÝÞßàá%aclkhclkdclk_vp0dclk_vp1dclk_vp2¨\4 ‹ okay,rockchip,rk3568-vopOßàtports ²port@0 endpoint@2›]²eport@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ? �”ÝÞ aclkiface¯4 okay²\dsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ �Dpclkèdphy^4 ¼apbS‹  disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ �Epclkédphy_4 ¼apbS‹  disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ  �-(æç“(Úiahbisfrcecrefòdefault è`ab4 O‹ tokay«c»d²ports port@0endpoint›e²]port@1endpoint›f²Ùqos@fe128000,rockchip,rk3568-qossysconþ€ ²-qos@fe138080,rockchip,rk3568-qossysconþ€€ ²<qos@fe138100,rockchip,rk3568-qossysconþ� ²=qos@fe138180,rockchip,rk3568-qossysconþ�€ ²>qos@fe148000,rockchip,rk3568-qossysconþ€ ².qos@fe148080,rockchip,rk3568-qossysconþ€€ ²/qos@fe148100,rockchip,rk3568-qossysconþ� ²0qos@fe150000,rockchip,rk3568-qossysconþ ²:qos@fe158000,rockchip,rk3568-qossysconþ€ ²4qos@fe158100,rockchip,rk3568-qossysconþ� ²5qos@fe158180,rockchip,rk3568-qossysconþ�€ ²6qos@fe158200,rockchip,rk3568-qossysconþ‚ ²7qos@fe158280,rockchip,rk3568-qossysconþ‚€ ²8qos@fe158300,rockchip,rk3568-qossysconþƒ ²9qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ ²?qos@fe190280,rockchip,rk3568-qossysconþ€ ²Cqos@fe190300,rockchip,rk3568-qossysconþ ²Dqos@fe190380,rockchip,rk3568-qossysconþ€ ²Eqos@fe190400,rockchip,rk3568-qossysconþ ²Fqos@fe198000,rockchip,rk3568-qossysconþ€ ²;qos@fe1a8000,rockchip,rk3568-qossysconþ€ ²1qos@fe1a8080,rockchip,rk3568-qossysconþ€€ ²2qos@fe1a8100,rockchip,rk3568-qossysconþ� ²3dfi@fe230000,rockchip,rk3568-dfiþ# � Ëgpcie@fe260000,rockchip,rk3568-pcie0À@þ&ô‘dbiapbconfig<�KJIHGŒsyspmcmsglegacyerrØ(�‚ƒ„…$aclk_mstaclk_slvaclk_dbipclkauxöpci�â`õhhhh   # 2 A I pcie-phy4Tôôô ô à@S¡¼pipe okayòdefaultèi /[ Sjlegacy-interrupt-controller�z �H²hmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@ �b °±Š‹biuciuciu-driveciu-sampleÈÓðÑ€SÔ¼resetokayáö c#ëòdefaultèklmn]xo„mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@ �c ²³Œ�biuciuciu-driveciu-sampleÈÓðÑ€SÖ¼reset disabledspi@fe300000 ,rockchip,sfcþ0@ �exvclk_sfchclk_sfcèpòdefaultokay flash@0,jedec,spi-nor l2ê ~ �mmc@fe310000,rockchip,rk3568-dwcmshcþ1 �O{}_ ëÂn6(|zy{}corebusaxiblocktimerokayáÓ ëÂ5òdefaultèqrstx„rng@fe388000,rockchip,rk3568-rngþ8€@po coreahbSmokayi2s@fe400000,rockchip,rk3568-i2s-tdmþ@ �4O=A_FÏqFÏq?C9mclk_txmclk_rxhclkJu  txSPQ ¼tx-mrx-m‹ tokay² i2s@fe410000,rockchip,rk3568-i2s-tdmþA �5OEI_FÏqFÏqGK:mclk_txmclk_rxhclkJuu  rxtxSRS ¼tx-mrx-m‹ òdefaultèvwxytokay ª²Ûi2s@fe420000,rockchip,rk3568-i2s-tdmþB �6OM_FÏqOO;mclk_txmclk_rxhclkJuu  txrxST¼tx-m‹ òdefaultèz{|}tokay ªi2s@fe430000,rockchip,rk3568-i2s-tdmþC �7SW<mclk_txmclk_rxhclkJuu  txrxSUV ¼tx-mrx-m‹ t disabledpdm@fe440000,rockchip,rk3568-pdmþD �LZYpdm_clkpdm_hclkJu   rxè~€�‚ƒòdefaultSX¼pdm-mt disabledspdif@fe460000,rockchip,rk3568-spdifþF �f mclkhclk_\Ju  txòdefaultè„t disableddma-controller@fe530000,arm,pl330arm,primecellþS@�  Å  apb_pclk ܲ'dma-controller@fe550000,arm,pl330arm,primecellþU@� Å  apb_pclk ܲui2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ �/HG i2cpclkè…òdefault  disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[ �0JI i2cpclkè†òdefault  disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\ �1LK i2cpclkè‡òdefault  disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ] �2NM i2cpclkèˆòdefault  disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^ �3PO i2cpclkè‰òdefault okayrtc@51,haoyu,hym8563Q#�( Õrtcic_32koutòdefaultèŠñwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ` �• tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa �gRQspiclkapb_pclkJ''  txrxòdefault 苌�  disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb �hTSspiclkapb_pclkJ''  txrxòdefault èŽ��  disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc �iVUspiclkapb_pclkJ''  txrxòdefault è‘’“  disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd �jXWspiclkapb_pclkJ''  txrxòdefault 蔕–  disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe �ubaudclkapb_pclkJ'' è—˜™òdefaultO\okay çbluetooth,brcm,bcm43438-btšlpo ÷›  ›  › òdefault èœ�ž ,& 8serial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf �v# baudclkapb_pclkJ''èŸòdefaultO\okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg �w'$baudclkapb_pclkJ''è òdefaultO\ disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh �x+(baudclkapb_pclkJ'' è¡òdefaultO\ disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi �y/,baudclkapb_pclkJ' ' è¢òdefaultO\ disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj �z30baudclkapb_pclkJ' ' è£òdefaultO\ disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk �{74baudclkapb_pclkJ''è¤òdefaultO\ disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl �|;8baudclkapb_pclkJ''è¥òdefaultO\ disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm �}?<baudclkapb_pclkJ''è¦òdefaultO\ disabledthermal-zonescpu-thermal Ed [è i§tripscpu_alert0 yp …Ðýpassive²¨cpu_alert1 y$ø …Ðýpassivecpu_crit ys …Ð ýcriticalcooling-mapsmap0 �¨0 • ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal E [è i§tripsgpu-threshold yp …Ðýpassivegpu-target y$ø …Ðýpassive²©gpu-crit ys …Ð ýcriticalcooling-mapsmap0 �© •ªÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq �sO_f@ ®`tsadcapb_pclkS�‚׋  ¤sòdefaultsleepè« »¬ Åokay Û ò²§saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr �]saradcapb_pclkS€ ¼saradc-apb okay ­pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþnZY pwmpclkè®òdefaultf disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþnZY pwmpclkè¯òdefaultf disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY pwmpclkè°òdefaultf disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0ZY pwmpclkè±òdefaultf disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo]\ pwmpclkè²òdefaultf disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo]\ pwmpclkè³òdefaultf disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\ pwmpclkè´òdefaultf disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0]\ pwmpclkèµòdefaultf disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp`_ pwmpclkè¶òdefaultf disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp`_ pwmpclkè·òdefaultf disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_ pwmpclkè¸òdefaultf disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0`_ pwmpclkè¹òdefaultf disabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ"} refapbpipeO"_õáSǼphy +º =» Sokay²phy@fe840000,rockchip,rk3568-naneng-combphyþ„%~ refapbpipeO%_õáSɼphy +º =¼ Sokay²phy@fe870000,rockchip,rk3568-csi-dphyþ‡ypclk SSº¼apb‹  disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ… refpclkz S4 ¼apbS» disabled²^mipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ† refpclk{ S4 ¼apbS¼ disabled²_usb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠphyclkÕclk_usbphy0_480m �‡ ^½(okay²host-port Sokay¾²otg-port Sokay¿²usb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹phyclkÕclk_usbphy1_480m �ˆ ^À(okayhost-port Sokay¾²otg-port Sokay¾²pinctrl,rockchip,rk3568-pinctrl‹ Ëg ²Ágpio@fdd60000,rockchip,gpio-bankýÖ �!.  n ~Á  Šz�²#gpio@fe740000,rockchip,gpio-bankþt �"cd n ~Á  Šz�²ãgpio@fe750000,rockchip,gpio-bankþu �#ef n ~Á@  Šz�²Ñgpio@fe760000,rockchip,gpio-bankþv �$gh n ~Á`  Šz�²[gpio@fe770000,rockchip,gpio-bankþw �%ij n ~Á€  Šz�²›pcfg-pull-up –²Äpcfg-pull-down £²Êpcfg-pull-none ²²Âpcfg-pull-none-drv-level-1 ² ¿²Æpcfg-pull-none-drv-level-2 ² ¿²Åpcfg-pull-none-drv-level-3 ² ¿²Épcfg-pull-up-drv-level-1 – ¿²Èpcfg-pull-up-drv-level-2 – ¿²Ãpcfg-pull-none-smt ² βÇacodecaudiopwmbt656bt1120camvcc_cam_en ã ²äcan0can0m0-pins ã  Â²Õcan1can1m0-pins ã²Öcan2can2m0-pins ã  ²×cifclk32kclk32k-out0 ã²cpuebcedpdpemmcemmc-bus8€ ã à ÃÃÃÃÃÃòqemmc-clk ãòremmc-cmd ãòsemmc-datastrobe ã²teth0eth1flashfspifspi-pins` ã²pgmac0gmac1gmac1m1-miim ã²Tgmac1m1-clkinout ã²Xgmac1m1-rx-bus20 ã ²Vgmac1m1-tx-bus20 ãÅŲUgmac1m1-rgmii-clk ãÂÆ²Wgmac1m1-rgmii-bus@ ãÂÂÅŲYgpuhdmitxhdmitxm1-cec ã²bhdmitx-scl ã²`hdmitx-sda ã²ai2c0i2c0-xfer ã Ç Ç²!i2c1i2c1-xfer ã Ç Ç²…i2c2i2c2m0-xfer ã ÇDz†i2c3i2c3m1-xfer ã ÇDz‡i2c4i2c4m1-xfer ã Ç Ç²ˆi2c5i2c5m0-xfer ã Ç Ç²‰i2s1i2s1m0-lrcktx ã²wi2s1m0-mclk ã²%i2s1m0-sclktx ã²vi2s1m0-sdi0 ã ²xi2s1m0-sdo0 ã²yi2s2i2s2m0-lrcktx ã²{i2s2m0-sclktx ã²zi2s2m0-sdi ã²|i2s2m0-sdo ã²}i2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pcie30x2m1-pins0 ã²Ðpdmpdmm0-clk ã²~pdmm0-clk1 ã²pdmm0-sdi0 ã ²€pdmm0-sdi1 ã ²�pdmm0-sdi2 ã ²‚pdmm0-sdi3 㲃pmicpmic_int ãIJ$pmupwm0pwm0m0-pins ã²)pwm1pwm1m0-pins ã²*pwm2pwm2m0-pins ã²+pwm3pwm3-pins ã²,pwm4pwm4-pins ã²®pwm5pwm5-pins 㲯pwm6pwm6-pins ã²°pwm7pwm7-pins ã²±pwm8pwm8m0-pins ã ²²pwm9pwm9m0-pins ã ²³pwm10pwm10m0-pins ã ²´pwm11pwm11m0-pins ã²µpwm12pwm12m0-pins ã²¶pwm13pwm13m0-pins ã²·pwm14pwm14m0-pins 㲸pwm15pwm15m0-pins ã²¹refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ ãÃÃÃòksdmmc0-clk ãòlsdmmc0-cmd ãòmsdmmc0-det ãIJnsdmmc1sdmmc2sdmmc2m0-bus4@ ãÃÃÃòLsdmmc2m0-clk ãòNsdmmc2m0-cmd ãòMspdifspdifm0-tx 㲄spi0spi0m0-pins0 ã ²�spi0m0-cs0 㲋spi0m0-cs1 㲌spi1spi1m0-pins0 ã ²�spi1m0-cs0 㲎spi1m0-cs1 ã²�spi2spi2m0-pins0 㲓spi2m0-cs0 㲑spi2m0-cs1 ã²’spi3spi3m0-pins0 ã  ²–spi3m0-cs0 ã²”spi3m0-cs1 㲕tsadctsadc-shutorg 㲫tsadc-pin 㲬uart0uart0-xfer ãÄIJ(uart1uart1m0-xfer ã Ä Ä²—uart1m0-ctsn 㲘uart1m0-rtsn ã ²™uart2uart2m0-xfer ãÄIJŸuart3uart3m0-xfer ãÄIJ uart4uart4m0-xfer ãÄIJ¡uart5uart5m0-xfer ãÄIJ¢uart6uart6m0-xfer ãÄIJ£uart7uart7m0-xfer ãÄIJ¤uart8uart8m0-xfer ãÄIJ¥uart9uart9m0-xfer ãÄIJ¦vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2displayvcc_mipi_en ã²åetherneteth_phy_rst ã²Zhym8563hym8563-int ãIJŠledsled_user_en ã²Úpciepcie-enable-h ã²Ýpcie-reset-h ã²iusbvcc5v0_usb_host_en ã²ßvcc5v0_usb_hub_en ã²ávcc5v0_usb_otg_en ã²âbtbt-enable ã ²žbt-host-wake ã ʲœbt-wake ã ²�sdio-pwrseqwifi-enable ã²Üsata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü–—˜satapmaliverxoob �^ sata-phy"4 disabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconýDzØqos@fe190080,rockchip,rk3568-qossysconþ€ ²@qos@fe190100,rockchip,rk3568-qossysconþ ²Aqos@fe190200,rockchip,rk3568-qossysconþ ²Bsyscon@fdcb8000%,rockchip,rk3568-pcie3-phy-grfsysconýË€²Ëphy@fe8c0000,rockchip,rk3568-pcie3-phyþŒ S&'wrefclk_mrefclk_npclkS¾¼phy ñËokay̲Îpcie@fe270000,rockchip,rk3568-pcie Ø(ˆ‰Š‹Œ$aclk_mstaclk_slvaclk_dbipclkauxöpci<� Ÿž�œŒsyspmcmsglegacyerr�â`õÍÍÍÍ   # 2 A IÎ pcie-phy40À@@þ'òTòòò ò à@@@‘dbiapbconfigS±¼pipe disabledlegacy-interrupt-controllerz� ��²Ípcie@fe280000,rockchip,rk3568-pcie Ø(��‘’“$aclk_mstaclk_slvaclk_dbipclkauxöpci<�¥¤£¢¡Œsyspmcmsglegacyerr�â`õÏÏÏÏ   # 2 A  IÎ pcie-phy40À€@þ(ðTððð ð à€€@‘dbiapbconfigSÁ¼pipeokayòdefaultèÐ /Ñ Sjlegacy-interrupt-controllerz� �¢²Ïethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ*�Œmacirqeth_wake_irq@‚……¸´µ…¹Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refS× ¼stmmaceth‹ ‘Ò¡²ÓÅÔØ disabledmdio,snps,dwmac-mdio stmmac-axi-config;EU²Òrx-queues-confige²Óqueue0tx-queues-config{²Ôqueue0can@fe570000,rockchip,rk3568v2-canfdþW �A@ baudpclkSUT ¼coreapbòdefaultèÕ disabledcan@fe580000,rockchip,rk3568v2-canfdþX �CB baudpclkSWV ¼coreapbòdefaultèÖ disabledcan@fe590000,rockchip,rk3568v2-canfdþY �ED baudpclkSYX ¼coreapbòdefaultè× disabledphy@fe820000,rockchip,rk3568-naneng-combphyþ‚| refapbpipeO_õáSżphy +º =Ø Sokay²chosen serial2:1500000n8hdmi-con,hdmi-connectorýaportendpoint›Ù²fexternal-gmac1-clock ,fixed-clockÅsY@ Õgmac1_clkin(²Rleds ,gpio-ledsled-0 5# heartbeat  heartbeatòdefaultèÚrk809-sound,simple-audio-cardLi2s 5Analog RK809esimple-audio-card,cpu†Ûsimple-audio-card,codec†šsdio-pwrseq,mmc-pwrseq-simpleš ext_clockòdefaultèÜ 3d JLK@ /[²Kvcc12v-dcin-regulator,regulator-fixed µvcc12v_dcinÄØ²Þpcie30-avdd0v9-regulator,regulator-fixedµpcie30_avdd0v9ÄØê »  » /&pcie30-avdd1v8-regulator,regulator-fixedµpcie30_avdd1v8ÄØêw@w@/&vcc3v3-pi6c-03-regulator,regulator-fixedµvcc3v3_pi6c_03ÄØê2Z 2Z /"²Ìvcc3v3-pcie-regulator,regulator-fixed ] 5#òdefaultèÝ µvcc3v3_pcieê2Z 2Z /"²jvcc3v3-sys-regulator,regulator-fixed µvcc3v3_sysÄØê2Z 2Z /Þ²&vcc5v0-sys-regulator,regulator-fixed µvcc5v0_sysÄØêLK@LK@/Þ²"vcc5v0-usb-regulator,regulator-fixed µvcc5v0_usbÄØêLK@LK@/Þ²àvcc5v0-usb-host-regulator,regulator-fixed ] p#òdefaultèßµvcc5v0_usb_hostêLK@LK@/ಾvcc5v0-usb-hub-regulator,regulator-fixed ] p#òdefaultèáµvcc5v0_usb_hubÄ/àvcc5v0-usb-otg-regulator,regulator-fixed ] p#òdefaultèâµvcc5v0_usb_otgêLK@LK@/ಿvcc-cam-regulator,regulator-fixed ] pã òdefaultèäµvcc_camê2Z 2Z /&regulator-state-mem:vcc-mipi-regulator,regulator-fixed ] p[òdefaultèå µvcc_mipiê2Z 2Z /&regulator-state-mem: interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendrockchip,system-power-controller#sound-dai-cellsvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencybus-widthdisable-wpcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modephy-supplyreset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesvpcie3v3-supplycd-gpiosspi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthdma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctsdevice-wakeup-gpioshost-wakeup-gpiosshutdown-gpiosvbat-supplyvddio-supplypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfstdout-pathfunctioncolorlinux,default-triggerpost-power-on-delay-mspower-off-delay-usenable-active-highgpio